SAA5233 [NXP]
Dual standard PDC decoder; 双重标准PDC解码器
| 型号： | SAA5233 |
| 厂家： | 
NXP |
| 描述： | Dual standard PDC decoder |
| 文件： | 总20页 (文件大小：86K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA5233
Dual standard PDC decoder
June 1994
Objective specification
File under Integrated Circuits, IC02
Philips Semiconductors
Philips Semiconductors
Objective specification
Dual standard PDC decoder
SAA5233
FEATURES
• Digital data slicer
• Acquisition and decoding of VPS data
(EBU PDC System A)
• Acquisition and decoding of Teletext packet 8/30/2 data
(EBU PDC System B)
• Separate storage of VPS data and packet 8/30/2
allowing dual standard PDC decoders
• I2C-bus interface with automatic word address
increment
• Programmable interrupt for data received
• Programmable error level detection
• Single +5 V power supply.
GENERAL DESCRIPTION
The SAA5233 is a dual standard Program Delivery Control
(PDC) decoder, allowing the reception and decoding of
both VPS data (EBU PDC System A) and Teletext packet
8/30/2 data (EBU PDC System B). It is intended for use in
European video recorders which are manually
programmed, so that they receive broadcast real time
switching signals for accurate timing of program recording.
QUICK REFERENCE DATA
SYMBOL
VDD
PARAMETER
MIN.
TYP.
MAX.
UNIT
supply voltage
supply current
4.5
−
5.0
30
5.5
45
−
V
IDD
mA
fclk
crystal input frequency
−
27
MHz
V
Vsync
Vvid(p-p)
CVBS sync voltage amplitude
0.1
0.7
0.3
1.0
0.6
1.4
CVBS video voltage amplitude
(peak-to-peak value)
V
Tamb
Tstg
operating ambient temperature
storage temperature
−20
−55
−
−
+70
°C
°C
+125
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
MATERIAL
PINS
16
PIN POSITION
DIP16
CODE
SAA5233P
SAA5233T
plastic
plastic
SOT38-1
20
SO20L
SOT163-1
June 1994
2
Philips Semiconductors
Objective specification
Dual standard PDC decoder
SAA5233
BLOCK DIAGRAM
SCL
SDA
12
13
2
14
I C BUS
MEMORY
INTERFACE
AND RAM
AD
INTERFACE
15
INTERRUPT
CONTROL
INT
SAA5233
4
V
8/30/2
ACQUISITION
AND
DD
TELETEXT
AND VPS
CONTROL
5
V
DECODING
SS1
9
V
SS2
VPS
ACQUISITION
AND
10
V
SS3
11
V
SS4
DECODING
DATA SLICER
AND CLOCK
16
V
SS5
REGENERATOR
POWER
ON RESET
PLL AND
TIMING
13.5 MHz
27 MHz
1.125 MHz
INPUT
CLAMP
AND SYNC
SEPARATOR
27 MHz
OSCILLATOR
AND DIVIDER
ANALOGUE
TO DIGITAL
CONVERTER
6
7
8
1
2
3
MLB725
OSCOUT OSCIN OSCGND
CVBS BLACK IREF
Fig.1 Block diagram; pin numbers for DIP16.
June 1994
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Philips Semiconductors
Objective specification
Dual standard PDC decoder
SAA5233
PINNING
PIN
SYMBOL
DESCRIPTION
DIP16
SO20L
CVBS
BLACK
n.c.
1
2
1
2
composite video input
video black level storage pin
not connected
−
3
IREF
VDD
3
4
reference current input
+5 V supply
4
5
VSS1
OSCOUT
n.c.
5
6
0 V ground 1 (main ground pin)
27 MHz crystal oscillator output
not connected
6
7
−
8
OSCIN
OSCGND
VSS2
VSS3
n.c.
7
9
27 MHz crystal oscillator input
27 MHz crystal oscillator ground
0 V ground 2; connect to VSS1
0 V ground 3; connect to VSS1
not connected
8
10
11
12
13
14
15
16
17
18
19
20
9
10
−
VSS4
SCL
11
12
13
−
connect to VSS1 in normal operation
serial clock open-drain input for I2C-bus
serial data open-drain input/output for I2C-bus
SDA
i.c.
internally connected; do not connect in normal operation
programmable I2C-bus address bit input
interrupt open-drain output
AD
14
15
16
INT
VSS5
connect to VSS1 in normal operation
handbook, halfpage
handbook, halfpage
V
1
2
20
19
18
CVBS
BLACK
n.c.
V
SS5
1
2
3
4
16
CVBS
BLACK
IREF
SS5
INT
AD
15
14
INT
AD
3
IREF
4
17 i.c.
V
13 SDA
DD
SAA5233
V
16
15
14
13
12
11
V
SDA
5
5
6
7
8
12
DD
SCL
SS1
SAA5233
V
V
6
OSCOUT
OSCIN
SCL
V
11
SS1
SS4
V
V
10
9
OSCOUT
n.c.
7
SS3
SS2
SS4
OSCGND
8
n.c.
V
MLB726
OSCIN
OSCGND
9
SS3
V
10
SS2
MLB727
Fig.2 Pin configuration; DIP16.
Fig.3 Pin configuration; SO20L.
June 1994
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Philips Semiconductors
Objective specification
Dual standard PDC decoder
SAA5233
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDD
PARAMETER
MIN.
−0.3
MAX.
+6.5
UNIT
supply voltage
V
V
V
VImax
VOmax
IIOmax
IOmax
Tamb
Tstg
maximum input voltage (any input)
maximum output voltage (any output)
maximum DC input or output diode current
maximum output current (any output)
operating ambient temperature
storage temperature
−0.3
−0.3
−
VDD + 0.3
VDD + 0.3
±20
mA
mA
°C
−
±10
−20
−55
+70
+125
°C
June 1994
5
Philips Semiconductors
Objective specification
Dual standard PDC decoder
SAA5233
QUALITY AND RELIABILITY
This device will meet the requirements of the “Philips Semiconductors General Quality Specification SNW-FQ-611E” in
accordance with “Quality Reference Pocketbook (order number 9398 510 34011)”. The principal requirements are as
shown in Tables 1 to 4.
Group A
Table 1 Acceptance tests per lot.
TEST
REQUIREMENTS(1)
Mechanical
Electrical
cumulative target: <100 ppm
cumulative target: <100 ppm
Group B
Table 2 Processability tests (by package family).
TEST
REQUIREMENTS(1)
Solderability
<7% LTPD
<15% LTPD
<15% LTPD
Mechanical
Solder heat resistance
Group C
Table 3 Reliability tests (by process family).
TEST
CONDITIONS
REQUIREMENTS(1)
Operational life
Humidity life
168 hours at Tj = 150 °C
<1500 FPM; equivalent to <100 FITS
at Tj = 70 °C
temperature, humidity, bias
(1000 hours, 85 °C, 85% RH or
equivalent test)
<2000 FPM
Temperature cycling performance
Tstg(min) to Tstg(max)
<2000 FPM
Table 4 Reliability tests (by device type).
TEST
CONDITIONS
REQUIREMENTS(1)
ESD and latch-up
ESD Human body model
<15% LTPD
2000 V; 100 pF; 1.5 kΩ
ESD Machine model
200 V; 200 pF; 0 Ω
<15% LTPD
<15% LTPD
latch-up 100 mA; 1.5 × VDD
(absolute maximum)
Note to Tables 1 to 4.
1. ppm = fraction of defective devices, in parts per million.
LTPD = Lot Tolerance Percent Defective.
FPM = fraction of devices failing at test condition, in Failures Per Million.
FITS = Failures In Time Standard.
June 1994
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Philips Semiconductors
Objective specification
Dual standard PDC decoder
SAA5233
CHARACTERISTICS
VDD = 4.5 to 5.5 V; VSS = 0 V; Tamb = −20 to +70 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN.
TYP.
MAX.
UNIT
Supplies
VDD
IDD
supply voltage
4.5
5.0
30
5.5
V
supply current
−
45
mA
Inputs
CVBS
Vsync
sync voltage amplitude
0.1
0.7
0.3
1.0
0.6
1.4
V
V
Vvid(p-p)
video voltage amplitude
(peak-to-peak value)
Vdat(text)
Teletext data voltage
amplitude
0.30
0.46
0.70
V
Vdat(vps)
Zsource
ZI
VPS data voltage amplitude
source impedance
input impedance
0.30
−
0.50
−
0.70
250
−
V
Ω
2.5
−
5.0
−
kΩ
pF
CI
input capacitance
10
IREF
Rgnd
resistor to ground
−
−
27
−
−
kΩ
VIREF
input reference voltage
0.5VDD
V
AD
VIL
VIH
ILI
LOW level input voltage
HIGH level input voltage
input leakage current
input capacitance
−0.3
0.7VDD
−10
−
−
−
−
−
+0.3VDD
VDD + 0.3
+10
V
V
VI = 0 to VDD
µA
pF
CI
10
SCL
VIL
VIH
ILI
CI
fclk
tr
LOW level input voltage
HIGH level input voltage
input leakage current
input capacitance
clock frequency
−0.3
−
−
−
−
−
−
−
+0.3VDD
VDD + 0.3
+10
V
0.7VDD
V
VI = 0 to VDD
−10
−
µA
pF
kHz
ns
ns
10
0
100
input rise time
0.3VDD to 0.7VDD
0.7VDD to 0.3VDD
−
1000
300
tf
input fall time
−
June 1994
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Philips Semiconductors
Objective specification
Dual standard PDC decoder
SAA5233
SYMBOL
Outputs
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
INT (OPEN-DRAIN OUTPUT)
VPU
VOL
IOL
CL
pull-up voltage at pin
−
0
−
−
−
−
−
−
−
−
VDD
LOW level output voltage
LOW level output current
load capacitance
IOL = 3 mA
0.4
4.0
V
mA
pF
ns
400
100
tf
output fall time
CL = 100 pF;
0.7VDD to 0.3VDD
Inputs/Outputs
BLACK
Cblack
ILI
storage capacitor to ground
input leakage current
−
100
−
nF
VI = 0 to VDD
−10
−
+10
µA
SDA (OPEN-DRAIN OUTPUT)
VIL
VIH
ILI
CI
CL
tr
LOW level input voltage
−0.3
−
−
−
−
−
−
−
−
−
+0.3VDD
VDD + 0.3
+10
V
HIGH level input voltage
input leakage current
input capacitance
load capacitance
input rise time
0.7VDD
V
VI = 0 to VDD
−10
−
µA
pF
pF
ns
ns
V
10
−
400
0.3VDD to 0.7VDD
0.7VDD to 0.3VDD
IOL = 3 mA
−
1000
300
tf
input fall time
−
VOL
tf
LOW level output voltage
output fall time
0
0.4
CL = 400 pF;
−
200
ns
0.7VDD to 0.3VDD
CRYSTAL OSCILLATOR (OSCIN; OSCOUT)
Vosc
oscillator voltage amplitude
(peak-to-peak value)
−
1.0
−
V
Gv
CI
small signal voltage gain
input capacitance
−
−
−
1.0
−
−
10
−
pF
pF
Cfb
feedback capacitance
1
June 1994
8
Philips Semiconductors
Objective specification
Dual standard PDC decoder
SAA5233
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I2C-bus timing (see Fig.4)
fclk
SCL clock frequency
0
−
−
100
kHz
tBUF
bus free time between a
STOP and START
4.7
−
µs
tHD;STA
tLOW
repeated START hold time note 1
SCL clock LOW time
4.0
4.7
4.0
4.7
−
−
−
−
−
−
−
−
µs
µs
µs
µs
tHIGH
SCL clock HIGH time
tSU;STA
set-up time for a repeated
START
tHD;DAT
tSU;DAT
tr
data hold time
0
−
−
−
−
−
−
ns
ns
ns
ns
µs
data set-up time
250
−
−
SDA, SCL input rise time
SDA, SCL input fall time
set-up time for STOP
0.3VDD to 0.7VDD
0.7VDD to 0.3VDD
1000
300
−
tf
−
tSU;STO
4.0
Note
1. After this time the first clock pulse is generated.
a
SDA
t
t
f
t
BUF
LOW
SCL
SDA
t
HIGH
t
t
HD;STA
r
t
HD;DAT
t
SU;DAT
MBC764
t
SU;STA
t
SU;STO
Fig.4 I2C-bus timing diagram.
June 1994
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Philips Semiconductors
Objective specification
Dual standard PDC decoder
SAA5233
data is biphase decoded and stored with 4 data bits stored
in the lower nibble of each byte, in the same way as
Teletext packet 8/30/2 data; see Tables 11 and 12. In
addition to the VCR data, Word 4
(Program Source Identification, ASCII sequential) is
stored, which may be useful for future applications.
FUNCTIONAL DESCRIPTION
Control of device
The function of the device is controlled via the I2C-bus.
Pin AD provides a choice of two alternative addresses.
The PDC acquisition section requires little software control
apart from enabling the interrupts which occur when data
is found. Interrupts can be enabled for either Teletext
packet 8/30/2 or VPS and both can be enabled to allow for
the presence of both standards being transmitted on the
same TV channel. The interrupt register is accessed as
address 01 WRITE, see Section “Register 01: Interrupt
(reset state X00X XXXX)”.
The stored data is read via the I2C-bus in the normal way.
Multiple reception/majority error correction of the data is
the responsibility of the control software, the device simply
stores the data as transmitted after Hamming or biphase
decoding. As both VPS and Teletext packet 8/30/2 signals
are stored separately, it is possible to deal with future
situations where both EBU PDC System A and EBU PDC
System B transmissions may be present on the same TV
channel, the defaults and level of service being chosen by
the software control.
When an interrupt is signalled, a bit is set in the status
register to indicate its source. Information about the
received PDC data is given in the status register D5 and
D6. The microcontroller must service the ‘data received’
interrupts within 40 ms (VPS) or 200 ms
Error indication
Indication of errors in the received data is given in two
ways and is programmable by setting bit D4 in the control
register.
(Teletext packet 8/30/2), since new data may be written
after this period. The status register is accessed as
address 00 READ; see Section
“Register 00:Control/Status (reset state XXX0 XX00)”.
When the status register has been read the data received
flags and interrupt signal are reset.
The first is a flag to indicate Hamming or biphase errors
and is stored with the related data in bit 0 of the upper
nibble of the data byte.
Data of both types is constantly received and stored, but
can be selectively acquired by setting bits D1 and D0 of the
control register. This allows acquisition of only Teletext
packet 8/30/2 on every VBI line or only VPS data on every
VBI line. The control register is accessed as address
00 WRITE, see Section “Register 00:Control/Status (reset
state XXX0 XX00)”.
The second is no interrupt which is sent to the
microcontroller but the data signal quality bit (D7) is set.
The level of interrupt is controlled by the Interrupt
Error Level bit which is D4 of the control register. If this bit
is not set then an interrupt only occurs if an error free line
of either Teletext packet 8/30/2 or VPS data is received
and stored in RAM. If this bit is set then an interrupt occurs
if the correct framing code and Teletext packet header
8/30/2 is found, or the correct start code for VPS data is
found. The data is then stored in the RAM with any errors
indicated in the upper nibble. This may be used by more
sophisticated software, which could decide the importance
of an error in a particular nibble.
Storage of PDC data
The PDC data memory is accessed at address 02 (HEX)
to 31 (HEX). The exact addresses of Teletext packet
8/30/2 and VPS data is shown in Table 5.
TELETEXT DATA
The Teletext packet 8/30/2 data is stored after hardware
Hamming correction. There are 4 data bits stored in the
lower nibble of each byte in address 11 (HEX)
I2C-bus interface
FEATURES
• Standard I2C-bus slave transceiver
• Operates from 0 to 100 kHz
to 1D (HEX); see Table 13, in the order shown in Table 5.
The status message, which is odd parity coded, is stored
as a byte which represents a Teletext character in address
1E (HEX) to 31 (HEX); see Table 14.
• Acknowledge function is performed
• Auto-increment between registers and direct addressing
• Selectable I2C-bus slave address dependent on
VPS DATA
address pin AD.
The VPS data from Line 16 is stored in register address
02 (HEX) to 0F (HEX) in the order shown in Table 5. VPS
June 1994
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Philips Semiconductors
Objective specification
Dual standard PDC decoder
SAA5233
Register map
The data received when address locations 00 (HEX) to 31 (HEX) are read or written is shown in Table 5.
Table 5 Register map.
ADDRESS (HEX)
DATA(1)
control/status
interrupt
ADDRESSING
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
:
direct
direct
VPS B5
direct/auto-increments to 03
direct/auto-increments to 04
direct/auto-increments to 05
direct/auto-increments to 06
direct/auto-increments to 07
direct/auto-increments to 08
direct/auto-increments to 09
direct/auto-increments to 0A
direct/auto-increments to 0B
direct/auto-increments to 0C
direct/auto-increments to 0D
direct/auto-increments to 0E
direct/auto-increments to 0F
stop value
VPS B5
VPS B11
VPS B11
VPS B12
VPS B12
VPS B13
VPS B13
VPS B14
VPS B14
VPS B15
VPS B15
VPS B4
VPS B4
−
direct
8/30/2 B13
8/30/2 B14
8/30/2 B15
8/30/2 B16
8/30/2 B17
8/30/2 B18
8/30/2 B19
8/30/2 B20
8/30/2 B21
8/30/2 B22
8/30/2 B23
8/30/2 B24
8/30/2 B25
status message
:
direct/auto-increments to 12
direct/auto-increments to 13
direct/auto-increments to 14
direct/auto-increments to 15
direct/auto-increments to 16
direct/auto-increments to 17
direct/auto-increments to 18
direct/auto-increments to 19
direct/auto-increments to 1A
direct/auto-increments to 1B
direct/auto-increments to 1C
direct/auto-increments to 1D
direct/auto-increments to 1E
direct/auto-increments to 1F
direct/auto-increments
31
status message
stop value
Note
1. For the address range 02H to 0FH, even addresses hold the least significant nibble and odd addresses hold the most
significant nibble. BXX refers to byte definitions, EBU specification of the domestic video PDC system.
June 1994
11
Philips Semiconductors
Objective specification
Dual standard PDC decoder
SAA5233
Register 00:Control/Status (reset state XXX0 XX00)
Register 00 is split into two parts. The control part (WRITE only) consisting of bits D4, D1 and D0 and status part (READ
only) consisting of bits D7 to D5.
Table 6 Register 00.
D7
−
D6
−
D5
−
D4
IEL
−
D3
−
D2
−
D1
D0
ACQ 8/30/2 ACQ VPS
DSQ
8/30/2 RF
VPS RF
−
−
−
−
Table 7 Register 00 bit description.
SYMBOL
IEL
BIT
FUNCTION
D4
Interrupt Error Level.
When logic 0, signal only completely valid data lines from Teletext packet 8/30/2
received and VPS received flags.
When logic 1, signal valid framing code and Teletext packet header 8/30/2 received or
valid start codeword for VPS received.
ACQ 8/30/2
ACQ VPS
D1
D0
Acquire 8/30/2.
Acquire VPS.
Allows selective decoding of either Teletext packet 8/30/2 data or VPS data. If both are
set to the same value the system automatically selects the format being transmitted
(see Table 8).
DSQ
D7
D6
Data Signal Quality.
When logic 1, good Teletext or VPS data signal is being received.
When logic 0, no Teletext or VPS data signal is being received.
8/30/2 RF
8/30/2 Received Flag.
When logic 1, and IEL (D4) = logic 0 an error-free Teletext packet 8/30/2 has been
received, Hamming decoded and stored in the RAM. When logic 1, and IEL(D4) =
logic 1 a Teletext packet with a valid framing code and 8/30/2 header has been
received, Hamming decoded and stored in RAM.
When logic 0 no Teletext packet 8/30/2 data received.
VPS RF
D5
VPS Received Flag.
When logic 1, and IEL(D4) = logic 0, an error-free VPS data line has been received,
biphase decoded and stored in the RAM. When logic 1, and IEL(D4) = logic 1 a VPS
data line with valid start code has been received, biphase decoded and stored in RAM.
When logic 0 no VPS data received.
Table 8 Selection of Teletext packet 8/30/2 data or VPS data.
ACQ 8/30/2
ACQ VPS
FUNCTION
use automatic selection algorithm for line 16
0
0
1
1
0
1
0
1
acquire only VPS data on every VBI line
acquire only 8/30/2 data on every line 16
use automatic selection algorithm for line 16
June 1994
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Philips Semiconductors
Objective specification
Dual standard PDC decoder
SAA5233
Register 01: Interrupt (reset state X00X XXXX)
Register R01 is WRITE only.
Table 9 Register 01.
D7
D6
D5
D4
D3
D2
D1
D0
−
8/30/2 IE
VPS IE
−
−
−
−
−
Table 10 Register 01 bit description.
SYMBOL
BIT
FUNCTION
8/30/2 IE
D6
8/30/2 Interrupt Enable.
This allows the reception of Teletext packet 8/30/2 data to be signalled on the INT pin.
When logic 0 reception of Teletext packet 8/30/2 data is not signalled on INT pin.
When logic 1 reception of Teletext packet 8/30/2 data is signalled on INT pin.
VPS IE
D5
VPS Interrupt Enable.
This allows the reception of VPS data to be signalled on the INT pin.
When logic 0 reception of VPS data is not signalled on INT pin.
When logic 1 reception of VPS data is signalled on INT pin.
Register 02 to 0F (HEX): VPS data bytes
A single VPS data bytes is stored as two memory bytes, the least significant nibble of both memory bytes is the data
making up the single VPS data byte. The most significant nibble of each memory byte is used to indicate a biphase error
in the least significant nibble. This is indicated by the least significant bit being set, the top three bits are not used and
are fixed to logic 0 (see Table 11).
Table 11 VPS data bytes.
ADDRESS (HEX)
REGISTER
DATA
02
03
VPS B5 least significant nibble
VPS B5 most significant nibble
0000 1100(1)
0000 0101(1)
Note
1. Equivalent to VPS B5 0101 1100 (MSB to LSB).
Table 12 Register 02.
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
BIPHASE
DATA BIT 3 DATA BIT 2 DATA BIT 1 DATA BIT 0
ERROR BIT
Register 11 to 1D (HEX): Teletext packet 8/30/2 data bytes
Data is stored as single bytes. The four least significant bits represent the data. The fifth bit if set indicates a Hamming
error in the stored data. The top three bits of the byte are not used and are fixed to logic 0.
Table 13 Register 11.
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
HAMMING
DATA BIT 3 DATA BIT 2 DATA BIT 1 DATA BIT 0
ERROR BIT
June 1994
13
Philips Semiconductors
Objective specification
Dual standard PDC decoder
SAA5233
Register 1E to 31D (HEX): Status display message
Data is stored as bytes which represent a Teletext character. The data is odd parity checked, if a parity error occurs this
causes the byte not to be written to the RAM. The MSB is not used and is fixed to logic 0.
Table 14 Register 11.
D7
D6
D5
D4
D3
D2
D1
D0
−
DATA BIT 6 DATA BIT 5 DATA BIT 4 DATA BIT 3 DATA BIT 2 DATA BIT 1 DATA BIT 0
I2C-bus slave address
Table 16 Increment between registers.
The slave address for the device can take one of two
values dependent on the state of the input pin AD.
ADDRESS
CONTENTS
02 to 0F (HEX) VPS data bytes
11 to 31 (HEX) Teletext packet 8/30/2 data bytes and
Status display message
Table 15 Device address.
AD
0
SLAVE ADDRESS
0010 001X(1)
Addressing any register in either of these ranges will
initialize an increment until the final stop value provided
each byte is acknowledged by the receiver.
1
0010 000X(1)
Note
Initialization during power-up
1. Where X is the R/W bit.
The device has an internal power-on reset unit which is
used to reset the I2C-bus interface to be a slave
transceiver. It also initializes the device to receive only
completely valid Teletext packet 8/30/2 and VPS data. The
interrupt signals for both Teletext packet 8/30/2 and VPS
are disabled.
I2C-bus increment
The I2C-bus will also increment between registers as listed
in Table 16
June 1994
14
Philips Semiconductors
Objective specification
Dual standard PDC decoder
SAA5233
APPLICATION INFORMATION
100 nF
5 V
1
2
3
16
15
14
13
12
11
10
9
video
input
V
CVBS
BLACK
IREF
SS5
4.7
kΩ
100 nF
220 Ω
INT to
microcontroller
INT
27 kΩ
AD
4
5
6
(1)
V
5 V
SDA
SCL
DD
2
100
nF
33
µF
I C bus
SAA5233
to microcontroller
V
SS1
V
OSCOUT
OSCIN
SS4
SS3
SS2
10
pF
100
nF
15 pF
4.7 µH
7
8
V
V
3.3
kΩ
OSCGND
27 MHz 3rd
overtone
MLB728
(1) I2C-bus address 0010 001R/W.
Fig.5 Application diagram; DIL16.
Table 17 Crystal characteristics.
SYMBOL
PARAMETER
TYP.
MAX.
UNIT
Crystal (27 MHz, 3rd overtone)
C1
C0
CL
Rr
series capacitance
1.7
5.2
20
−
−
pF
pF
pF
Ω
parallel capacitance
load capacitance
resonance resistance
series resistance
ageing
−
−
50
R1
Xa
Xj
20
−
−
Ω
year−1
±5 × 10−6
±25 × 10−6
±25 × 10−6
adjustment tolerance
drift
−
Xd
−
June 1994
15
Philips Semiconductors
Objective specification
Dual standard PDC decoder
SAA5233
PACKAGE OUTLINES
22.00
21.35
8.25
7.80
3.7
max
4.7
max
3.9
3.4
0.51
min
2.2
max
0.254 M
2.54
(7x)
0.32 max
0.53
max
7.62
1.4 max
9.5
8.3
MSA254
16
9
8
6.48
6.14
1
Dimensions in mm.
Fig.6 Plastic dual in-line package; 16 leads (300 mil); DIP16, SOT38-1.
June 1994
16
Philips Semiconductors
Objective specification
Dual standard PDC decoder
SAA5233
13.0
12.6
7.6
7.4
A
10.65
10.00
0.1 S
S
0.9
0.4
(4x)
20
11
1.1
1.0
2.45
2.25
2.65
2.35
0.3
0.1
0.32
0.23
pin 1
index
1.1
0.5
o
0 to 8
1
10
detail A
MBC234 - 1
0.49
0.36
0.25 M
(20x)
1.27
Dimensions in mm.
Fig.7 Plastic small outline package; 20 leads; large body; SO20L, SOT163-1.
June 1994
17
Philips Semiconductors
Objective specification
Dual standard PDC decoder
SAA5233
SOLDERING
BY SOLDER PASTE REFLOW
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
Plastic dual in-line packages
BY DIP OR WAVE
The maximum permissible temperature of the solder is
260 °C; this temperature must not be in contact with the
joint for more than 5 s. The total contact time of successive
solder waves must not exceed 5 s.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified storage maximum. If the printed-circuit board has
been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within
the permissible limit.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)
Apply a low-voltage soldering iron below the seating plane
(or not more than 2 mm above it). If its temperature is
below 300 °C, it must not be in contact for more than 10 s;
if between 300 and 400 °C, for not more than 5 s.
Plastic small-outline packages
BY WAVE
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
June 1994
18
Philips Semiconductors
Objective specification
Dual standard PDC decoder
SAA5233
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
June 1994
19
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SCD32
© Philips Electronics N.V. 1994
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533061/01/1500/pp20
Date of release: June 1994
9397 736 20011
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Document order number:
Philips Semiconductors
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