SAA4995WP-T [NXP]
IC SPECIALTY CONSUMER CIRCUIT, PQCC44, PLASTIC, SOT-187, LCC-44, Consumer IC:Other;
| 型号： | SAA4995WP-T |
| 厂家： | 
NXP |
| 描述： | IC SPECIALTY CONSUMER CIRCUIT, PQCC44, PLASTIC, SOT-187, LCC-44, Consumer IC:Other 消费电路 商用集成电路 |
| 文件： | 总16页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA4995WP
PANorama-IC (PAN-IC)
1997 Jun 10
Preliminary specification
File under Integrated Circuits, IC02
Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
SAA4995WP
FEATURES
GENERAL DESCRIPTION
• Horizontal sample rate conversion in both zoom and
compress direction, with a sample rate conversion factor
between 0.5 and 2 (in 384 steps)
The PAN-IC is an add-on IC to be used, for example,
between analog-to-digital conversion and a serial (field)
memory. The device performs the following tasks:
• Dynamic sample rate conversion for panorama mode
display e.g. 4 : 3 material on a 16 : 9 display
• Linear horizontal sample rate conversion in both zoom
and compress direction, with a sample rate conversion
factor between 0.5 and 2
• Dynamic sample rate conversion for amaronap mode
display of e.g. 16 : 9 material on a 4 : 3 display
• Dynamic sample rate conversion for panorama mode
display of e.g. 4 : 3 material on a 16 : 9 display
• Operates with 1fh and 2fh
• Dynamic sample rate conversion for amaronap mode
display of e.g. 16 : 9 material on a 4 : 3 display.
• Programmable via microcontroller SNERT
(Synchronous No parity Eight bit Receive Transmit) bus.
The PAN-IC has the ability to increase the data rate from
the ADC to a maximum of twice the data rate at the output.
To achieve this a clock rate at twice the normal output
clock rate is needed to write data to the memory.
All actions to generate a lower data rate, produces disable
cycles in Write Enable (WE).
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
5.5
UNIT
VDD
IDD
supply voltage
supply current
4.5
−
5
V
110
−
−
mA
MHz
°C
fCLK
Tamb
operating clock frequency
−
33
70
operating ambient temperature
0
−
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
SAA4995WP
PLCC44 plastic leaded chip carrier; 44 leads
SOT187-2
1997 Jun 10
2
Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
SAA4995WP
BLOCK DIAGRAM
V
V
V
V
DD4 GND4
CL16
5
CLK
31
DD1 GND1
10 12
DD2 GND2
15 16
DD3 GND3
33 30
6
32
Y
Y
I7
I0
O7
to
37 to 44
29 to 22
SECAM
NOTCH
VPD
FRONT-END
VPD
BACK-END
to
Y
MUX
Y
O0
CL16
CLK
notch
U
V
/U
V
U
/V
I1 I0
O0 O1
1 to 4
21 to 18
VPD
FRONT-END
VPD
BACK-END
and
and
/V
/U
I1 I0
O0 O1
SAA4995WP
CL16
CLK
∆UV
∆Y
'0'
C
1
MUX
INTEGRATOR
INTEGRATOR
DTO
+
C
2
C
0
17
14
WE
O
7
WE
I
LINE CONTROL
WE
od
13
11
CL16
CLK
T1
T0
34
35
36
SNDA
SNCL
VRST
C0
C1
C2
SNERT BUS INTERFACE
8
9
MGK176
TEST
SCANIN
Fig.1 Block diagram.
3
1997 Jun 10
Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
SAA4995WP
PINNING
SYMBOL
YO2
PIN
DESCRIPTION
SYMBOL
UI1
PIN
DESCRIPTION
U input bit 1
24
25
26
27
28
29
30
31
32
33
34
luminance output bit 2
1
2
YO3
luminance output bit 3
luminance output bit 4
luminance output bit 5
luminance output bit 6
luminance output bit 7
ground 3
UI0
U input bit 0
YO4
VI1
3
V input bit 1
YO5
VI0
4
V input bit 0
YO6
CL16
VDD4
WEI
TEST
SCANIN
VDD1
T0
5
half system clock
supply voltage 4
write enable input
test mode switch
input for scan chain
supply voltage 1
test mode switch 0
ground 1
YO7
6
GND3
CLK
GND4
VDD3
SNDA
7
system clock
8
ground 4
9
supply voltage 3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
data input from interface
SNERT bus
GND1
T1
SNCL
VRST
35
36
clock input from interface
SNERT bus
test mode switch 1
write enable odd samples
supply voltage 2
ground 2
WEod
VDD2
GND2
WEO
VO0
reset input in the vertical
blanking interval
YI7
YI6
YI5
YI4
YI3
YI2
YI1
YI0
37
38
39
40
41
42
43
44
luminance input bit 7
luminance input bit 6
luminance input bit 5
luminance input bit 4
luminance input bit 3
luminance input bit 2
luminance input bit 1
luminance input bit 0
write enable output
V output bit 0
VO1
V output bit 1
UO0
U output bit 0
UO1
U output bit 1
YO0
luminance output bit 0
luminance output bit 1
YO1
1997 Jun 10
4
Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
SAA4995WP
7
8
39
38
37
36
WE
Y
Y
Y
I
I5
I6
I7
TEST
9
SCANIN
10
11
12
V
VRST
DD1
T0
35 SNCL
34 SDNA
GND1
SAA4995WP
T1 13
33 V
DD3
32 GND4
31 CLK
WE
V
14
od
15
DD2
GND2 16
30 GND3
WE 17
O
29 Y
O7
MGK175
Fig.2 Pin configuration.
In the centre of the line a high quality compression (e.g.
with a factor 4⁄3) has to be made. Towards the sides of the
line, more and more expansion and compression
respectively is made. The sample rate conversion factor
over a line will have a bathtub shape, with parameters
illustrated in Fig.3:
FUNCTIONAL DESCRIPTION
The PAN-IC is an add-on IC to be used, for example,
between analog-to-digital conversion and a serial (field)
memory. The device performs the following tasks:
• Linear horizontal sample rate conversion in both zoom
and compress direction, with a sample rate conversion
factor between 0.5 and 2
• X0l and X0r, where in-between a constant data rate is
maintained (area I) and starting points from where a
curve can be programmed for its 2nd derivative (in
areas II and V)
• Dynamic sample rate conversion for panorama mode
display of e.g. 4 : 3 material on a 16 : 9 display
• Dynamic sample rate conversion for amaronap mode
• X1l and X1r, points from where a new curve can be
display of e.g. 16 : 9 material on a 4 : 3 display.
programmed for its 2nd derivative (for areas III and IV)
• X2l corresponds to the first sample in the output data
stream, defined by start of WEI
The PAN-IC has the ability to increase the data rate from
the ADC (maximum 16 MHz in a 16/32 MHz concept) to a
maximum of twice the data rate. For this, a 32 MHz clock
rate is needed to write to the memory. All actions to
generate a lower data rate produces disable cycles in write
enable.
• X2r corresponds to the last sample in the output data
stream, defined by the programmed number of samples
• C1, which controls the second derivatives of the data
rate in areas II and V
In panorama and amaronap modes, the sample rate
conversion factor is modulated along the video line.
• C2, which controls the second derivatives of the data
rate in areas III and IV.
1997 Jun 10
5
Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
SAA4995WP
There is an offset in the programmed number of samples
compared to the effective number of samples per line.
Interpolation function
The interpolation for phase positions between the original
samples, is achieved with a variable phase delay filter with
10 taps for luminance signals and 4 taps for chrominance
signals. For luminance the PAN-IC supplies samples up to
32 MHz. For chrominance the PAN-IC supplies each
U and V samples with a data rate of 8 MHz (max).
• Effective number of Y samples = 4 × (programmed
number of samples + 1)
• Effective number of UV samples = 1 × (programmed
number of samples + 1)
SECAM Y notch
Processing control in the PAN-IC
A notch filter at the Y input of the PAN-IC can be switched
on. The purpose of this filter is to prevent artefacts from
scan velocity modulation with SECAM inputs. The notch
filter is an FIR filter with coefficients (−1 0 3 0 3 0 −1).
When fs = 16 MHz, the notch frequency is 4 MHz; the
maximum gain of the filter is +3 dB at 2 and 6 MHz.
The compress factor (see Fig.4) at any position in the lines
is a function of the dynamically changing DTO-increment.
When DTOincr = 255, the sample rate is divided by 2; when
DTOincr = 0, the sample rate in the PAN-IC remains
unchanged; when DTOincr = −128, the sample rate is
doubled.
Timing
Control of number of samples per line
The inputs are related to CL16 (half system clock). This
clock is used for reference in the PAN-IC from the CL16
pin. The system clock must have a fixed phase relationship
to the CL16 enable signal (one clock system).
Three possibilities exist for the relationship between the
end of WEI and the required number of samples per line for
storage in the field memory:
•
WEI negative edge coincides with the required last
sample in the line; standard operation.
Relationship of WE to video data
• WEI negative edge is reached before the present last
sample in the line was required; extra dummy WE cycles
will be generated at the maximum rate (zoom factor 2)
to arrive at the required number of samples per line.
WE inputs and outputs may be used with either coincident
or advanced WE to video timing (see Fig.5). The advanced
WE to video timing is applicable to field memories, such as
the SAA4955TJ. The input and output WEs of the PAN-IC
can be programmed separately to either timing by the
in-phase and out-phase bits.
• The required number of samples per line is reached
before WEI negative edge; the DTO calculations will
continue until the required number of samples is
reached, but without generation of WE cycles.
Odd/even sample distribution
The PAN-IC usually delivers a complete YUV data stream
to one receiving device, e.g. a field memory. Optionally, a
data stream can be split into odd and even samples, to be
received by two receiving devices.
The programmed number of samples per line is thus
always realized, independent of all other controls (unless
the line period becomes insufficient to store up to the last
sample in a line). When using odd/even sample
distribution, the programmed number of samples refers to
the number of samples in each data stream.
Consequently, the total number of samples is twice as
many.
The relationship between Y and UV samples is then
non-trivial (see Tables 1 to 4).
1997 Jun 10
6
Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
SAA4995WP
NO SPLITTING INTO ODD AND EVEN SAMPLE STREAM
Table 1 Normal output YUV data stream
E
Y0
O
E
O
E
O
E
O
E
O
E
O
E
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
0
0
0
0
4
4
4
4
8
8
8
8
12
UV76
UV54
UV32
UV10
UV76
UV54
UV32
UV10
UV76
UV54
UV32
UV10
UV76
SPLITTING INTO ODD AND EVEN SAMPLE STREAM
Keeps corresponding parts of the UV samples in one stream (UV0, UV8, etc. in even stream and UV4, UV12, etc. in odd
stream): The odd data stream misses two samples at the start of a line and has two dummy samples at the end of the
line, to keep the UV format correct and maintain the same line length as for the even stream (In the odd stream, the last
two Y samples and the last U and V samples of a line are not valid).
Table 2 Even YUV data stream
E
Y0
−
E
−
E
−
E
−
E
−
E
−
E
−
−
Y2
−
−
Y4
−
−
Y6
−
−
Y8
−
−
Y10
−
−
Y12
0
0
0
0
8
8
12
UV76
UV54
UV32
UV10
UV76
UV54
UV32
Table 3 Odd YUV data stream
−
−
−
−
−
O
−
−
−
O
Y7
−
−
−
O
Y9
−
−
−
O
Y11
−
−
−
−
−
−
−
−
−
−
−
−
−
Y5
4
4
4
4
UV76
UV54
UV32
UV10
The even and odd data streams given in Tables 2 and 3 can be distributed to two receiving devices with input enable
facilities. A separate input signal for each of the receiving devices must then be applied while the even YUV data stream
and odd YUV data stream are again combined.
COMBINED ODD/EVEN OUTPUT YUV DATA STREAM
Table 4 Distribution with odd/even input enable signals
E
−
E
−
E
−
E
O
E
O
E
O
E
Y0
−
−
Y2
−
−
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
0
0
0
4
0
4
8
4
8
4
8
UV76
UV54
UV32
UV76
UV10
UV54
UV75
UV32
UV54
UV10
UV32
1997 Jun 10
7
Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
SAA4995WP
active period
area:
IV
V
I
II
III
sample
rate
C
C
2
2
C
C
1
1
C
0
positions:
X
X
X
X
X
X
2r
2I
1I
0I
0r
1r
MGK177
Fig.3 Panorama mode.
MGK178
2
compress
factor
1
0.5
−256
−128
0
256
DTO
incr
Fig.4 Compress factor.
8
1997 Jun 10
Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
SAA4995WP
CL16
WE
I
with in-phase = 0
with in-phase = 1
WE
I
YUV
I
CLK
WE /WE
O
od
od
with out-phase = 0
with out-phase = 1
WE /WE
O
YUV
O
MGK179
Fig.5 WE timing.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDD
PARAMETER
supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+6.5
UNIT
V
Vi, Vo
Io/out
P/out
Tstg
input and output voltages
−0.5
−
VDD + 0.5
20
V
output current per output pin
power dissipation per output pin
storage temperature
mA
−
100
mW
°C
°C
V
−55
−40
−
+140
+85
Tamb
VESD
operating ambient temperature
electrostatic handling for all pins
note 1
note 2
±2000
±300
−
V
Notes
1. Human body model: C = 100 pF, R = 1.5 kΩ, V = 2 kV.
2. Machine model: C = 200 pF, R = 0 Ω, V = 300 V.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
thermal resistance from junction to ambient in free air
VALUE
UNIT
50
K/W
1997 Jun 10
9
Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
SAA4995WP
CHARACTERISTICS
V
DD = 5.0 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL PARAMETER
supply voltage
CONDITIONS
MIN.
4.5
TYP.
MAX.
UNIT
VDD
IDD
5
5.5
−
V
supply current
−
110
mA
MHz
MHz
V
fCLK
fCL16
VIL
operating frequency (CLK)
operating frequency (CL16)
LOW level input voltage
HIGH level input voltage
input capacitance
−
−
33
−
−
1⁄2fCLK
−
−
0.8
VDD
15
0.4
−
VIH
2.0
−
−
V
Ci
10
−
pF
V
VOL
VOH
tsu(i)(D)
LOW level output voltage
HIGH level output voltage
Io = 4 mA
Io = −4 mA
−
2.6
8
3.4
−
V
input set-up time with respect to CL16 except pins SNDA, SNCL,
−
ns
rising edge
VRST and CLK; see Fig.6
th(i)(CL16)
input hold time with respect to CL16
rising edge
except pins SNDA, SNCL,
VRST and CLK; see Fig.6
0
7
3
−
−
−
−
−
−
ns
ns
ns
tsu(i)(CL16) input set-up time with respect to CLK
rising edge
see Fig.6
see Fig.6
CL = 7 pF
th(i)(CL16)
input hold time with respect to CLK
rising edge
th(o)
td
output hold time with respect to CLK
5
−
0
−
−
−
−
−
−
ns
ns
°C
°C
output delay time with respect to CLK CL = 15 pF
operating ambient temperature
19
70
125
Tamb
Tj
junction temperature
CLK
t
t
h(i)(CL16)
h(i)(CL16)
t
t
su(i)(CL16)
su(i)(CL16)
CL16
data
input
t
su(i)(D)
t
h(i)(D)
data
output
data valid
data valid
MGK180
t
h(o)
t
d
Fig.6 Clock timing.
1997 Jun 10
10
Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
SAA4995WP
MICROCONTROLLER BUS TIMING (SNERT BUS)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX. UNIT
Tcy(SNCL) SNCL cycle time
see Fig.7
see Fig.7
see Fig.7
see Fig.7
see Fig.7
1
−
µs
ns
ns
ns
ns
tsu(i)
th(i)
th(o)(D)
td
input data set-up time
input data hold time
output data hold time
output data delay time
90
50
0
−
−
−
−
700
T
SNCL
cy(SNCL)
t
t
su(i)
h(i)
SNDA
(receiver
mode)
LSB
t
d
SNDA
(transmitter
mode)
data
valid
data
valid
data
valid
data
valid
data
valid
MGK181
t
h(o)(D)
Fig.7 SNERT bus interface timing.
MICROCONTROLLER BUS CONTROL (SNERT BUS)
The following control table applies (Table 5), for control via the microcontroller bus (SNERT bus, consisting of SNCL,
SNDA and VRST signals). Data communication is by writing to the PAN-IC (address 40H to 48H) and reading from it
(address 49H)
Table 5 SNERT-bus control
ADDRESS
(HEX)
BIT
POSITION
FUNCTION
# OF BITS
REMARKS
40
41
42
43
44
X1l
8
7 : 0
7 : 0
7 : 0
7 : 0
7 : 0
definition of X1l with a resolution of 4 samples; see Fig.3 and
note 1
X0l
X0r
X1r
8
8
8
8
definition of X0l with a resolution of 4 samples; see Fig.3 and
note 1
definition of X0r with a resolution of 4 samples; see Fig.3 and
note 1
definition of X1r with a resolution of 4 samples; see Fig.3 and
note 1
output samples
per line
resolution of 4 luminance samples; actual #
samples = (programmed # samples + 1) × 4; note 2
1997 Jun 10
11
Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
SAA4995WP
ADDRESS
BIT
POSITION
FUNCTION
# OF BITS
REMARKS
(HEX)
45
C0
8
6
7 : 0
constant DTOincr value for area I, MSB extended by zoom bit
at address 48 (twos complement value); see Figs 3 and 4
46
47
C1
5 : 0
2nd derivatives for DTOincr for areas II and V
(twos complement value); see Figs 3 and 4
distribution
C2
1
6
6
enables odd/even sample distribution; see Tables 1 to 4
5 : 0
2nd derivatives for DTOincr for areas III and IV
(twos complement value)
test 1
notch
1
6
7
test bit, must be logic 0 in normal operation
1
SECAM Y notch on/off (logic 1 = on, logic 0 = off)
logic 1 = zoom, logic 0 = compress in area I
logic 1 = shifted relation WE_IN to input data; see Fig.5
logic 1 = shifted relation WEO/WEod to output data; see Fig.5
circuitry is initialized at VRST pulse
48
zoom bit
in-phase
out-phase
init
1
0
1
1
1
2
1
3
vrst_xfer
keep
1
4
new settings are activated at VRST pulse
1
5
compression curve is kept from last active line in field
test bit, must be logic 0 in normal operation
test 2
1
1
6
adapt
7
adapt bit, must be logic 0 in normal operation
PAN-IC identifies by pulling all bits LOW (hardware cluck)
49
Notes
identify read
8 read bits
7 : 0
1. For a symmetrical bathtub curve Xnl + Xnr = output samples per line + 1.
2. WEI falling edge delay to the WEO latest sample should not be equal to the pipeline delay. This can be controlled
with the WEI length via the microcontroller.
TEST
The test mode can be chosen via pins TEST, T0 and T1.
Table 6 Test modes
PIN NAME
MODE
TEST
T1
T0
Functional test
Test mode on
0
1
X(1)
X(1)
X(1)
X(1)
Note
1. X = don’t care.
1997 Jun 10
12
Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
SAA4995WP
PACKAGE OUTLINE
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
e
e
E
D
y
X
A
39
29
Z
E
b
28
p
40
b
1
w
M
44
1
H
E
E
pin 1 index
A
A
1
A
4
e
(A )
3
6
18
k
1
β
L
p
k
detail X
7
17
v
M
A
e
Z
D
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
(1)
(1)
A
min.
A
max.
k
1
max.
Z
Z
E
(1)
(1)
1
4
D
UNIT
mm
A
A
b
D
E
e
e
e
H
H
k
L
p
v
w
y
β
b
D
E
D
E
3
p
1
max. max.
4.57
4.19
0.81 16.66 16.66
0.66 16.51 16.51
16.00 16.00 17.65 17.65 1.22
14.99 14.99 17.40 17.40 1.07
1.44
1.02
0.53
0.33
0.51
0.51 0.25 3.05
0.020 0.01 0.12
1.27
0.05
0.18 0.18 0.10 2.16 2.16
o
45
0.180
0.165
0.032 0.656 0.656
0.026 0.650 0.650
0.630 0.630 0.695 0.695 0.048
0.590 0.590 0.685 0.685 0.042
0.057
0.040
0.021
0.013
inches
0.020
0.007 0.007 0.004 0.085 0.085
Note
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-02-25
SOT187-2
112E10
MO-047AC
1997 Jun 10
13
Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
SAA4995WP
SOLDERING
Introduction
Wave soldering
Wave soldering techniques can be used for all PLCC
packages if the following conditions are observed:
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream corners.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all PLCC
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
The choice of heating method may be influenced by larger
PLCC packages (44 leads, or more). If infrared or vapour
phase heating is used and the large packages are not
absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9398 510 63011).
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1997 Jun 10
14
Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
SAA4995WP
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of this specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Jun 10
15
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Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/20/01/pp16
Date of release: 1997 Jun 10
Document order number: 9397 750 01609
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