BF1205 [NXP]
Dual N-channel dual gate MOS-FET; 双N沟道双栅MOS -FET
| 型号： | BF1205 |
| 厂家： | 
NXP |
| 描述： | Dual N-channel dual gate MOS-FET |
| 文件： | 总24页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DISCRETE SEMICONDUCTORS
DATA SHEET
andbook, halfpage
BF1205
Dual N-channel dual gate
MOS-FET
Product specification
2003 Sep 30
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
FEATURES
PINNING - SOT363
PIN
• Two low noise gain controlled amplifiers in a single
package. One with a fully integrated bias and one with a
partly integrated bias
DESCRIPTION
1
2
3
4
5
6
gate 1 (a)
gate 2
• Internal switch reduces the number of external
components
gate 1 (b)
drain (b)
source
• Superior cross-modulation performance during AGC
• High forward transfer admittance
drain (a)
• High forward transfer admittance to input capacitance
ratio.
APPLICATIONS
d (a)
s
d (b)
handbook, halfpage
• Gain controlled low noise amplifiers for VHF and UHF
applications with 5 V supply voltage, such as digital and
analog television tuners and professional
communications equipment.
6
5
4
AMP
a
AMP
b
DESCRIPTION
1
2
3
The BF1205 is a combination of two equal dual gate
MOS-FET amplifiers with shared source and gate 2 leads
and an integrated switch. The integrated switch is
operated by the gate 1 bias of amplifier b. The source and
substrate are interconnected. Internal bias circuits enable
DC stabilization and a very good cross-modulation
performance during AGC. Integrated diodes between the
gates and source protect against excessive input voltage
surges. The transistor is encapsulated in SOT363
micro-miniature plastic package.
Top view
g1 (a)
g2
g1 (b)
MGX429
Marking code: L4-.
Fig.1 Simplified outline and symbol.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
BF1205
−
Plastic surface mounted package; 6 leads
SOT363
2003 Sep 30
2
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Per MOS-FET; unless otherwise specified
VDS
ID
drain-source voltage
drain current (DC)
−
−
−
−
−
−
10
V
30
mA
mW
Ptot
total power dissipation
Ts ≤ 102 °C; temperature at the
200
soldering point of the source lead
yfs
forward transfer admittance
input capacitance at gate 1
ID = 12 mA
26
−
31
40
2.3
2.5
−
mS
pF
Cig1-ss
amp. a: f = 1 MHz
amp. b: f = 1 MHz
f = 1 MHz
1.8
2.0
20
−
pF
Crss
NF
reverse transfer capacitance
noise figure
−
fF
amp. a: f = 800 MHz
amp. b: f = 800 MHz
−
1.2
1.4
102
1.9
2.1
−
dB
−
dB
Xmod
cross-modulation
amp. a: input level for k = 1% at
40 dB AGC
98
dBµV
amp. b: input level for k = 1% at
40 dB AGC
100 105
−
dBµV
°C
Tj
junction temperature
−
−
150
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX. UNIT
Per MOS-FET; unless otherwise specified
VDS
ID
drain-source voltage
drain current (DC)
gate 1 current
−
−
−
−
−
10
V
30
mA
mA
mA
mW
°C
IG1
IG2
Ptot
Tstg
Tj
±10
±10
200
+150
150
gate 2 current
total power dissipation
storage temperature
junction temperature
Ts ≤ 102 °C; note
−65
−
°C
Note
1. Ts is the temperature at the soldering point of the source lead.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
VALUE
UNIT
K/W
Rth j-s
thermal resistance from junction to soldering point
240
2003 Sep 30
3
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
MGS359
250
handbook, halfpage
P
tot
(mW)
200
150
100
50
0
0
50
100
150
200
T
(°C)
s
Fig.2 Power derating curve.
STATIC CHARACTERISTICS
Tj = 25 °C; per MOS-FET; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX. UNIT
V(BR)DSS
drain-source breakdown voltage
amp. a: VG1-S = VG2-S = 0 V; ID = 10 µA 10
−
V
amp. b: VG1-S = VG2-S = 0 V; ID = 10 µA
VGS = VDS = 0 V; IG1-S = 10 mA
VGS = VDS = 0 V; IG2-S = 10 mA
VG2-S = VDS = 0 V; IS-G1 = 10 mA
VG1-S = VDS = 0 V; IS-G2 = 10 mA
VDS = 5 V; VG2-S = 4 V; ID = 100 µA
VDS = 5 V; VG1-S = 5 V; ID = 100 µA
7
−
V
V(BR)G1-SS gate-source breakdown voltage
V(BR)G2-SS gate-source breakdown voltage
6
10
10
1.5
1.5
1
V
6
V
V(F)S-G1
V(F)S-G2
VG1-S(th)
VG2-S(th)
IDSX
forward source-gate voltage
forward source-gate voltage
gate-source threshold voltage
gate-source threshold voltage
drain-source current
0.5
0.5
0.3
0.4
8
V
V
V
1.0
16
V
amp. a: VG2-S = 4 V; VDS = 5 V;
mA
RG1 = 150 kΩ; note 1
amp. b: VG2-S = 4 V; VDS = 5 V;
8
16
mA
RG1 = 150 kΩ; note 2
IG1-S
gate cut-off current
gate cut-off current
amp. a: VG1-S = 5 V; VG2-S = VDS = 0 V
amp. b: VG1-S = 5 V; VG2-S = VDS = 0 V
VG2-S = 4 V; VG1-S = VDS = 0 V
−
−
−
50
50
20
nA
nA
nA
IG2-S
Note
1. RG1 connects gate 1 (b) to VGG = 0 V (see Fig.4).
2. RG1 connects gate 1 (b) to VGG = 5 V (see Fig.4).
2003 Sep 30
4
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
MGX430
16
handbook, halfpage
I
D
(mA)
(1)
(2)
handbook, halfpage
12
g1 (a)
d (a)
s
g2
(3)
8
g1 (b)
d (b)
R
G1
4
V
MGX431
GG
(4)
(5)
(6)
0
0
1
2
3
4
5
V
(V)
GG
(1) ID (b); RG1 = 120 kΩ.
(2) ID (b); RG1 = 150 kΩ.
(4) ID (a); RG1 = 180 kΩ.
(5) ID (a); RG1 = 150 kΩ.
(3)
ID (b); RG1 = 180 kΩ.
(6) ID (a); RG1 = 120 kΩ.
VGG = 5 V: amplifier a is OFF; amplifier b is ON.
VGG = 0 V: amplifier a is ON; amplifier b is OFF.
Fig.3 Drain currents of MOS-FET a and b as
functions of VGG (see Fig.4).
Fig.4 Functional diagram
2003 Sep 30
5
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
DYNAMIC CHARACTERISTICS AMPLIFIER a
Common source; Tamb = 25 °C; VG2-S = 4 V; VDS = 5 V; ID = 12 mA; note 1
SYMBOL
PARAMETER
CONDITIONS
MIN.
26
TYP. MAX. UNIT
yfs
forward transfer admittance
input capacitance at gate 1
input capacitance at gate 2
output capacitance
Tj = 25 °C
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
31
40
2.3
−
mS
pF
pF
pF
fF
Cig1-ss
Cig2-ss
Coss
Crss
−
1.8
3.3
0.75
20
−
−
−
reverse transfer capacitance
power gain
−
−
Gtr
f = 200 MHz; GS = 2 mS; BS = BS(opt)
GL = 0.5 mS; BL = BL(opt)
;
;
31
35
39
dB
f = 400 MHz; GS = 2 mS; BS = BS(opt)
GL = 1 mS; BL = BL(opt)
27
22
31
26
35
30
dB
dB
f = 800 MHz; GS = 3.3 mS; BS = BS(opt)
;
GL = 1 mS; BL = BL(opt)
NF
noise figure
f = 10.7 MHz; GS = 20 mS; BS = 0
f = 400 MHz; YS = YS(opt)
−
4
−
dB
−
1.1
1.2
−
1.7
1.9
−
dB
f = 800 MHz; YS = YS(opt)
−
dB
Xmod
cross-modulation
input level for k = 1% at 0 dB AGC;
fw = 50 MHz; funw = 60 MHz; note 2
90
dBµV
input level for k = 1% at 10 dB AGC;
fw = 50 MHz; funw = 60 MHz; note 2
−
90
−
−
dBµV
dBµV
input level for k = 1% at 40 dB AGC;
fw = 50 MHz; funw = 60 MHz; note 2
98
102
Notes
1. For the MOS-FET not in use: VG1-S (b) = 0 V; VDS (b) = 0 V.
2. Measured in Fig.13 test circuit.
2003 Sep 30
6
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
GRAPHS FOR AMPLIFIER a
MGX432
MGX433
(1)
20
24
handbook, halfpage
handbook, halfpage
(3)
(2)
(4)
I
(5)
(6)
D
(mA)
I
D
(mA)
(1)
15
(2)
(3)
16
10
5
(4)
(5)
8
(6)
(7)
(7)
0
0
0
0
0.4
0.8
1.2
1.6
2
2
4
6
8
10
(V)
V
(V)
V
DS
G1-S
(1) VG1-S (a) = 1.4 V.
(2) VG1-S (a) = 1.3 V.
(3) VG1-S (a) = 1.2 V.
(4) VG1-S (a) = 1.1 V.
(5) VG1-S (a) = 1 V.
(6) VG1-S (a) = 0.9 V.
(7) VG1-S (a) = 0.8 V.
(1) VG2-S = 4 V.
(5) VG2-S = 2 V.
(2) VG2-S = 3.5 V.
(3) VG2-S = 3 V.
(4) VG2-S = 2.5 V.
(6) VG2-S = 1.5 V.
(7) VG2-S = 1 V.
VDS (a) = 5 V; VG1-S (b) = VDS (b) = 0 V; Tj = 25 °C.
VG2-S = 4 V; VG1-S (b) = VDS (b) = 0 V; Tj = 25 °C.
Fig.5 Transfer characteristics; typical values;
amplifier a.
Fig.6 Output characteristics; typical values;
amplifier a.
2003 Sep 30
7
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
MGX434
MGX435
40
12
handbook, halfpage
handbook, halfpage
y
(1) (2)
fs
(mS)
I
(a)
D
(mA)
(3)
(4)
30
8
20
10
0
4
0
(5)
0
4
8
12
16
I
20
(mA)
0
10
20
30
40
(b) (µA)
I
D
D
(1) VG2-S = 4 V.
(4) VG2-S = 2.5 V.
(5) VG2-S = 2 V.
(2) VG2-S = 3.5 V.
(3) VG2-S = 3 V.
VDS (a) = 5 V; VG2-S = 4 V; VDS (b) = 5 V; VG1-S (b) = 0 V; Tj = 25 °C.
VDS (a) = 5 V; VG1-S (b) = VDS (b) = 0 V; Tj = 25 °C.
Fig.8 Drain current as a function of internal G1
current (current in pin drain (b) if MOS-FET
(b) is switched off); typical values; amplifier a.
Fig.7 Forward transfer admittance as a function
of drain current; typical values; amplifier a.
2003 Sep 30
8
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
MGX436
MGX437
12
120
(1)
handbook, halfpage
I
handbook, halfpage
D
(mA)
10
(2)
(3)
V
unw
(dBµV)
(4)
(5)
110
8
6
4
2
100
90
0
0
80
0
2
4
6
20
40
gain reduction (dB)
60
V
= V
(V)
DS
GG
(1) VDS (b) = 5 V.
(2) VDS (b) = 4.5 V.
(3) VDS (b) = 4 V.
(4) VDS (b) = 3.5 V.
(5) VDS (b) = 3 V.
VDS (a) = VDS (b) = 5 V; VG1-S (b) = 0 V; f w = 50 MHz;
VDS (a) = 5 V; VG1-S (b) = 0 V; Gate 1 (a) = open; Tj = 25 °C.
f unw = 60 MHz; Tamb = 25 °C; see Fig.13.
Fig.9 Drain current as a function of gate 2 and
drain supply voltage; typical values;
amplifier a.
Fig.10 Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical values;
amplifier a.
2003 Sep 30
9
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
MGX438
MGX439
0
16
handbook, halfpage
handbook, halfpage
I
gain
reduction
(dB)
D
(mA)
12
20
40
60
8
4
0
0
0
1
2
3
4
20
40
60
V
(V)
AGC
gain reduction (dB)
VDS (a) = VDS (b) = 5 V; VG1-S (b) = 0 V; f = 50 MHz; Tamb = 25 °C;
see Fig.13.
VDS (a) = VDS (b) = 5 V; VG1-S (b) = 0 V; f = 50 MHz; see Fig.13.
Fig.11 Gain reduction as a function of AGC
voltage; typical values; amplifier a.
Fig.12 Drain current as a function of gain
reduction; typical values; amplifier a.
V
(a)
h
DS
5 V
V
AGC
4.7 nF
L1
2.2 µH
10 kΩ
4.7 nF
4.7 nF
4.7 nF
g1 (a)
d (a)
R
R
GEN
50 Ω
L
50 Ω
g2
s
50 Ω
BF1205
V
i
4.7 nF
g1 (b)
d (b)
L2
2.2 µH
50 Ω
R
G1
150 kΩ
4.7 nF
V
V
(b)
GG
0 V
DS
5 V
MGX440
Fig.13 Cross-modulation test set-up for amplifier a.
10
2003 Sep 30
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
MGX442
MGX441
2
2
2
10
10
−10
handbook, halfpage
handbook, halfpage
y
is
(mS)
y
ϕ
|
|
fs
fs
(mS)
(deg)
10
y
|
|
fs
b
is
1
10
−10
g
is
ϕ
−1
fs
10
−2
10
1
10
−1
2
3
2
3
10
10
10
10
10
f (MHz)
f (MHz)
VDS (a) = 5 V; VG2-S (a) = 4 V; VDS (b) = VG1-S (b) = 0 V;
ID (a) = 12 mA.
VDS (a) = 5 V; VG2-S (a) = 4 V; VDS (b) = VG1-S (b) = 0 V;
ID (a) = 12 mA.
Fig.15 Forward transfer admittance and phase as
a function of frequency; typical values;
amplifier a.
Fig.14 Input admittance as a function of frequency;
typical values; amplifier a.
MGX443
3
MGX444
−10
3
10
10
handbook, halfpage
handbook, halfpage
ϕ
rs
y
y
|
|
rs
os
(deg)
(µS)
(mS)
ϕ
b
rs
2
2
os
−10
10
1
y
|
|
g
rs
os
−1
−10
−1
10
10
10
−2
1
10
2
3
2
3
10
10
10
10
10
f (MHz)
f (MHz)
VDS (a) = 5 V; VG2-S (a) = 4 V; VDS (b) = VG1-S (b) = 0 V;
ID (a) = 12 mA.
VDS (a) = 5 V; VG2-S (a) = 4 V; VDS (b) = VG1-S (b) = 0 V;
ID (a) = 12 mA.
Fig.16 Reverse transfer admittance and phase as
a function of frequency; typical values;
amplifier a.
Fig.17 Output admittance as a function of
frequency; typical values; amplifier a.
2003 Sep 30
11
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
Scattering parameters: amplifier a
VDS (a) = 5 V; VG2-S = 4 V; ID (a) = 12 mA; VDS (b) = 0 V; VG-1S (b) = 0 V; Tamb = 25 °C
s11
s21
s12
s22
f
MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE
(MHz)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
50
100
200
300
400
500
600
700
800
900
1000
0.997
0.995
0.988
0.976
0.963
0.944
0.924
0.900
0.874
0.846
0.817
−3.70
−7.37
3.15
3.15
3.12
3.09
3.04
2.99
2.94
2.87
2.81
2.73
2.65
175.99
171.92
163.99
156.06
148.32
140.52
132.88
125.30
117.79
110.29
102.91
0.00067
0.00132
0.00262
0.00373
0.00471
0.00557
0.00624
0.00669
0.00701
0.00705
0.00688
86.39
84.34
79.71
75.29
71.43
66.89
63.52
60.09
59.58
52.42
49.17
0.992
0.991
0.990
0.988
0.985
0.982
0.978
0.975
0.972
0.968
0.965
−1.38
−2.83
−14.64
−21.85
−28.95
−35.98
−42.90
−49.77
−56.61
−63.18
−69.84
−5.62
−8.40
−11.15
−13.88
−16.65
−19.35
−22.08
−24.87
−27.63
Noise data
V
DS (a) = 5 V; VG2-S = 4 V; ID (a) = 12 mA; VDS (b) = 0 V; VG-1S (b) = 0 V; Tamb = 25 °C
GAMMA OPT
(ratio)
f
F MIN
(dB)
Rn
(Ω)
(MHz)
(deg)
400
800
1.1
1.2
0.719
0.628
16.16
32.7
31.18
29.74
DYNAMIC CHARACTERISTICS AMPLIFIER b
Common source; Tamb = 25 °C; VG2-S = 4 V; VDS = 5 V; ID = 12 mA
SYMBOL
PARAMETER
CONDITIONS
MIN.
26
TYP. MAX. UNIT
yfs
forward transfer admittance
input capacitance at gate 1
input capacitance at gate 2
output capacitance
Tj = 25 °C
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
31
40
2.5
−
mS
pF
pF
pF
fF
Cig1-ss
Cig2-ss
Coss
Crss
−
2.0
3.3
0.85
20
−
−
−
reverse transfer capacitance
power gain
−
−
Gtr
f = 200 MHz; GS = 2 mS; BS = BS(opt)
GL = 0.5 mS; BL = BL(opt); note 1
;
;
30
34
38
dB
f = 400 MHz; GS = 2 mS; BS = BS(opt)
GL = 1 mS; BL = BL(opt); note 1
27
22
31
26
35
30
dB
dB
f = 800 MHz; GS = 3.3 mS; BS = BS(opt)
;
GL = 1 mS; BL = BL(opt); note 1
NF
noise figure
f = 10.7 MHz; GS = 20 mS; BS = 0
f = 400 MHz; YS = YS(opt)
−
−
−
4
−
dB
dB
dB
1.3
1.4
1.9
2.1
f = 800 MHz; YS = YS(opt)
2003 Sep 30
12
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
SYMBOL
PARAMETER
cross-modulation
CONDITIONS
MIN.
90
TYP. MAX. UNIT
Xmod
input level for k = 1% at 0 dB AGC;
fw = 50 MHz; funw = 60 MHz; note 2
−
−
−
−
dBµV
dBµV
dBµV
input level for k = 1% at 10 dB AGC;
fw = 50 MHz; funw = 60 MHz; note 2
−
92
105
input level for k = 1% at 40 dB AGC;
fw = 50 MHz; funw = 60 MHz; note 2
100
Notes
1. For the MOS-FET not in use: VG1-S (a) = 0; VDS (a) = 0.
2. Measured in test circuit Fig.30.
GRAPHS FOR AMPLIFIER b
MGX445
MGX446
20
24
handbook, halfpage
handbook, halfpage
(3)
(4)
I
(5)
D
(mA)
(2)
(1)
I
D
(mA)
(1)
15
(2)
(3)
16
(6)
10
5
(4)
(5)
8
(6)
(7)
(7)
0
0
0
0
0.4
0.8
1.2
1.6
V
2
(V)
2
4
6
8
10
(V)
V
DS
G1-S
(1) VG2-S = 4 V.
(5) VG2-S = 2 V.
(1) VG1-S (b) = 1.4 V.
(2) VG1-S (b) = 1.3 V.
(3) VG1-S (b) = 1.2 V.
(5) VG1-S (b) = 1 V.
(2) VG2-S = 3.5 V.
(6) VG2-S = 1.5 V.
(6) VG1-S (b) = 0.9 V.
(7) VG1-S (b) = 0.8 V.
(3)
VG2-S = 3 V.
(7) VG2-S = 1 V.
(4) VG2-S = 2.5 V.
(4)
VG1-S (b) = 1.1 V.
VDS (b) = 5 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 °C.
VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 °C.
Fig.18 Transfer characteristics; typical values;
amplifier b.
Fig.19 Output characteristics; typical values;
amplifier b.
2003 Sep 30
13
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
MGX448
MGX447
60
40
handbook, halfpage
handbook, halfpage
(2)
(1)
(3)
(4)
y
(1) (2)
fs
(mS)
I
G1
(µA)
(3)
(4)
30
(5)
40
20
10
20
(6)
(7)
(5)
0
0
0
0
0.4
0.8
1.2
1.6
G1-S
2
4
8
12
16
I
20
(mA)
V
(V)
D
(1) VG2-S = 4 V.
(5) VG2-S = 2 V.
(1)
V
G2-S = 4 V.
(4) VG2-S = 2.5 V.
(5) VG2-S = 2 V.
(2) VG2-S = 3.5 V.
(3) VG2-S = 3 V.
(4) VG2-S = 2.5 V.
(6) VG2-S = 1.5 V.
(7) VG2-S = 1 V.
(2) VG2-S = 3.5 V.
(3) VG2-S = 3 V.
VDS (b) = 5 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 °C.
VDS (b) = 5 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 °C.
Fig.20 Gate 1 current as a function of gate 1
voltage; typical values; amplifier b.
Fig.21 Forward transfer admittance as a function
of drain current; typical values; amplifier b.
2003 Sep 30
14
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
MGX449
MGX450
20
16
handbook, halfpage
handbook, halfpage
I
D
(mA)
16
I
D
(mA)
12
12
8
8
4
4
0
0
0
0
10
20
30
40
I
50
(µA)
1
2
3
4
5
V
(V)
G1
GG
VDS (b) = 5 V; VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V;
Tj = 25 °C; RG1 (b) = 150 kΩ (connected to VGG); see Fig.4.
VDS (b) = 5 V; VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 °C.
Fig.22 Drain current as a function of gate 1 current;
typical values; amplifier b.
Fig.23 Drain current as a function of gate 1 supply
voltage (VGG); typical values; amplifier b.
2003 Sep 30
15
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
MGX451
MGX452
20
16
(1)
handbook, halfpage
handbook, halfpage
I
D
(mA)
16
I
D
(mA)
(2)
(1)
(2)
(3)
(4)
12
(3)
(4)
(5)
(5)
(6)
12
8
8
4
(7)
(8)
4
0
0
0
0
2
4
6
(V)
2
4
6
V
= V
V
(V)
GG
DS
G2-S
(1)
(2)
R
G1 (b) = 68 kΩ.
G1 (b) = 82 kΩ.
(5) RG1 (b) = 150 kΩ.
(6) G1 (b) = 180 kΩ.
R
R
(3) RG1 (b) = 100 kΩ.
(4) RG1 (b) = 120 kΩ.
(7) RG1 (b) = 220 kΩ.
(8) RG1 (b) = 270 kΩ.
(1)
(2) VGG = 4.5 V.
(3) GG = 4.0 V.
V
GG = 5.0 V.
(4) VGG = 3.5 V.
(5) VGG = 3.0 V.
V
VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 °C;
RG1 (b) = 150 kΩ (connected to VGG); see Fig.4.
VDS (b) = 5 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 °C;
RG1 (b) = 150 kΩ (connected to VGG); see Fig.4.
Fig.24 Drain current as a function of gate 1 (VGG
and drain supply voltage; typical values;
amplifier b.
)
Fig.25 Drain current as a function of gate 2
voltage; typical values; amplifier b.
2003 Sep 30
16
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
MGX454
MGX453
30
120
handbook, halfpage
handbook, halfpage
V
unw
I
(1)
G1
(µA)
(dBµV)
(2)
(3)
(4)
(5)
110
20
100
90
10
80
0
0
20
40
60
0
2
4
6
V
(V)
G2-S
gain reduction (dB)
(1)
V
GG = 5.0 V.
(4) VGG = 3.5 V.
(5) VGG = 3.0 V.
(2) VGG = 4.5 V.
(3) VGG = 4.0 V.
VDS (b) = 5 V; VGG = 5 V; VDS (a) = VG1-S (a) = 0 V;
RG1 (b) = 150 kΩ (connected to VGG); fw = 50 MHz;
funw = 60 MHz; Tamb = 25 °C; see Fig.30.
VDS (b) = 5 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 °C;
RG1 (b) = 150 kΩ (connected to VGG); see Fig.4.
Fig.27 Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical values;
amplifier b.
Fig.26 Gate 1 current as a function of gate 2
voltage; typical values; amplifier b.
2003 Sep 30
17
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
MGX455
MGX456
16
0
handbook, halfpage
handbook, halfpage
I
gain
reduction
(dB)
D
(mA)
12
20
40
60
8
4
0
0
0
1
2
3
4
20
40
60
V
(V)
gain reduction (dB)
AGC
VDS (b) = 5 V; VGG = 5 V; VDS (a) = VG1-S (a) = 0 V;
RG1 (b) = 150 kΩ (connected to VGG); f = 50 MHz;
Tamb = 25 °C; see Fig.30.
VDS (b) = 5 V; VGG = 5 V; VDS (a) = VG1-S (a) = 0 V;
RG1 (b) = 150 kΩ (connected to VGG); f = 50 MHz;
Tamb = 25 °C; see Fig.30.
Fig.28 Typical gain reduction as a function of AGC
voltage; amplifier b.
Fig.29 Drain current as a function of gain
reduction; typical values; amplifier b.
2003 Sep 30
18
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
V
(a)
DS
5 V
V
AGC
4.7 nF
L1
2.2 µH
10 kΩ
4.7 nF
g1 (a)
d (a)
4.7 nF
50 Ω
g2
s
BF1205
4.7 nF
g1 (b)
d (b)
R
R
GEN
50 Ω
L2
2.2 µH
L
50 Ω
50 Ω
R
G1
150 kΩ
V
i
4.7 nF
V
V
(b)
GG
5 V
DS
5 V
MDB813
Fig.30 Cross-modulation test set-up for amplifier b.
MGX458
MGX457
2
2
2
10
−10
10
handbook, halfpage
handbook, halfpage
y
is
y
ϕ
|
|
fs
fs
(mS)
(mS)
(deg)
y
|
|
fs
10
10
−10
b
g
is
is
1
ϕ
fs
−1
1
10
−1
10
2
3
2
3
10
10
10
10
10
f (MHz)
f (MHz)
VDS (b) = 5 V; VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V;
ID (b) = 12 mA.
VDS (b) = 5 V; VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V;
ID (b)= 12 mA.
Fig.32 Forward transfer admittance and phase as
a function of frequency; typical values;
amplifier b.
Fig.31 Input admittance as a function of frequency;
typical values; amplifier b.
2003 Sep 30
19
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
MGX459
3
MGX460
−10
3
10
10
handbook, halfpage
handbook, halfpage
ϕ
rs
y
y
|
|
os
rs
(deg)
(mS)
(µS)
b
g
os
ϕ
2
2
rs
−10
1
10
os
y
|
|
rs
−1
−10
−1
10
10
−2
10
1
10
2
3
2
3
10
10
10
10
10
f (MHz)
f (MHz)
VDS (b) = 5 V; VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V;
ID (b) = 12 mA.
VDS (b) = 5 V; VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V;
ID (b) = 12 mA.
Fig.33 Reverse transfer admittance and phase as
a function of frequency; typical values;
amplifier b.
Fig.34 Output admittance as a function of
frequency; typical values; amplifier b.
2003 Sep 30
20
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
Scattering parameters: amplifier b
VDS (b) = 5 V; VG2-S = 4 V; ID (b) = 12 mA; VDS (a) = 0 V; VG1-S (a) = 0 V; Tamb = 25 °C
s11
s21
s12
s22
f
MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE
(MHz)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
50
100
200
300
400
500
600
700
800
900
1000
0.987
0.985
0.978
0.968
0.956
0.941
0.924
0.905
0.884
0.861
0.837
−3.76
−7.38
3.12
3.11
3.09
3.06
3.01
2.95
2.89
2.83
2.75
2.67
2.59
175.87
171.77
163.72
155.67
147.79
139.86
132.06
124.31
116.69
108.97
101.39
0.00071
0.00136
0.00272
0.00396
0.00509
0.00616
0.00710
0.00791
0.00848
0.00900
0.00941
85.43
86.06
84.25
82.63
81.35
79.46
78.57
77.88
76.72
76.55
76.67
0.991
0.989
0.988
0.986
0.983
0.973
0.975
0.972
0.968
0.964
0.959
−1.56
−3.11
−14.63
−21.82
−28.92
−35.99
−42.93
−49.89
−56.57
−63.36
−70.05
−6.16
−9.17
−12.17
−15.16
−18.15
−21.07
−24.08
−27.03
−30.02
Noise data
VDS (b) = 5 V; VG2-S = 4 V; ID (b) = 12 mA; VDS (a) = 0 V; VG1-S (a) = 0 V; Tamb = 25 °C
F MIN
(dB)
f
F MIN
(dB)
Rn
(Ω)
(MHz)
(ratio)
(deg)
400
800
1.3
1.4
0.662
0.578
16.76
33.97
31.55
30.53
2003 Sep 30
21
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
PACKAGE OUTLINE
Plastic surface mounted package; 6 leads
SOT363
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
1
2
3
c
e
1
b
L
p
w
M B
p
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
97-02-28
SOT363
SC-88
2003 Sep 30
22
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Sep 30
23
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R77/01/pp24
Date of release: 2003 Sep 30
Document order number: 9397 750 11784
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