BF1206 [NXP]
Dual N-channel dual-gate MOS-FET; 双N沟道双栅MOS -FET
| 型号： | BF1206 |
| 厂家： | 
NXP |
| 描述： | Dual N-channel dual-gate MOS-FET |
| 文件： | 总21页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DISCRETE SEMICONDUCTORS
DATA SHEET
andbook, halfpage
BF1206
Dual N-channel dual-gate
MOS-FET
Product specification
2003 Nov 17
Philips Semiconductors
Product specification
Dual N-channel dual-gate MOS-FET
BF1206
FEATURES
PINNING - SOT363
PIN
• Two low noise gain controlled amplifiers in a single
package
DESCRIPTION
1
2
3
4
5
6
drain (b)
source
• Superior cross-modulation performance during AGC
• High forward transfer admittance
gate 1 (b)
gate 1 (a)
gate 2
• High forward transfer admittance to input capacitance
ratio.
drain (a)
APPLICATIONS
• Gain controlled low noise amplifiers for VHF and UHF
applications with 5 V supply voltage, such as digital and
analog television tuners.
d (a)
g2
g1 (a)
handbook, halfpage
6
5
4
DESCRIPTION
AMP
a
The BF1206 is a combination of two different dual gate
MOS-FET amplifiers with shared source and gate 2 leads.
The source and substrate are interconnected. Internal bias
circuits enable DC stabilization and a very good
AMP
b
1
2
3
cross-modulation performance during AGC. Integrated
diodes between the gates and source protect against
excessive input voltage surges. The transistor is
Top view
d (b)
s
g1 (b)
MAM480
encapsulated in SOT363 micro-miniature plastic package.
Marking code: L6-.
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Per MOS-FET; unless otherwise specified
VDS
ID
drain-source voltage
drain current (DC)
−
−
6
V
−
−
30
48
44
2.9
2.2
−
mA
mS
mS
pF
yfs
forward transfer admittance
amp. a: ID = 18 mA
33
29
−
38
34
2.4
1.7
15
amp. b: ID = 12 mA
Cig1-s
input capacitance at gate 1
amp. a: ID = 18 mA; f = 1 MHz
amp. b: ID = 12 mA; f = 1 MHz
f = 1 MHz
−
pF
Crss
reverse transfer capacitance
cross-modulation
−
fF
Xmod
amp. a: input level for k = 1% at
40 dB AGC
102 105
−
dBµV
amp. b: input level for k = 1% at
40 dB AGC
100 103
−
dBµV
NF
noise figure
amp. a: f = 400 MHz; ID = 18 mA
amp. b: f = 800 MHz; ID = 12 mA
amp. a: f = 11 MHz; ID = 18 mA
amp. b: f = 11 MHz; ID = 12 mA
−
−
−
−
1.3
1.4
3
1.9
2.0
−
dB
dB
dB
dB
3.5
−
2003 Nov 17
2
Philips Semiconductors
Product specification
Dual N-channel dual-gate MOS-FET
BF1206
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
BF1206
−
plastic surface mounted package; 6 leads
SOT363
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL PARAMETER CONDITIONS
Per MOS-FET; unless otherwise specified
MIN.
MAX. UNIT
VDS
ID
drain-source voltage
drain current (DC)
gate 1 current
−
−
−
−
−
6
V
30
mA
mA
mA
mW
°C
IG1
IG2
Ptot
Tstg
Tj
±10
±10
180
+150
150
gate 2 current
total power dissipation
storage temperature
junction temperature
Ts ≤ 107 °C; note 1
−65
−
°C
Note
1. Ts is the temperature at the soldering point of the source lead.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
VALUE
UNIT
K/W
Rth j-s
thermal resistance from junction to soldering point
240
2003 Nov 17
3
Philips Semiconductors
Product specification
Dual N-channel dual-gate MOS-FET
BF1206
MLE257
200
handbook, halfpage
P
tot
(mW)
150
100
50
0
0
50
100
150
200
T
(°C)
s
Fig.2 Power derating curve.
STATIC CHARACTERISTICS
Tj = 25 °C unless otherwise specified.
SYMBOL
Per MOS-FET unless otherwise specified
V(BR)DSS drain-source breakdown voltage VG1-S = VG2-S = 0; ID = 10 µA
PARAMETER
CONDITIONS
MIN. MAX. UNIT
6
−
V
V(BR)G1-SS gate-source breakdown voltage VGS = VDS = 0; IG1-S = 10 mA
V(BR)G2-SS gate-source breakdown voltage VGS = VDS = 0; IG2-S = 10 mA
6
10
10
1.5
1.5
1
V
6
V
V(F)S-G1
V(F)S-G2
VG1-S(th)
VG2-S(th)
IDSX
forward source-gate voltage
forward source-gate voltage
gate-source threshold voltage
gate-source threshold voltage
drain-source current
VG2-S = VDS = 0; IS-G1 = 10 mA
VG1-S = VDS = 0; IS-G2 = 10 mA
VDS = 5 V; VG2-S = 4 V; ID = 100 µA
VDS = 5 V; VG1-S = 5 V; ID = 100 µA
0.5
0.5
0.3
0.35
14
V
V
V
1
V
amp. a:
23
mA
VG2-S = 4 V; VDS = 5 V; RG = 91 kΩ; note 1
amp. b:
9
17
mA
VG2-S = 4 V; VDS = 5 V; RG = 150 kΩ; note 1
IG1-S
IG2-S
gate cut-off current
gate cut-off current
VG1-S = 5 V; VG2-S = VDS = 0
VG2-S = 5 V; VG1-S = VDS = 0
−
−
50
20
nA
nA
Note
1. RG1 connects gate 1 to VGG = 5 V.
2003 Nov 17
4
Philips Semiconductors
Product specification
Dual N-channel dual-gate MOS-FET
BF1206
DYNAMIC CHARACTERISTICS AMPLIFIER a
Common source; Tamb = 25 °C; VG2-S = 4 V; VDS = 5 V; ID = 18 mA; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
33
TYP. MAX. UNIT
yfs
forward transfer admittance pulsed; Tj = 25 °C
input capacitance at gate 1 f = 1 MHz
input capacitance at gate 2 f = 1 MHz
38
2.4
3.2
1.1
15
3
48
2.9
−
mS
pF
pF
pF
fF
Cig1-ss
Cig2-ss
Coss
Crss
−
−
−
−
−
−
−
−
output capacitance
f = 1 MHz
−
reverse transfer capacitance f = 1 MHz
30
−
NF
noise figure
power gain
f = 11 MHz; GS = 20 mS; BS = 0
dB
dB
dB
dB
f = 400 MHz; YS = YS opt
f = 800 MHz; YS = YS opt
1.3
1.6
35
1.9
2.2
−
Gtr
f = 200 MHz; GS = 2 mS; BS = BS opt
GL = 0.5 mS; BL = BL opt; note 1
;
;
f = 400 MHz; GS = 2 mS; BS = BS opt
GL = 1 mS; BL = BL opt; note 1
−
−
30
23
−
−
dB
dB
f = 800 MHz; GS = 3.3 mS; BS = BS opt
GL = 1 mS; BL = BL opt; note 1
;
Xmod
cross-modulation
input level for k = 1%; fw = 50 MHz;
funw = 60 MHz; note 2
at 0 dB AGC
at 10 dB AGC
at 40 dB AGC
90
−
−
−
−
−
dBµV
dBµV
dBµV
92
105
102
Notes
1. Calculated from measured s-parameters.
2. Measured in Fig.35 test circuit.
2003 Nov 17
5
Philips Semiconductors
Product specification
Dual N-channel dual-gate MOS-FET
BF1206
GRAPHS FOR AMPLIFIER a
MLE258
MLE259
30
32
handbook, halfpage
handbook, halfpage
(1)
I
D
(1)
(2)
(3)
(2)
(3)
I
D
(4)
(5)
(mA)
(mA)
24
20
(4)
(5)
16
8
(6)
(7)
10
(6)
(7)
0
0
0
0
0.5
1
1.5
2
2
4
6
V
(V)
V
(V)
DS
G1-S
VDS = 5 V; Tj = 25 °C.
VG2-S = 4 V; Tj = 25 °C.
(1) VG2-S = 4 V.
(5) VG2-S = 2 V.
(6) VG2-S = 1.5 V.
(7) G2-S = 1 V.
(1) VG1-S = 1.5 V.
(2) VG1-S = 1.4 V.
(3) VG1-S = 1.3 V.
(4) VG1-S = 1.2 V.
(5) VG1-S = 1.1 V.
(6) VG1-S = 1 V.
(7) VG1-S = 0.9 V.
(2) VG2-S = 3.5 V.
(3)
VG2-S = 3 V.
V
(4) VG2-S = 2.5 V.
Fig.3 Transfer characteristics; typical values;
amplifier a.
Fig.4 Output characteristics; typical values;
amplifier a.
2003 Nov 17
6
Philips Semiconductors
Product specification
Dual N-channel dual-gate MOS-FET
BF1206
MLE260
MLE261
100
50
handbook, halfpage
handbook, halfpage
(1)
(2)
y
I
fs
G1
(mS)
(µA)
(3)
(2)
(1)
(3)
(4)
80
40
(4)
30
20
1
60
40
(5)
(5)
(6)
(6)
(7)
(7)
20
0
0
0
0
0.5
1
1.5
V
2
10
20
30
I
(mA)
D
(V)
G1-S
VDS = 5 V; Tj = 25 °C.
VDS = 5 V; Tj = 25 °C.
(1) G2-S = 4 V.
(1)
(2) VG2-S = 3.5 V.
(3) G2-S = 3 V.
(4) VG2-S = 2.5 V.
VG2-S = 4 V.
(5) VG2-S = 2 V.
(6) VG2-S = 1.5 V.
(7) G2-S = 1 V.
V
(5) VG2-S = 2 V.
(6) VG2-S = 1.5 V.
(7) VG2-S = 1 V.
(2) VG2-S = 3.5 V.
(3) VG2-S = 3 V.
(4) VG2-S = 2.5 V.
V
V
Fig.5 Gate 1 current as a function of gate 1
voltage; typical values; amplifier a.
Fig.6 Forward transfer admittance as a function
of drain current; typical values; amplifier a.
MLE262
MLE263
24
20
handbook, halfpage
handbook, halfpage
I
D
(mA)
16
I
D
(mA)
16
12
8
8
0
4
0
0
10
20
30
40
I
50
(µA)
0
1
2
3
4
5
V
(V)
GG
G1
VDS = 5 V; VG2-S = 4 V; Tj = 25 °C.
RG1 = 91 kΩ (connected to VGG); see Fig.35.
VDS = 5 V; VG2-S = 4 V; Tj = 25 °C.
Fig.7 Drain current as a function of gate 1 current;
typical values; amplifier a.
Fig.8 Drain current as a function of gate 1 supply
voltage (VGG); typical values; amplifier a.
2003 Nov 17
7
Philips Semiconductors
Product specification
Dual N-channel dual-gate MOS-FET
BF1206
MLE288
MLE292
(1)
40
20
handbook, halfpage
handbook, halfpage
I
I
D
(mA)
D
(mA)
16
(2)
(3)
(1)
(2)
32
(4)
(5)
(3)
(4)
(5)
12
8
24
(6)
(7)
16
4
8
0
0
0
0
2
3
6
8
2
4
6
V
(V)
G2-S
V
= V
(V)
DS
GG
VG2-S = 4 V; Tj = 25 °C; RG1 = 150 kΩ (connected to VGG); see Fig.35.
(1) RG1 = 56 kΩ.
(2) RG1 = 68 kΩ.
(3) RG1 = 82 kΩ.
(4) RG1 = 91 kΩ.
(5) RG1 = 100 kΩ.
(6) RG1 = 120 kΩ.
(7) RG1 = 150 kΩ.
VDS = 5 V; Tj = 25 °C; RG1 = 91 kΩ (connected to VGG); see Fig.35.
(1)
(2)
V
GG = 5 V.
(4) VGG = 3.5 V.
(5) GG = 3 V.
VGG = 4.5 V.
V
(3) VGG = 4 V.
Fig.9 Drain current as a function of gate 1 (VGG
and drain supply voltage; typical values;
amplifier a.
)
Fig.10 Drain current as a function of gate 2
voltage; typical values; amplifier a.
2003 Nov 17
8
Philips Semiconductors
Product specification
Dual N-channel dual-gate MOS-FET
BF1206
MLE264
MLE266
50
120
handbook, halfpage
handbook, halfpage
I
G1
(µA)
V
unw
(dBµV)
(1)
40
110
(2)
(3)
30
(4)
100
90
(5)
20
1
0
80
0
0
2
4
6
10
20
30
40
50
V
(V)
G2-S
gain reduction (dB)
VDS 5 V; Tj = 25 °C.
RG1 = 91 kΩ (connected to VGG); see Fig.35.
(1)
V
GG = 5 V.
(4) VGG = 3.5 V.
(5) VGG = 3 V.
VDS = 5 V; VGG = 5 V; RG1 = 91 kΩ; f = 50 MHz; f unw = 60 MHz;
Tamb = 25 °C; see Fig.35.
(2) VGG = 4.5 V.
(3) VGG = 4 V.
Fig.12 Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical values;
amplifier a.
Fig.11 Gate 1 current as a function of gate 2
voltage; typical values; amplifier a.
MLE265
MLE267
0
24
handbook, halfpage
gain
handbook, halfpage
reduction
I
D
(dB)
(mA)
−10
16
−20
−30
8
0
−40
−50
0
1
2
3
4
0
10
20
30
40
50
V
(V)
gain reduction (dB)
AGC
VDS = 5 V; VGG = 5 V; RG1 = 91 kΩ; f = 50 MHz; Tamb = 25 °C;
VDS = 5 V; VGG = 5 V; RG1 = 91 kΩ; f = 50 MHz; Tamb = 25 °C;
see Fig.35.
see Fig.35.
Fig.13 Typical gain reduction as a function of AGC
voltage; typical values; amplifier a.
Fig.14 Drain current as a function of gain
reduction; typical values; amplifier a.
2003 Nov 17
9
Philips Semiconductors
Product specification
Dual N-channel dual-gate MOS-FET
BF1206
MLE268
MLE269
3
2
3
10
10
−10
handbook, halfpage
handbook, halfpage
ϕ
y
rs
Y
is
(mS)
rs
(deg)
(µS)
ϕ
rs
rs
2
2
10
−10
10
b
is
y
−10
−1
1
10
g
is
−1
10
1
2
3
2
3
10
10
10
10
10
10
f (MHz)
f (MHz)
VDS = 5 V; VG2 = 4 V; ID = 18 mA; Tamb = 25 °C.
VDS = 5 V; VG2 = 4 V; ID = 18 mA; Tamb = 25 °C.
Fig.16 Reverse transfer admittance and phase as
a function of frequency; typical values;
amplifier a.
Fig.15 Input admittance as a function of frequency;
typical values; amplifier a.
MLE270
MLE271
2
2
10
10
−10
handbook, halfpage
handbook, halfpage
ϕ
Y
fs
os
y
fs
fs
(deg)
(mS)
y
fs
(mS)
b
os
1
−10
10
−ϕ
g
os
−1
10
−2
1
10
−1
10
2
3
2
3
10
10
10
10
10
f (MHz)
f (MHz)
VDS = 5 V; VG2 = 4 V; ID = 18 mA; Tamb = 25 °C.
VDS = 5 V; VG2 = 4 V; ID = 18 mA; Tamb = 25 °C.
Fig.17 Forward transfer admittance and phase as
a function of frequency; typical values;
amplifier a.
Fig.18 Output admittance as a function of
frequency; typical values; amplifier a.
2003 Nov 17
10
Philips Semiconductors
Product specification
Dual N-channel dual-gate MOS-FET
BF1206
Amplifier a scattering parameters
VDS = 5 V; VG2-S = 4 V; ID = 18 mA; Tamb = 25 °C
s11
s21
s12
s22
f
MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE
(MHz)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
50
100
200
300
400
500
600
700
800
900
1000
0.988
0.984
0.971
0.951
0.926
0.896
0.865
0.832
0.797
0.769
0.732
−4.62
−9.23
3.72
3.71
3.66
3.58
3.47
3.36
3.23
3.09
2.91
2.83
2.67
174.72
169.42
159.05
148.77
138.74
129.05
119.67
110.43
101.40
93.09
0.0008
0.0015
0.0029
0.0038
0.0044
0.0046
0.0043
0.0038
0.0028
0.0051
0.0071
86.73
84.39
79.96
76.62
74.42
74.84
79.73
92.63
118.47
146.61
159.78
0.991
0.989
0.986
0.980
0.973
0.965
0.958
0.951
0.937
0.940
0.937
−2.07
−4.16
−18.33
−27.32
−36.04
−44.50
−52.63
−60.47
−67.66
−75.01
−81.73
−8.24
−12.32
−16.33
−20.25
−24.20
−28.14
−32.14
−35.76
−39.86
84.05
Noise data
VDS = 5 V; VG2-S = 4 V; ID = 18 mA; Tamb = 25 °C
Γopt
f
Fmin
Rn
(MHz)
(dB)
(Ω)
(ratio)
(deg)
400
800
1.3
1.6
0.618
0.593
22.7
44.1
26.7
29.7
2003 Nov 17
11
Philips Semiconductors
Product specification
Dual N-channel dual-gate MOS-FET
BF1206
DYNAMIC CHARACTERISTICS AMPLIFIER b
Common source; Tamb = 25 °C; VG2-S = 4 V; VDS = 5 V; ID = 12 mA; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
29
TYP. MAX. UNIT
yfs
forward transfer admittance pulsed; Tj = 25 °C
input capacitance at gate 1 f = 1 MHz
input capacitance at gate 2 f = 1 MHz
34
44
2.2
−
mS
pF
pF
pF
fF
Cig1-ss
Cig2-ss
Coss
Crss
F
−
−
−
−
−
−
−
−
1.7
4.2
0.85
15
output capacitance
f = 1 MHz
−
reverse transfer capacitance f = 1 MHz
30
−
noise figure
power gain
f = 11 MHz; GS = 20 mS; BS = 0
3.5
1.3
1.4
35
dB
dB
dB
dB
f = 400 MHz; YS = YS opt
f = 800 MHz; YS = YS opt
1.9
2
Gtr
f = 200 MHz; GS = 2 mS; BS = BS opt
GL = 0.5 mS; BL = BL opt; note 1
;
;
−
f = 400 MHz; GS = 2 mS; BS = BS opt
GL = 1 mS; BL = BL opt; note 1
−
−
31
27
−
−
dB
dB
f = 800 MHz; GS = 3.3 mS; BS = BS opt
GL = 1 mS; BL = BL opt; note 1
;
Xmod
cross-modulation
input level for k = 1%; fw = 50 MHz;
funw = 60 MHz; note 2
at 0 dB AGC
at 10 dB AGC
at 40 dB AGC
90
−
−
−
−
−
dBµV
dBµV
dBµV
90
103
100
Notes
1. Calculated from measured s-parameters.
2. Measured in Fig.35 test circuit.
2003 Nov 17
12
Philips Semiconductors
Product specification
Dual N-channel dual-gate MOS-FET
BF1206
GRAPHS FOR AMPLIFIER b
MLE272
MLE273
30
32
handbook, halfpage
handbook, halfpage
(1)
I
D
(2)
(3)
I
(4)
(5)
D
(mA)
(mA)
(1)
(2)
(3)
24
20
16
8
(6)
(7)
(4)
(5)
10
(6)
(7)
0
0
0
0
0.5
1
1.5
2
2
4
6
V
(V)
V
(V)
DS
G1-S
VDS = 5 V; Tj = 25 °C.
(1) G2-S = 4 V.
VG2-S = 4 V; Tj = 25 °C.
(1) VG1-S = 1.5 V.
(2) VG1-S = 1.4 V.
(3) VG1-S = 1.3 V.
(4) VG1-S = 1.2 V.
(5) VG1-S = 1.1 V.
V
(5) VG2-S = 2 V.
(6) VG1-S = 1 V.
(2) VG2-S = 3.5 V.
(3) VG2-S = 3 V.
(4) VG2-S = 2.5 V.
(6) VG2-S = 1.5 V.
(7) VG2-S = 1 V.
(7) VG1-S = 0.9 V.
Fig.19 Transfer characteristics; typical values;
amplifier b.
Fig.20 Output characteristics; typical values;
amplifier b.
2003 Nov 17
13
Philips Semiconductors
Product specification
Dual N-channel dual-gate MOS-FET
BF1206
MLE274
MLE275
100
50
handbook, halfpage
handbook, halfpage
(1)
(2)
y
I
fs
G1
(mS)
(µA)
(2)
(1)
(3)
80
40
(3)
(4)
(4)
(5)
30
20
10
60
40
(5)
(6)
(6)
(7)
20
0
(7)
0
0
0
0.5
1
1.5
V
2
10
20
30
I
(mA)
D
(V)
G1-S
VDS = 5 V; Tj = 25 °C.
VDS = 5 V; Tj = 25 °C.
(1) G2-S = 4 V.
(1) VG2-S = 4 V.
(2) VG2-S = 3.5 V.
(3) VG2-S = 3 V.
(5) VG2-S = 2 V.
(6) VG2-S = 1.5 V.
(7) VG2-S = 1 V.
V
(5) VG2-S = 2 V.
(6) VG2-S = 1.5 V.
(7) VG2-S = 1 V.
(2) VG2-S = 3.5 V.
(3) VG2-S = 3 V.
(4) VG2-S = 2.5 V.
(4)
VG2-S = 2.5 V.
Fig.21 Gate 1 current as a function of gate 1
voltage; typical values; amplifier b.
Fig.22 Forward transfer admittance as a function
of drain current; typical values; amplifier b.
MLE276
MLE277
24
12
handbook, halfpage
handbook, halfpage
I
I
D
D
(mA)
(mA)
16
8
8
0
4
0
0
10
20
30
40
I
50
(µA)
0
1
2
3
4
5
V
(V)
GG
G1
VDS = 5 V; VG2-S = 4 V; Tj = 25 °C.
RG1 = 150 kΩ (connected to VGG); see Fig.35.
VDS = 5 V; VG2-S = 4 V; Tj = 25 °C.
Fig.23 Drain current as a function of gate 1 current;
typical values; amplifier b.
Fig.24 Drain current as a function of gate 1 supply
voltage (VGG); typical values; amplifier b.
2003 Nov 17
14
Philips Semiconductors
Product specification
Dual N-channel dual-gate MOS-FET
BF1206
MLE278
MLE279
24
16
handbook, halfpage
handbook, halfpage
I
D
I
(1)
(2)
(3)
(4)
D
(1)
(2)
(mA)
(mA)
12
(3)
(4)
16
(5)
(5)
(6)
8
4
(7)
8
0
0
0
0
2
4
6
8
2
4
6
V
(V)
G2-S
V
= V
(V)
DS
GG
VG2-S = 4 V; Tj = 25 °C.
RG1 = 150 kΩ (connected to VGG); see Fig.35.
VDS = 5 V; Tj = 25 °C.
RG1 = 150 kΩ (connected to VGG); see Fig.35.
(1)
(2) RG1 = 220 kΩ.
(3) G1 = 180 kΩ.
(4) RG1 = 150 kΩ.
R
G1 = 270 kΩ.
(5) RG1 = 120 kΩ.
(6) RG1 = 100 kΩ.
R
(7) RG1 = 82 kΩ.
(1) VGG = 5 V.
(2) VGG = 4.5 V.
(3) VGG = 4 V.
(4) VGG = 3.5 V.
(5) VGG = 3 V.
Fig.25 Drain current as a function of gate 1 (VGG
and drain supply voltage; typical values;
amplifier b.
)
Fig.26 Drain current as a function of gate 2
voltage; typical values; amplifier b.
2003 Nov 17
15
Philips Semiconductors
Product specification
Dual N-channel dual-gate MOS-FET
BF1206
MLE280
MLE282
30
120
handbook, halfpage
handbook, halfpage
V
unw
I
(1)
(2)
(3)
G1
(µA)
(dBµV)
110
20
(4)
(5)
100
90
10
0
80
0
0
2
4
6
10
20
30
40
50
V
(V)
gain reduction (dB)
G2-S
VDS 5 V; Tj = 25 °C.
RG1 = 150 kΩ (connected to VGG); see Fig.35.
(1)
V
GG = 5 V.
(4) VGG = 3.5 V.
(5) VGG = 3 V.
VDS = 5 V; VGG = 5 V; RG1 = 150 kΩ; f = 50 MHz; f unw = 60 MHz;
Tamb = 25 °C; see Fig.35.
(2) VGG = 4.5 V.
(3) VGG = 4 V.
Fig.28 Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical values;
amplifier b.
Fig.27 Gate 1 current as a function of gate 2
voltage; typical values; amplifier b.
MLE281
MLE283
0
16
handbook, halfpage
handbook, halfpage
gain
I
reduction
D
(dB)
(mA)
−10
12
−20
−30
8
4
0
−40
−50
0
1
2
3
4
0
10
20
30
40
50
V
(V)
gain reduction (dB)
AGC
VDS = 5 V; VGG = 5 V; RG1 = 150 kΩ; f = 50 MHz; Tamb = 25 °C;
VDS = 5 V; VGG = 5 V; RG1 = 150 kΩ; f = 50 MHz; Tamb = 25 °C;
see Fig.35.
see Fig.35.
Fig.29 Typical gain reduction as a function of AGC
voltage; typical values; amplifier b.
Fig.30 Drain current as a function of gain
reduction; typical values; amplifier b.
2003 Nov 17
16
Philips Semiconductors
Product specification
Dual N-channel dual-gate MOS-FET
BF1206
MLE284
MLE285
3
2
3
10
10
−10
handbook, halfpage
handbook, halfpage
Y
is
ϕ
y
rs
rs
(mS)
10
(deg)
(µS)
ϕ
rs
rs
2
2
−10
10
b
is
1
y
g
−10
−1
10
is
−1
10
−2
10
1
2
3
2
3
10
10
10
10
10
10
f (MHz)
f (MHz)
VDS = 5 V; VG2 = 4 V; ID = 12 mA; Tamb = 25 °C.
VDS = 5 V; VG2 = 4 V; ID = 12 mA; Tamb = 25 °C.
Fig.32 Reverse transfer admittance and phase as
a function of frequency; typical values;
amplifier b.
Fig.31 Input admittance as a function of frequency;
typical values; amplifier b.
MLE286
MLE287
2
2
2
10
10
−10
handbook, halfpage
handbook, halfpage
ϕ
Y
fs
os
y
(deg)
(mS)
fs
y
fs
(mS)
b
os
10
−10
10
g
os
−ϕ
1
fs
−1
1
10
−1
10
2
3
2
3
10
10
10
10
10
f (MHz)
f (MHz)
VDS = 5 V; VG2 = 4 V; ID = 12 mA; Tamb = 25 °C.
VDS = 5 V; VG2 = 4 V; ID = 12 mA; Tamb = 25 °C.
Fig.33 Forward transfer admittance and phase as
a function of frequency; typical values;
amplifier b.
Fig.34 Output admittance as a function of
frequency; typical values; amplifier b.
2003 Nov 17
17
Philips Semiconductors
Product specification
Dual N-channel dual-gate MOS-FET
BF1206
V
AGC
R1
10 kΩ
C1
4.7 nF
C3
4.7 nF
R
50 Ω
L1
≈2.2 µH
L
C2
DUT
C4
4.7 nF
R
GEN
50 Ω
R2
50 Ω
R
G1
4.7 nF
V
V
V
I
GG
DS
MGS315
Fig.35 Cross-modulation test set-up (for one MOS-FET).
Amplifier b scattering parameters
VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 °C
s11
s21
s12
s22
f
MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE
(MHz)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
50
100
200
300
400
500
600
700
800
900
1000
0.991
0.989
0.982
0.973
0.961
0.947
0.933
0.919
0.905
0.890
0.881
−3.43
−6.84
3.44
3.43
3.41
3.38
3.34
3.29
3.23
3.16
3.09
3.02
2.94
176.33
172.66
165.44
158.20
151.04
144.02
137.12
130.22
123.22
116.84
110.20
0.0008
0.0015
0.0029
0.0041
0.0051
0.0058
0.0062
0.0063
0.0065
0.0055
0.0058
86.54
84.92
80.95
77.63
74.43
71.86
70.28
70.72
72.37
75.91
89.82
0.988
0.987
0.985
0.982
0.978
0.973
0.969
0.965
0.960
0.958
0.958
−1.69
−3.38
−13.61
−20.37
−27.05
−33.68
−40.17
−46.54
−52.86
−58.60
−64.34
−6.72
−10.08
−13.46
−16.83
−20.25
−23.68
−27.22
−30.57
−34.14
Noise data
VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 °C
Γopt
f
Fmin
Rn
(MHz)
(dB)
(Ω)
(ratio)
0.648
0.604
(deg)
14.4
31.1
400
800
1.3
1.4
28.8
27.9
2003 Nov 17
18
Philips Semiconductors
Product specification
Dual N-channel dual-gate MOS-FET
BF1206
PACKAGE OUTLINE
Plastic surface mounted package; 6 leads
SOT363
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
1
2
3
c
e
1
b
L
p
w
M B
p
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
97-02-28
SOT363
SC-88
2003 Nov 17
19
Philips Semiconductors
Product specification
Dual N-channel dual-gate MOS-FET
BF1206
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Nov 17
20
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R77 20p/01/pp21
Date of release: 2003 Nov 17
Document order number: 9397 750 12005
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