BF1205C,115 [NXP]
BF1205C - Dual N-channel dual-gate MOSFET TSSOP 6-Pin;
| 型号： | BF1205C,115 |
| 厂家： | 
NXP |
| 描述： | BF1205C - Dual N-channel dual-gate MOSFET TSSOP 6-Pin 开关 光电二极管 晶体管 |
| 文件： | 总23页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BF1205C
Dual N-channel dual gate MOS-FET
Rev. 3 — 7 September 2011
Product data sheet
1. Product profile
1.1 General description
The BF1205C is a combination of two dual gate MOS-FET amplifiers with shared source
and gate 2 leads and an integrated switch. The integrated switch is operated by the gate 1
bias of amplifier b.
The source and substrate are interconnected. Internal bias circuits enable DC stabilization
and a very good cross-modulation performance during AGC. Integrated diodes between
the gates and source protect against excessive input voltage surges. The transistor has a
SOT363 micro-miniature plastic package.
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken
during transport and handling.
1.2 Features and benefits
Two low noise gain controlled amplifiers in a single package; one with a fully integrated
bias and one with a partly integrated bias
Internal switch to save external components
Superior cross-modulation performance during AGC
High forward transfer admittance
High forward transfer admittance to input capacitance ratio.
1.3 Applications
Gain controlled low noise amplifiers for VHF and UHF applications with 5 V supply
voltage
digital and analog television tuners
professional communication equipment.
BF1205C
NXP Semiconductors
Dual N-channel dual gate MOS-FET
1.4 Quick reference data
Table 1.
Quick reference data
Per MOS-FET unless otherwise specified.
Symbol Parameter Conditions
Min Typ Max Unit
VDS
ID
drain-source voltage
-
-
-
-
-
-
6
V
drain current (DC)
30
mA
[1]
Ptot
yfs
total power dissipation
Tsp 107 C
180 mW
forward transfer admittance f = 1 MHz
amplifier a; ID = 19 mA
amplifier b; ID = 13 mA
input capacitance at gate 1 f = 1 MHz
26
28
31
33
41
43
mS
mS
Cig1-ss
amplifier a
amplifier b
-
-
-
-
-
2.2 2.7 pF
2.0 2.5 pF
Crss
NF
reverse transfer capacitance f = 1 MHz
20
-
fF
noise figure
amplifier a; f = 400 MHz
amplifier b; f = 800 MHz
1.3 1.9 dB
1.4 2.1 dB
Xmod
cross-modulation
input level for k = 1 % at
40 dB AGC
amplifier a
amplifier b
100 105
100 103
-
-
dBV
dBV
Tj
junction temperature
-
-
150 C
[1] Tsp is the temperature at the soldering point of the source lead.
2. Pinning information
Table 2.
Discrete pinning
Pin
1
Description
gate 1 (a)
gate 2
Simplified outline
Symbol
6
5
4
2
AMP a
G1
(A)
D
(A)
3
gate 1 (b)
drain (b)
source
4
5
G2
S
1
2
3
6
drain (a)
001aaa706
G1
(B)
D
(B)
AMP b
sym033
BF1205C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 September 2011
2 of 23
BF1205C
NXP Semiconductors
Dual N-channel dual gate MOS-FET
3. Ordering information
Table 3.
Ordering information
Type number Package
Name
Description
Version
BF1205C
-
plastic surface mounted package; 6 leads
SOT363
4. Marking
Table 4.
Marking
Type number
Marking code[1]
BF1205C
M6*
[1] * = p or -: made in Hong Kong.
* = t: made in Malaysia.
* = W: made in China.
5. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
Per MOS-FET
VDS
ID
drain-source voltage
-
6
V
drain current (DC)
gate 1 current
-
30
mA
mA
mA
mW
C
IG1
IG2
Ptot
Tstg
Tj
-
10
10
180
+150
150
gate 2 current
-
[1]
total power dissipation
storage temperature
junction temperature
Tsp 107 C
-
65
-
C
[1] Tsp is the temperature at the soldering point of the source lead.
6. Thermal characteristics
Table 6.
Thermal characteristics
Symbol
Parameter
Conditions
Typ
240
Unit
Rth(j-s)
thermal resistance from junction
to soldering point
K/W
BF1205C
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 September 2011
3 of 23
BF1205C
NXP Semiconductors
Dual N-channel dual gate MOS-FET
001aac193
250
tot
P
(mW)
200
150
100
50
0
0
50
100
150
200
T
(˚C)
sp
Fig 1. Power derating curve.
7. Static characteristics
Table 7.
Static characteristics
Tj = 25 C.
Symbol
Parameter
Conditions
Min Typ Max Unit
Per MOS-FET; unless otherwise specified
V(BR)DSS
drain-source breakdown voltage
VG1-S = VG2-S = 0 V; ID = 10 A
amplifier a
6
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
amplifier b
6
-
V(BR)G1-SS
V(BR)G2-SS
V(F)S-G1
V(F)S-G2
VG1-S(th)
VG2-S(th)
IDSX
gate 1-source breakdown voltage VGS = VDS = 0 V; IG1-S = 10 mA
gate 2-source breakdown voltage VGS = VDS = 0 V; IG2-S = 10 mA
6
10
10
1.5
1.5
1.0
1.0
6
forward source-gate 1 voltage
forward source-gate 2 voltage
gate 1-source threshold voltage
gate 2-source threshold voltage
drain-source current
VG2-S = VDS = 0 V; IS-G1 = 10 mA
VG1-S = VDS = 0 V; IS-G2 = 10 mA
0.5
0.5
0.3
0.4
VDS = 5 V; VG2-S = 4 V; ID = 100 A
VDS = 5 V; VG1-S = 5 V; ID = 100 A
VG2-S = 4 V; VDS(b) = 5 V; RG1 = 150 k
amplifier a; VDS(a) = 5 V
amplifier b
[1]
[2]
14
9
-
-
24
17
mA
mA
IG1-S
gate 1 cut-off current
gate 2 cut-off current
VG2-S = VDS(a) = 0 V
amplifier a; VG1-S(a) = 5 V; ID(b) = 0 A
-
-
-
-
-
-
50
50
20
nA
nA
nA
amplifier b; VG1-S(b) = 5 V; VDS(b) = 0 V
IG2-S
VG2-S = 4 V;
VG1-S(a) = VDS(a) = VDS(b) = 0 V;
VG1-S(b) = 0 V;
[1] RG1 connects gate 1 (b) to VGG = 0 V (see Figure 3).
[2] RG1 connects gate 1 (b) to VGG = 5 V (see Figure 3).
BF1205C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 September 2011
4 of 23
BF1205C
NXP Semiconductors
Dual N-channel dual gate MOS-FET
001aaa552
20
I
D
(mA)
16
(1)
(2)
12
8
(3)
G1 (A)
G2
D (A)
S
(4)
4
(6)
(5)
G1 (B)
D (B)
R
G1
0
0
1
2
3
4
5
V
GG
V
(V)
001aaa553
GG
(1) ID(b); RG1 = 120 k.
(2) D(b); RG1 = 150 k.
V
V
GG = 5 V: amplifier a is off; amplifier b is on
GG = 0 V: amplifier a is on; amplifier b is off.
I
(3) ID(b); RG1 = 180 k.
(4) ID(a); RG1 = 180 k.
(5)
ID(a); RG1 = 150 k.
(6) ID(a); RG1 = 120 k.
Fig 2. Drain currents of MOS-FET a and b as function
of VGG
Fig 3. Functional diagram.
.
8. Dynamic characteristics
8.1 Dynamic characteristics for amplifier a
Table 8.
Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 19 mA.
Dynamic characteristics for amplifier a[1]
Symbol Parameter
Conditions
Tj = 25 C
f = 1 MHz
f = 1 MHz
f = 1 MHz
Min Typ Max Unit
yfs
Cig1-ss
Cig2-ss
Coss
Crss
forward transfer admittance
26
-
31
41
mS
pF
pF
pF
fF
input capacitance at gate 1
input capacitance at gate 2
output capacitance
2.2 2.7
-
3.0
0.9
20
-
-
-
-
reverse transfer capacitance f = 1 MHz
-
Gtr
power gain
BS = BS(opt); BL = BL(opt)
f = 200 MHz; GS = 2 mS; GL = 0.5 mS
f = 400 MHz; GS = 2 mS; GL = 1 mS
f = 800 MHz; GS = 3.3 mS; GL = 1 mS
f = 11 MHz; GS = 20 mS; BS = 0 S
f = 400 MHz; YS = YS(opt)
31
26
21
-
35
30
25
3.0
39
34
29
-
dB
dB
dB
dB
dB
dB
NF
noise figure
-
1.3 1.9
1.4 2.1
f = 800 MHz; YS = YS(opt)
-
BF1205C
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 September 2011
5 of 23
BF1205C
NXP Semiconductors
Dual N-channel dual gate MOS-FET
Table 8.
Dynamic characteristics for amplifier a[1] …continued
Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 19 mA.
Symbol Parameter
Xmod cross-modulation
Conditions
Min Typ Max Unit
[2]
input level for k = 1 %; fw = 50 MHz; funw = 60 MHz
at 0 dB AGC
at 10 dB AGC
at 20 dB AGC
at 40 dB AGC
90
-
-
-
-
-
-
dBV
dBV
dBV
dBV
90
99
-
100 105
[1] For the MOS-FET not in use: VG1-S(b) = 0 V; VDS(b) = 0 V.
[2] Measured in Figure 33 test circuit.
8.1.1 Graphs for amplifier a
001aaa554
001aaa555
30
32
(1)
I
(1)
(2)
D
(2)
(3)
I
D
(mA)
(mA)
(4)
(5)
24
(3)
(4)
20
16
8
(5)
(6)
(7)
10
(6)
(7)
(8)
(9)
0
0
0
0.4
0.8
1.2
1.6
V
2
(V)
0
2
4
6
V
(V)
DS
G1-S
(1) VG2-S = 4 V.
(2) G2-S = 3.5 V.
(1) VG1-S(a) = 1.8 V.
(2) G1-S(a) = 1.7 V.
V
V
(3) VG2-S = 3 V.
(3) VG1-S(a) = 1.6 V.
(4) VG1-S(a) = 1.5 V.
(4) VG2-S = 2.5 V.
(5)
V
G2-S = 2 V.
(5) VG1-S(a) = 1.4 V.
(6) VG2-S = 1.5 V.
(7) VG2-S = 1 V.
(6) VG1-S(a) = 1.3 V.
(7) VG1-S(a) = 1.2 V.
(8) VG1-S(a) = 1.1 V.
VDS(a) = 5 V; VG1-S(b) = VDS(b) = 0 V; Tj = 25 C.
(9)
V
G1-S(a) = 1 V.
VG2-S = 4 V; VG1-S(b) = VDS(b) = 0 V; Tj = 25 C.
Fig 4. Transfer characteristics; typical values.
Fig 5. Output characteristics; typical values.
BF1205C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 September 2011
6 of 23
BF1205C
NXP Semiconductors
Dual N-channel dual gate MOS-FET
001aaa557
001aaa556
20
(a)
40
I
D
y
fs
(mA)
16
(mS)
(1)
(2)
30
12
8
20
10
0
(3)
(4)
4
(5)
(6)
0
0
20
40
60
0
8
16
24
32
I
(b) (μA)
I
(mA)
D
D
(1) VG2-S = 4 V.
VDS(a) = 5 V; VG2-S = 4 V; VDS(b) = 5 V; VG1-S(b) = 0 V;
Tj = 25 C.
(2) VG2-S = 3.5 V.
(3) VG2-S = 3 V.
(4)
VG2-S = 2.5 V.
(5) VG2-S = 2 V.
(6) VG2-S = 1.5 V.
V
DS(a) = 5 V; VG1-S(b) = VDS(b) = 0 V; Tj = 25 C.
Fig 6. Forward transfer admittance as a function of
drain current; typical values.
Fig 7. Drain current as a function of internal G1
current (current in pin drain (b) if MOS-FET (b)
is switched off); typical values.
BF1205C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 September 2011
7 of 23
BF1205C
NXP Semiconductors
Dual N-channel dual gate MOS-FET
001aaa558
001aaa559
20
32
I
D
I
D
(mA)
16
(mA)
24
(1)
12
8
(2)
(3)
16
8
(4)
(5)
(6)
4
0
0
0
1
2
3
4
5
0
2
4
6
V
(V)
V
(V)
G2-S
sup
VDS(a) = VDS(b) = Vsupply, VG2-S = 4 V, Tj = 25 C,
G1(b) = 150 k (connected to ground); see Figure 3.
(1) VDS(b) = 5 V.
(2) DS(b) = 4.5 V.
R
V
(3) VDS(b) = 4 V.
(4) VDS(b) = 3.5 V.
(5)
VDS(b) = 3 V.
(6) VDS(b) = 2.5 V.
VDS(a) = 5 V; VG1-S(b) = 0 V; gate 1 (a) = open;
Tj = 25 C.
Fig 8. Drain current of amplifier a as a function of
supply voltage of a and b amplifier; typical
values.
Fig 9. Drain current as a function of gate 2 and drain
supply voltage; typical values.
001aaa560
001aaa561
120
0
gain
reduction
V
unw
(dBμV)
(dB)
10
110
20
30
40
50
100
90
80
0
10
20
30
40
50
0
1
2
3
4
gain reduction (dB)
V
(V)
AGC
VDS(a) = VDS(b) = 5 V; VG1-S(b) = 0 V; fw = 50 MHz;
unw = 60 MHz; Tamb = 25 C; see Figure 33.
VDS(a) = VDS(b) = 5 V; VG1-S(b) = 0 V; f = 50 MHz; see
Figure 33.
f
Fig 10. Unwanted voltage for 1 % cross-modulation as
a function of gain reduction; typical values.
Fig 11. Gain reduction as a function of AGC voltage;
typical values.
BF1205C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 September 2011
8 of 23
BF1205C
NXP Semiconductors
Dual N-channel dual gate MOS-FET
001aaa562
001aaa564
2
32
10
b , g
is is
(mS)
I
D
(mA)
24
10
1
b
g
is
16
8
is
−1
10
−2
0
10
2
3
0
20
40
60
10
10
10
gain reduction (dB)
f (MHz)
VDS(a) = VDS(b) = 5 V; VG1-S(b) = 0 V; f = 50 MHz;
amb = 25 C; see Figure 33.
VDS(a) = 5 V; VG2-S(a) = 4 V; VDS(b) = VG1-S(b) = 0 V;
ID(a) = 19 mA.
T
Fig 12. Drain current as a function of gain reduction;
typical values.
Fig 13. Input admittance as a function of frequency;
typical values.
001aaa565
001aaa566
2
2
3
2
3
10
10
10
10
y
−ϕ
(deg)
rs
rs
(mS)
y
−ϕ
fs
(deg)
y
fs
fs
(mS)
−ϕ
rs
2
10
10
10
10
y
rs
−ϕ
fs
10
10
1
3
1
3
1
1
2
2
10
10
10
10
10
10
f (MHz)
f (MHz)
VDS(a) = 5 V; VG2-S(a) = 4 V; VDS(b) = VG1-S(b) = 0 V;
ID(a) = 19 mA.
V
DS(a) = 5 V; VG2-S(a) = 4 V; VDS(b) = VG1-S(b) = 0 V;
ID(a) = 19 mA.
Fig 14. Forward transfer admittance and phase as a
function of frequency; typical values.
Fig 15. Reverse transfer admittance and phase as a
function of frequency: typical values.
BF1205C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 September 2011
9 of 23
BF1205C
NXP Semiconductors
Dual N-channel dual gate MOS-FET
001aaa567
10
b , g
os os
(mS)
b
g
os
1
os
−1
10
−2
10
2
3
10
10
10
f (MHz)
VDS(a) = 5 V; VG2-S(a) = 4 V; VDS(b) = VG1-S(b) = 0 V; ID(a) = 19 mA.
Fig 16. Output admittance as a function of frequency; typical values.
8.1.2 Scattering parameters for amplifier a
Table 9.
Scattering parameters for amplifier a
VDS(a) = 5 V; VG2-S = 4 V; ID(a) = 19 mA; VDS(b) = 0 V; VG-1S(b) = 0 V; Tamb = 25 C.
f
S11
S21
S12
S22
(MHz)
Magnitude Angle Magnitude Angle Magnitude Angle Magnitude Angle
ratio
(deg) ratio
3.91 3.07
7.76 3.06
15.42 3.04
22.99 3.01
30.52 2.96
37.83 2.90
45.14 2.83
52.31 2.76
59.47 2.69
66.23 2.60
73.10 2.52
(deg) ratio
(deg) ratio
83.61 0.992
83.19 0.992
78.19 0.990
73.75 0.988
69.82 0.985
66.12 0.982
62.11 0.979
58.86 0.975
58.28 0.972
50.64 0.968
47.28 0.966
(deg)
50
0.992
0.990
0.982
0.971
0.956
0.938
0.917
0.893
0.867
0.838
175.56 0.0007
171.18 0.0017
162.42 0.0026
153.79 0.0037
145.22 0.0047
136.78 0.0055
128.46 0.0061
120.20 0.0065
111.98 0.0068
103.90 0.0067
95.875 0.0065
1.47
100
200
300
400
500
600
700
800
900
2.93
5.84
8.71
11.59
14.48
17.31
20.14
22.98
25.85
28.74
1000 0.807
8.1.3 Noise data for amplifier a
Table 10. Noise data for amplifier a
VDS(a) = 5 V; VG2-S = 4 V; ID(a) = 19 mA; VDS(b) = 0 V; VG-1S(b) = 0 V; Tamb = 25 C.
f
Fmin
(dB)
opt
rn
()
(MHz)
ratio
0.718
0.677
(deg)
16.06
37.59
400
800
1.3
1.4
0.683
0.681
BF1205C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 September 2011
10 of 23
BF1205C
NXP Semiconductors
Dual N-channel dual gate MOS-FET
8.2 Dynamic characteristics for amplifier b
Table 11. Dynamic characteristics for amplifier b
Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 13 mA.
Symbol Parameter
Conditions
Min Typ Max Unit
yfs
Cig1-ss
Cig2-ss
Coss
Crss
forward transfer admittance Tj = 25 C
input capacitance at gate 1 f = 1 MHz
input capacitance at gate 2 f = 1 MHz
28
-
33
43
mS
2.0
3.4
0.85
20
2.5 pF
-
-
-
-
pF
pF
fF
output capacitance
f = 1 MHz
-
reverse transfer capacitance f = 1 MHz
-
[1]
Gtr
power gain
BS = BS(opt); BL = BL(opt)
f = 200 MHz; GS = 2 mS; GL = 0.5 mS
f = 400 MHz; GS = 2 mS; GL = 1 mS
f = 800 MHz; GS = 3.3 mS; GL = 1 mS
f = 11 MHz; GS = 20 mS; BS = 0 S
f = 400 MHz; YS = YS(opt)
31
28
24
-
35
32
28
5
39
36
32
-
dB
dB
dB
dB
NF
noise figure
-
1.3
1.4
1.9 dB
2.1 dB
f = 800 MHz; YS = YS(opt)
-
[2]
Xmod
cross-modulation
input level for k = 1 %; fw = 50 MHz; funw = 60 MHz
at 0 dB AGC
90
-
-
-
-
-
-
dBV
at 10 dB AGC
88
94
dBV
dBV
dBV
at 20 dB AGC
-
at 40 dB AGC
100 103
[1] For the MOS-FET not in use: VG1-S(a) = 0 V; VDS(a) = 0 V.
[2] Measured in Figure 34 test circuit.
BF1205C
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 September 2011
11 of 23
BF1205C
NXP Semiconductors
Dual N-channel dual gate MOS-FET
8.2.1 Graphs for amplifier b
001aaa568
001aaa569
30
32
(1)
(4)
I
D
(2)
(3)
I
D
(1)
(2)
(mA)
(mA)
24
(5)
20
(3)
(4)
(5)
16
8
(6)
(7)
10
(6)
(7)
0
0
0
0.4
0.8
1.2
1.6
V
2
(V)
0
2
4
6
V
(V)
DS
G1-S
(1) VG2-S = 4 V.
(1) VG1-S(b) = 1.6 V.
(2) VG1-S(b) = 1.5 V.
(2) VG2-S = 3.5 V.
(3)
V
G2-S = 3 V.
(3) VG1-S(b) = 1.4 V.
(4) VG2-S = 2.5 V.
(5) VG2-S = 2 V.
(4) VG1-S(b) = 1.3 V.
(5) VG1-S(b) = 1.2 V.
(6)
V
G2-S = 1.5 V.
(6)
VG1-S(b) = 1.1 V.
(7) VG2-S = 1 V.
(7) VG1-S(b) = 1 V.
VDS(b) = 5 V; VDS(a) = VG1-S(a) = 0 V; Tj = 25 C.
VG2-S = 4 V; VDS(a) = VG1-S(a) = 0 V; Tj = 25 C.
Fig 17. Transfer characteristics; typical values.
Fig 18. Output characteristics; typical values.
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Product data sheet
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BF1205C
NXP Semiconductors
Dual N-channel dual gate MOS-FET
001aaa570
001aaa571
100
40
(1)
(2)
(1)
(2)
I
G1
y
fs
(μA)
(mS)
(3)
(3)
80
30
(4)
(4)
(5)
60
40
20
0
20
10
0
(5)
(6)
(7)
(6)
(7)
0
0.4
0.8
1.2
1.6
V
2
0
8
16
24
32
(V)
I (mA)
D
G1-S
(1) VG2-S = 4 V.
(2) G2-S = 3.5 V.
(1)
(2)
V
V
G2-S = 4 V.
V
G2-S = 3.5 V.
(3) VG2-S = 3 V.
(3) VG2-S = 3 V.
(4) VG2-S = 2.5 V.
(4) VG2-S = 2.5 V.
(5)
V
G2-S = 2 V.
(5) VG2-S = 2 V.
(6) VG2-S = 1.5 V.
(7) VG2-S = 1 V.
(6) VG2-S = 1.5 V.
(7) VG2-S = 1 V.
V
DS(b) = 5 V; VDS(a) = VG1-S(a) = 0 V; Tj = 25 C.
VDS(b) = 5 V; VDS(a) = VG1-S(a) = 0 V; Tj = 25 C.
Fig 19. Gate 1 current as a function of gate 1 voltage;
typical values.
Fig 20. Forward transfer admittance as a function of
drain current; typical values.
001aaa572
001aaa573
24
16
I
D
I
D
(mA)
(mA)
12
16
8
4
0
8
0
0
10
20
30
40
I
50
(μA)
0
1
2
3
4
5
V
(V)
G1
GG
VDS(b) = 5 V; VG2-S = 4 V; VDS(a) = VG1-S(a) = 0 V;
V
DS(b) = 5 V; VG2-S = 4 V; VDS(a) = VG1-S(a) = 0 V;
Tj = 25 C.
Tj = 25 C; RG1(b) = 150 k (connected to VGG); see
Figure 3.
Fig 21. Drain current as a function of gate 1 current;
typical values.
Fig 22. Drain current as a function of gate 1 supply
voltage (VGG); typical values.
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BF1205C
NXP Semiconductors
Dual N-channel dual gate MOS-FET
001aaa574
001aaa575
24
16
(1)
(2)
(3)
I
D
(1)
(2)
I
D
(mA)
(mA)
12
(4)
(5)
(3)
(4)
16
(5)
8
4
0
(6)
(7)
(8)
8
0
0
2
4
6
0
2
4
6
V
= V
DS
(V)
V
(V)
G2-S
GG
(1) RG1(b) = 68 k.
(2) G1(b) = 82 k.
(1)
(2)
V
V
GG = 5.0 V.
GG = 4.5 V.
R
(3) RG1(b) = 100 k.
(4) RG1(b) = 120 k.
(3) VGG = 4.0 V.
(4) VGG = 3.5 V.
(5)
R
G1(b) = 150 k.
(5) VGG = 3.0 V.
(6) RG1(b) = 180 k.
(7) RG1(b) = 220 k.
VDS(b) = 5 V; VDS(a) = VG1-S(a) = 0 V; Tj = 25 C;
RG1(b) = 150 k (connected to VGG); see Figure 3.
(8)
RG1(b) = 270 k.
VG2-S = 4 V; VDS(a) = VG1-S(a) = 0 V; Tj = 25 C; RG1(b) is
connected to VGG; see Figure 3.
Fig 23. Drain current as a function of gate 1 (VGG),
drain supply voltage and value of RG1; typical
values.
Fig 24. Drain current as a function of gate 2 voltage;
typical values.
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Product data sheet
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BF1205C
NXP Semiconductors
Dual N-channel dual gate MOS-FET
001aaa576
001aaa577
30
120
V
unw
(1)
(2)
(3)
(4)
(5)
I
G1
(dBμV)
(μA)
110
20
100
90
10
0
80
0
2
4
6
0
20
40
60
V
(V)
gain reduction (dB)
G2-S
(1) VGG = 5.0 V.
(2) GG = 4.5 V.
V
R
DS(b) = 5 V; VGG = 5 V; VDS(a) = VG1-S(a) = 0 V;
G1(b) = 150 k (connected to VGG); fw = 50 MHz;
funw = 60 MHz; Tamb = 25 C; see Figure 34.
V
(3) VGG = 4.0 V.
(4) VGG = 3.5 V.
(5)
VGG = 3.0 V.
VDS(b) = 5 V; VDS(a) = VG1-S(a) = 0 V; Tj = 25 C;
RG1(b) = 150 k (connected to VGG); see Figure 3.
Fig 25. Gate 1 current as a function of gate 2 voltage;
typical values.
Fig 26. Unwanted voltage for 1 % cross-modulation as
a function of gain reduction; typical values.
001aaa578
001aaa579
0
16
gain
reduction
I
D
(dB)
(mA)
10
12
20
30
40
50
8
4
0
0
1
2
3
4
0
20
40
60
V
(V)
gain reduction (dB)
AGC
VDS(b) = 5 V; VGG = 5 V; VDS(a) = VG1-S(a) = 0 V;
G1(b) = 150 k (connected to VGG); f = 50 MHz;
Tamb = 25 C; see Figure 34.
V
R
DS(b) = 5 V; VGG = 5 V; VDS(a) = VG1-S(a) = 0 V;
G1(b) = 150 k (connected to VGG); f = 50 MHz;
Tamb = 25 C; see Figure 34.
R
Fig 27. Typical gain reduction as a function of AGC
voltage.
Fig 28. Drain current as a function of gain reduction;
typical values.
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BF1205C
NXP Semiconductors
Dual N-channel dual gate MOS-FET
001aaa581
001aaa582
2
2
2
10
10
10
b , g
is is
(mS)
y
fs
y
−ϕ
fs
fs
10
(mS)
(deg)
b
g
is
1
10
10
−ϕ
fs
is
−1
10
−2
1
3
10
1
2
3
2
10
10
10
10
10
10
f (MHz)
f (MHz)
VDS(b) = 5 V; VG2-S = 4 V; VDS(a) = VG1-S(a) = 0 V; ID(b)
= 13 mA.
VDS(b) = 5 V; VG2-S = 4 V; VDS(a) = VG1-S(a) = 0 V;
D(b) = 13 mA.
I
Fig 29. Input admittance as a function of frequency;
typical values.
Fig 30. Forward transfer admittance and phase as a
function of frequency; typical values.
001aaa583
001aaa584
3
2
3
10
10
10
y
−ϕ
(deg)
b
, g
os os
rs
rs
(μS)
(mS)
−ϕ
2
rs
b
g
os
10
10
1
y
rs
os
−1
10
10
10
−2
1
3
1
10
2
2
3
10
10
10
10
10
10
f (MHz)
f (MHz)
VDS(b) = 5 V; VG2-S = 4 V; VDS(a) = VG1-S(a) = 0 V;
ID(b) = 13 mA.
V
DS(b) = 5 V; VG2-S = 4 V; VDS(a) = VG1-S(a) = 0 V;
ID(b) = 13 mA.
Fig 31. Reverse transfer admittance and phase as a
function of frequency; typical values.
Fig 32. Output admittance as a function of frequency;
typical values.
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BF1205C
NXP Semiconductors
Dual N-channel dual gate MOS-FET
8.2.2 Scattering parameters for amplifier b
Table 12. Scattering parameters for amplifier b
V
DS(b) = 5 V; VG2-S = 4 V; ID(b) = 13 mA; VDS(a) = 0 V; VG1-S(a) = 0 V; Tamb = 25 C.
S11 S21 S12 S22
Magnitude Angle Magnitude Angle Magnitude Angle Magnitude Angle
f
(MHz)
ratio
(deg) ratio
3.66 3.26
7.01 3.24
13.71 3.22
20.36 3.19
27.04 3.15
33.62 3.10
40.16 3.05
46.70 2.99
52.07 2.92
59.48 2.84
65.86 2.77
(deg)
ratio
(deg) ratio
84.23 0.988
84.91 0.988
83.96 0.986
82.86 0.984
81.88 0.982
80.92 0.978
80.15 0.975
79.68 0.972
78.28 0.968
78.28 0.965
78.15 0.961
(deg)
50
0.986
0.982
0.975
0.966
0.955
0.943
0.927
0.909
0.891
0.868
0.846
175.93 0.0008
172.04 0.0015
164.24 0.0029
156.53 0.0042
148.86 0.0055
141.24 0.0066
133.70 0.0076
126.13 0.0086
118.64 0.0094
111.09 0.0100
103.58 0.0107
1.65
100
200
300
400
500
600
700
800
900
1000
3.27
6.50
9.69
12.88
16.07
19.21
22.35
25.52
28.65
31.85
8.2.3 Noise data for amplifier b
Table 13. Noise data for amplifier b
VDS(b) = 5 V; VG2-S = 4 V; ID(b) = 13 mA; VDS(a) = 0 V; VG1-S(a) = 0 V; Tamb = 25 C.
f
Fmin
(dB)
opt
rn
()
(MHz)
ratio
0.695
0.674
(deg)
13.11
32.77
400
800
1.3
1.4
0.694
0.674
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NXP Semiconductors
Dual N-channel dual gate MOS-FET
9. Test information
V
(a)
DS
5V
V
AGC
4.7 nF
10 kΩ
L1
2.2 μH
4.7 nF
4.7 nF
d (a)
S
g1 (a)
g2
R
GEN
50 Ω
R
L
50 Ω
4.7 nF
4.7 nF
50 Ω
BF1205C
V
i
g1 (b)
d (b)
L2
2.2 μH
50 Ω
R
G1
4.7 nF
V
GG
0V
V
(b)
DS
5V
001aaa563
Fig 33. Cross-modulation test set-up for amplifier a.
V
(a)
5V
V
DS
AGC
4.7 nF
10 kΩ
L1
2.2 μH
4.7 nF
g1 (a)
d (a)
S
4.7 nF
50 Ω
g2
BF1205C
4.7 nF
g1 (b)
4.7 nF
d (b)
R
GEN
50 Ω
L2
2.2 μH
R
L
50 Ω
50 Ω
R
G1
4.7 nF
V
i
V
(b)
DS
5V
V
GG
5V
001aaa580
Fig 34. Cross-modulation test set-up for amplifier b.
BF1205C
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Product data sheet
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BF1205C
NXP Semiconductors
Dual N-channel dual gate MOS-FET
10. Package outline
Plastic surface-mounted package; 6 leads
SOT363
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
1
2
3
c
e
1
b
L
p
w
M B
p
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-08
06-03-16
SOT363
SC-88
Fig 35. Package outline.
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19 of 23
BF1205C
NXP Semiconductors
Dual N-channel dual gate MOS-FET
11. Revision history
Table 14. Revision history
Document ID
BF1205C v.3
Modifications:
Release date
20110907
Data sheet status
Change notice
Supersedes
Product data sheet
-
BF1205C v.2
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
BF1205C v.2
20060815
Product data sheet
-
BF1205C v.1
BF1205C v.1
20040518
Product data sheet
-
-
(9397 750 13005)
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Dual N-channel dual gate MOS-FET
12. Legal information
12.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
12.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
12.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
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Dual N-channel dual gate MOS-FET
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
12.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
13. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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Dual N-channel dual gate MOS-FET
14. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
General description . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits. . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . 2
2
3
4
5
6
7
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal characteristics . . . . . . . . . . . . . . . . . . 3
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
8
8.1
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics for amplifier a. . . . . . . 5
Graphs for amplifier a. . . . . . . . . . . . . . . . . . . . 6
Scattering parameters for amplifier a . . . . . . . 10
Noise data for amplifier a . . . . . . . . . . . . . . . . 10
Dynamic characteristics for amplifier b. . . . . . 11
Graphs for amplifier b. . . . . . . . . . . . . . . . . . . 12
Scattering parameters for amplifier b . . . . . . . 17
Noise data for amplifier b . . . . . . . . . . . . . . . . 17
8.1.1
8.1.2
8.1.3
8.2
8.2.1
8.2.2
8.2.3
9
Test information. . . . . . . . . . . . . . . . . . . . . . . . 18
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20
10
11
12
Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
12.1
12.2
12.3
12.4
13
14
Contact information. . . . . . . . . . . . . . . . . . . . . 22
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 September 2011
Document identifier: BF1205C
相关型号：
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