BF1204,135 [NXP]
Dual N-channel dual-gate MOSFET TSSOP 6-Pin;
| 型号： | BF1204,135 |
| 厂家： | 
NXP |
| 描述： | Dual N-channel dual-gate MOSFET TSSOP 6-Pin |
| 文件： | 总13页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DISCRETE SEMICONDUCTORS
DATA SHEET
andbook, halfpage
BF1204
Dual N-channel dual gate
MOS-FET
Product specification
2010 Sep 16
Supersedes data of 2001 Apr 25
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
FEATURES
PINNING - SOT363
PIN
Two low noise gain controlled amplifiers in a single
package
DESCRIPTION
1
2
3
4
5
6
gate 1 (a)
gate 2
Superior cross-modulation performance during AGC
High forward transfer admittance
gate 1 (b)
drain (b)
source
High forward transfer admittance to input capacitance
ratio.
drain (a)
APPLICATIONS
Gain controlled low noise amplifiers for VHF and UHF
applications with 3 to 9 V supply voltage, such as digital
and analog television tuners and professional
communications equipment.
handbook, halfpage
d (a)
s
d (b)
6
5
4
AMP
a
AMP
b
DESCRIPTION
The BF1204 is a combination of two equal dual gate
MOS-FET amplifiers with shared source and gate 2 leads.
The source and substrate are interconnected. Internal bias
circuits enable DC stabilization and a very good
cross-modulation performance during AGC. Integrated
diodes between the gates and source protect against
excessive input voltage surges. The transistor has a
SOT363 micro-miniature plastic package.
1
2
3
g1 (a)
g2
g1 (b)
Top view
MBL252
Marking code: L3*
* = - : made in Hong Kong
* = p : made in Hong Kong
* = t : made in Malaysia
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
Per MOS-FET; unless otherwise specified
VDS
ID
drain-source voltage
10
30
200
40
2.2
V
drain current (DC)
mA
mW
mS
pF
Ptot
yfs
Cig1-s
Crss
NF
total power dissipation
forward transfer admittance
input capacitance at gate 1
reverse transfer capacitance
noise figure
Ts 102 C; note 1
ID = 12 mA; f = 1 MHz
ID = 12 mA; f = 1 MHz
f = 1 MHz
25
30
1.7
15
1.1
105
fF
f = 800 MHz
1.8
dB
Xmod
Tj
cross-modulation
input level for k = 1% at 40 dB AGC 100
dBV
C
operating junction temperature
150
Note
1. Ts is the temperature at the soldering point of the source lead.
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling.
2010 Sep 16
2
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Per MOS-FET; unless otherwise specified
VDS
ID
drain-source voltage
drain current (DC)
10
V
30
mA
mA
mA
mW
C
IG1
IG2
Ptot
Tstg
Tj
gate 1 current
10
10
200
+150
150
gate 2 current
total power dissipation
storage temperature
operating junction temperature
Ts 102 C
65
C
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
VALUE
UNIT
Rth j-s
thermal resistance from junction to soldering point
240
K/W
MGS359
250
handbook, halfpage
P
tot
(mW)
200
150
100
50
0
0
50
100
150
200
T
(°C)
s
Fig.2 Power derating curve.
2010 Sep 16
3
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
STATIC CHARACTERISTICS
Tj = 25 C; per MOS-FET; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. MAX. UNIT
V(BR)DSS
drain-source breakdown voltage VG1-S = VG2-S = 0; ID = 10 A
10
6
V
V(BR)G1-SS gate-source breakdown voltage VGS = VDS = 0; IG1-S = 10 mA
V(BR)G2-SS gate-source breakdown voltage VGS = VDS = 0; IG2-S = 10 mA
10
10
1.5
1.5
1
V
6
V
V(F)S-G1
V(F)S-G2
VG1-S(th)
VG2-S(th)
IDSX
forward source-gate voltage
forward source-gate voltage
gate-source threshold voltage
gate-source threshold voltage
drain-source current
VG2-S = VDS = 0; IS-G1 = 10 mA
VG1-S = VDS = 0; IS-G2 = 10 mA
VDS = 5 V; VG2-S = 4 V; ID = 100 A
VDS = 5 V; VG1-S = 4 V; ID = 100 A
VG2-S = 4 V; VDS = 5 V; RG = 120 k; note 1
VG1-S = 5 V; VG2-S = VDS = 0
0.5
0.5
0.3
0.3
8
V
V
V
1.2
16
50
20
V
mA
nA
nA
IG1-S
gate cut-off current
IG2-S
gate cut-off current
VG2-S = 4 V; VG1-S = VDS = 0
Note
1.
RG1 connects gate 1 to VGG = 5 V.
DYNAMIC CHARACTERISTICS
Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 12 mA; per MOS-FET (1); unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
25
TYP. MAX. UNIT
yfs
Cig1-ss
Cig2-ss
Coss
Crss
forward transfer admittance
input capacitance at gate 1
input capacitance at gate 2
output capacitance
Tj = 25 C
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
30
40
2.2
mS
pF
pF
pF
fF
1.7
3.3
0.85
15
reverse transfer capacitance
power gain
Gtr
f = 200 MHz; GS = 2 mS; BS = BS(opt)
GL = 0.5 mS; BL = BL(opt); note 1
;
;
30
34
38
dB
f = 400 MHz; GS = 2 mS; BS = BS(opt)
GL = 1 mS; BL = BL(opt); note 1
26
21
30
25
34
29
dB
dB
f = 800 MHz; GS = 3.3 mS; BS = BS(opt)
;
GL = 1 mS; BL = BL(opt); note 1
NF
noise figure
f = 10.7 MHz; GS = 20 mS; BS = 0
f = 400 MHz; YS = YS(opt)
9
11
1.5
1.8
dB
0.9
1.1
dB
f = 800 MHz; YS = YS(opt)
dB
Xmod
cross-modulation
input level for k = 1% at 0 dB AGC;
fw = 50 MHz; funw = 60 MHz; note 2
90
dBV
input level for k = 1% at 10 dB AGC;
fw = 50 MHz; funw = 60 MHz; note 2
92
dBV
dBV
input level for k = 1% at 40 dB AGC;
fw = 50 MHz; funw = 60 MHz; note 2
100
105
Notes
1. For the MOS-FET not in use: VG1-S = 0; VDS = 0.
2. Measured in Fig.19 test circuit.
2010 Sep 16
4
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
ALL GRAPHS FOR ONE MOS-FET
MCD952
MCD953
20
24
handbook, halfpage
handbook, halfpage
V
= 4 V
G2-S
I
2.5 V
D
(mA)
16
V
= 1.5 V
3.5 V
3 V
I
G1-S
D
(mA)
2 V
1.4 V
1.3 V
16
12
8
1.5 V
1.2 V
1.1 V
8
1 V
4
0
1 V
0.9 V
0
0
0
0.4
0.8
1.2
1.6
2
(V)
2
4
6
8
10
(V)
V
V
G1-S
DS
VDS = 5 V.
VG2-S = 4 V.
Tj = 25 C.
Tj = 25 C.
Fig.3 Transfer characteristics; typical values.
Fig.4 Output characteristics; typical values.
MCD955
MCD954
100
40
handbook, halfpage
handbook, halfpage
3.5 V
3 V
V
= 4 V
I
G2-S
3.5 V
G1
(μA)
80
y
fs
(mS)
V
= 4 V
G2-S
30
3 V
60
40
2.5 V
2 V
20
10
0
2.5 V
20
0
2 V
1.5 V
1 V
0
0.5
1
1.5
2
2.5
(V)
0
4
8
12
16
I
20
(mA)
V
D
G1-S
VDS = 5 V.
VDS = 5 V.
Tj = 25 C.
Tj = 25 C.
Fig.5 Gate 1 current as a function of gate 1
voltage; typical values.
Fig.6 Forward transfer admittance as a function
of drain current; typical values.
2010 Sep 16
5
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
MCD957
MCD956
20
16
handbook, halfpage
handbook, halfpage
I
D
(mA)
16
I
D
(mA)
12
12
8
8
4
4
0
0
0
0
10
20
30
40
I
50
(μA)
1
2
3
4
V
5
(V)
GG
G1
VDS = 5 V; VG2-S = 4 V; Tj = 25 C.
RG1 = 120 k (connected to VGG); see Fig.19.
VDS = 5 V; VG2-S = 4 V.
Tj = 25 C.
Fig.7 Drain current as a function of gate 1 current;
typical values.
Fig.8 Drain current as a function of gate 1 supply
voltage (= VGG); typical values.
MCD958
MCD959
20
16
handbook, halfpage
handbook, halfpage
R
= 68 kΩ
I
G1
D
(mA)
16
I
D
(mA)
V
= 5 V
GG
82 kΩ
4.5 V
12
8
4 V
100 kΩ
120 kΩ
3.5 V
3 V
12
8
150 kΩ
180 kΩ
220 kΩ
4
4
0
0
0
2
4
6
(V)
0
2
4
6
V
(V)
V
= V
G2-S
GG
DS
VG2-S = 4 V; Tj = 25 C.
G1 connected to VGG; see Fig.19.
VDS = 5 V; Tj = 25 C.
RG1 = 120 k (connected to VGG); see Fig.19.
R
Fig.9 Drain current as a function of gate 1 (= VGG
)
Fig.10 Drain current as a function of gate 2
voltage; typical values.
and drain supply voltage; typical values.
2010 Sep 16
6
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
MCD961
MCD960
40
0
handbook, halfpage
handbook, halfpage
gain
I
reduction
(dB)
G1
(μA)
V
= 5 V
GG
−10
30
20
10
0
4.5 V
−20
−30
4 V
3.5 V
3 V
−40
−50
0
2
4
6
0
1
2
3
4
V
(V)
V
(V)
AGC
G2-S
VDS = 5 V; Tj = 25 C.
RG1 = 120 k (connected to VGG); see Fig.19.
VDS = 5 V; VGG = 5 V; RG1 = 120 k;
f = 50 MHz; Tamb = 25 C.
Fig.11 Gate 1 current as a function of gate 2
voltage; typical values.
Fig.12 Typical gain reduction as a function of AGC
voltage; see Fig.19.
MCD962
MCD963
120
16
handbook, halfpage
handbook, halfpage
I
V
D
unw
(mA)
(dBμV)
110
12
100
90
8
4
0
80
0
10
20
30
40
50
0
10
20
30
40
50
gain reduction (dB)
gain reduction (dB)
VDS = 5 V; VGG = 5 V; RG1 = 120 k;
f= 50 MHz; funw = 60 MHz; Tamb = 25 C.
VDS = 5 V; VGG = 5 V; RG1 = 120 k;
f = 50 MHz; Tamb = 25 C.
Fig.13 Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical
values; see Fig.19.
Fig.14 Drain current as a function of gain
reduction; typical values; see Fig.19.
2010 Sep 16
7
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
MLD429
MLD430
3
2
3
10
10
−10
handbook, halfpage
handbook, halfpage
ϕ
(deg)
y
rs
Y
is
(mS)
rs
(μS)
ϕ
rs
2
2
10
−10
10
b
is
y
rs
g
is
−10
−1
1
10
−1
10
10
1
2
3
2
3
10
10
10
10
10
f (MHz)
f (MHz)
VDS = 5 V; VG2 = 4 V.
VDS = 5 V; VG2 = 4 V.
Fig.15 Input admittance as a function of frequency;
typical values.
Fig.16 Reverse transfer admittance and phase as
a function of frequency; typical values.
MLD431
MLD432
2
2
10
−10
10
handbook, halfpage
handbook, halfpage
ϕ
(deg)
y
Y
fs
fs
os
(mS)
(mS)
y
fs
b
os
1
10
−10
ϕ
fs
−1
10
g
os
−2
10
−1
1
10
2
3
2
3
10
10
10
10
10
f (MHz)
f (MHz)
VDS = 5 V; VG2 = 4 V.
VDS = 5 V; VG2 = 4 V.
Fig.17 Forward transfer admittance and phase as
a function of frequency; typical values.
Fig.18 Output admittance as a function of
frequency; typical values.
2010 Sep 16
8
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
V
AGC
R1
10 kΩ
C1
4.7 nF
C3
4.7 nF
R
50 Ω
L1
≈2.2 μH
L
C2
DUT
C4
4.7 nF
R
GEN
50 Ω
R2
50 Ω
R
G1
4.7 nF
V
V
V
I
GG
DS
MGS315
Fig.19 Cross-modulation test set-up (for one MOS-FET).
Scattering parameters
VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 C.
s11
s21
s12
s22
f
MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE
(MHz)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
50
100
200
300
400
500
600
700
800
900
1000
0.991
0.987
0.981
0.969
0.958
0.939
0.921
0.898
0.874
0.847
0.817
3.29
7.12
2.95
2.90
2.86
2.83
2.79
2.74
2.68
2.62
2.55
2.49
2.41
175.78
171.61
163.45
155.11
147.37
139.04
131.35
123.38
115.74
107.84
100.24
0.00060
0.00119
0.00234
0.00339
0.00429
0.00508
0.00565
0.00611
0.00646
0.00662
0.00670
85.25
84.74
80.85
75.77
72.23
68.24
64.97
61.90
57.77
55.04
52.16
0.995
0.994
0.992
0.989
0.987
0.983
0.981
0.976
0.973
0.969
0.966
1.44
2.90
14.21
21.22
28.14
35.01
41.75
48.51
54.96
61.62
67.84
5.70
8.50
11.25
13.96
16.67
19.36
22.04
24.80
27.45
2010 Sep 16
9
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
PACKAGE OUTLINE
Plastic surface-mounted package; 6 leads
SOT363
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
1
2
3
c
e
1
b
L
p
w
M B
p
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-08
06-03-16
SOT363
SC-88
2010 Sep 16
10
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
DATA SHEET STATUS
DOCUMENT
STATUS(1)
PRODUCT
STATUS(2)
DEFINITION
Objective data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary data sheet
Product data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
DISCLAIMERS
property or environmental damage. NXP Semiconductors
accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at
the customer’s own risk.
Limited warranty and liability Information in this
document is believed to be accurate and reliable.
However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
information.
Applications Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
In no event shall NXP Semiconductors be liable for any
indirect, incidental, punitive, special or consequential
damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the
removal or replacement of any products or rework
charges) whether or not such damages are based on tort
(including negligence), warranty, breach of contract or any
other legal theory.
Customers are responsible for the design and operation of
their applications and products using NXP
Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or
customer product design. It is customer’s sole
responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as
for the planned application and use of customer’s third
party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks
associated with their applications and products.
Notwithstanding any damages that customer might incur
for any reason whatsoever, NXP Semiconductors’
aggregate and cumulative liability towards customer for
the products described herein shall be limited in
accordance with the Terms and conditions of commercial
sale of NXP Semiconductors.
NXP Semiconductors does not accept any liability related
to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third
party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and
products using NXP Semiconductors products in order to
avoid a default of the applications and the products or of
the application or use by customer’s third party
customer(s). NXP does not accept any liability in this
respect.
Right to make changes NXP Semiconductors
reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
Suitability for use NXP Semiconductors products are
not designed, authorized or warranted to be suitable for
use in life support, life-critical or safety-critical systems or
equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe
2010 Sep 16
11
NXP Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
Limiting values Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
Quick reference data The Quick reference data is an
extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.
Non-automotive qualified products Unless this data
sheet expressly states that this specific NXP
Semiconductors product is automotive qualified, the
product is not suitable for automotive use. It is neither
qualified nor tested in accordance with automotive testing
or application requirements. NXP Semiconductors accepts
no liability for inclusion and/or use of non-automotive
qualified products in automotive equipment or
applications.
Terms and conditions of commercial sale NXP
Semiconductors products are sold subject to the general
terms and conditions of commercial sale, as published at
http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an
individual agreement is concluded only the terms and
conditions of the respective agreement shall apply. NXP
Semiconductors hereby expressly objects to applying the
customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
In the event that customer uses the product for design-in
and use in automotive applications to automotive
specifications and standards, customer (a) shall use the
product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and
specifications, and (b) whenever customer uses the
product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at
customer’s own risk, and (c) customer fully indemnifies
NXP Semiconductors for any liability, damages or failed
product claims resulting from customer design and use of
the product for automotive applications beyond NXP
Semiconductors’ standard warranty and NXP
No offer to sell or license Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Semiconductors’ product specifications.
Export control This document as well as the item(s)
described herein may be subject to export control
regulations. Export might require a prior authorization from
national authorities.
2010 Sep 16
12
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for the marking codes
and the package outline drawings which were updated to the latest version.
Contact information
For additional information please visit: http://www.nxp.com
For sales offices addresses send e-mail to: salesaddresses@nxp.com
© NXP B.V. 2010
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R77/03/pp13
Date of release: 2010 Sep 16
相关型号：
BF1204T/R
TRANSISTOR 2 CHANNEL, UHF BAND, Si, N-CHANNEL, RF SMALL SIGNAL, MOSFET, MICRO MINIATURE, PLASTIC, SC-88, 6 PIN, FET RF Small Signal
NXP
©2020 ICPDF网 联系我们和版权申明