BF1204_15 [JMNIC]
Dual N-channel dual gate MOS-FET;
| 型号： | BF1204_15 |
| 厂家： | 
QUANZHOU JINMEI ELECTRONIC CO.,LTD. |
| 描述： | Dual N-channel dual gate MOS-FET |
| 文件： | 总12页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DISCRETE SEMICONDUCTORS
DATA SHEET
andbook, halfpage
BF1204
Dual N-channel dual gate
MOS-FET
Product specification
2001 Apr 25
Supersedes data of 2000 Nov 13
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
FEATURES
PINNING - SOT363
PIN
• Two low noise gain controlled amplifiers in a single
package
DESCRIPTION
1
2
3
4
5
6
gate 1 (a)
gate 2
• Superior cross-modulation performance during AGC
• High forward transfer admittance
gate 1 (b)
drain (b)
source
• High forward transfer admittance to input capacitance
ratio.
drain (a)
APPLICATIONS
• Gain controlled low noise amplifiers for VHF and UHF
applications with 3 to 9 V supply voltage, such as digital
and analog television tuners and professional
communications equipment.
handbook, halfpage
d (a)
s
d (b)
6
5
4
DESCRIPTION
AMP
a
AMP
b
The BF1204 is a combination of two equal dual gate
MOS-FET amplifiers with shared source and gate 2 leads.
The source and substrate are interconnected. Internal bias
circuits enable DC stabilization and a very good
cross-modulation performance during AGC. Integrated
diodes between the gates and source protect against
excessive input voltage surges. The transistor has a
SOT363 micro-miniature plastic package.
1
2
3
g1 (a)
g2
g1 (b)
Top view
MBL252
Marking code: L3-
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
Per MOS-FET; unless otherwise specified
VDS
ID
drain-source voltage
−
−
10
30
200
40
2.2
−
V
drain current (DC)
−
−
mA
mW
mS
pF
Ptot
yfs
total power dissipation
forward transfer admittance
input capacitance at gate 1
reverse transfer capacitance
noise figure
Ts ≤ 102 °C; note 1
−
−
ID = 12 mA; f = 1 MHz
ID = 12 mA; f = 1 MHz
f = 1 MHz
25
−
30
1.7
15
1.1
105
−
Cig1-s
Crss
NF
−
fF
f = 800 MHz
−
1.8
−
dB
Xmod
Tj
cross-modulation
input level for k = 1% at 40 dB AGC 100
dBµV
°C
operating junction temperature
−
150
Note
1. Ts is the temperature at the soldering point of the source lead.
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.
2001 Apr 25
2
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Per MOS-FET; unless otherwise specified
VDS
ID
drain-source voltage
drain current (DC)
−
−
−
−
−
10
V
30
mA
mA
mA
mW
°C
IG1
IG2
Ptot
Tstg
Tj
gate 1 current
±10
±10
200
+150
150
gate 2 current
total power dissipation
storage temperature
operating junction temperature
Ts ≤ 102 °C
−65
−
°C
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
VALUE
UNIT
Rth j-s
thermal resistance from junction to soldering point
240
K/W
MGS359
250
handbook, halfpage
P
tot
(mW)
200
150
100
50
0
0
50
100
150
200
T
(°C)
s
Fig.2 Power derating curve.
2001 Apr 25
3
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
STATIC CHARACTERISTICS
Tj = 25 °C; per MOS-FET; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. MAX. UNIT
V(BR)DSS
drain-source breakdown voltage VG1-S = VG2-S = 0; ID = 10 µA
10
6
−
V
V(BR)G1-SS gate-source breakdown voltage VGS = VDS = 0; IG1-S = 10 mA
V(BR)G2-SS gate-source breakdown voltage VGS = VDS = 0; IG2-S = 10 mA
10
10
1.5
1.5
1
V
6
V
V(F)S-G1
V(F)S-G2
VG1-S(th)
VG2-S(th)
IDSX
forward source-gate voltage
forward source-gate voltage
gate-source threshold voltage
gate-source threshold voltage
drain-source current
VG2-S = VDS = 0; IS-G1 = 10 mA
VG1-S = VDS = 0; IS-G2 = 10 mA
VDS = 5 V; VG2-S = 4 V; ID = 100 µA
VDS = 5 V; VG1-S = 4 V; ID = 100 µA
VG2-S = 4 V; VDS = 5 V; RG = 120 kΩ; note 1
VG1-S = 5 V; VG2-S = VDS = 0
0.5
0.5
0.3
0.3
8
V
V
V
1.2
16
50
20
V
mA
nA
nA
IG1-S
gate cut-off current
−
IG2-S
gate cut-off current
VG2-S = 4 V; VG1-S = VDS = 0
−
Note
1. RG1 connects gate 1 to VGG = 5 V.
DYNAMIC CHARACTERISTICS
Common source; Tamb = 25 °C; VG2-S = 4 V; VDS = 5 V; ID = 12 mA; per MOS-FET (1); unless otherwise specified.
SYMBOL
yfs
PARAMETER
CONDITIONS
MIN.
25
TYP. MAX. UNIT
forward transfer admittance
input capacitance at gate 1
input capacitance at gate 2
output capacitance
Tj = 25 °C
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
30
40
2.2
−
mS
pF
pF
pF
fF
Cig1-ss
Cig2-ss
Coss
−
1.7
3.3
0.85
15
−
−
−
Crss
reverse transfer capacitance
power gain
−
−
Gtr
f = 200 MHz; GS = 2 mS; BS = BS(opt)
GL = 0.5 mS; BL = BL(opt); note 1
;
;
30
34
38
dB
f = 400 MHz; GS = 2 mS; BS = BS(opt)
GL = 1 mS; BL = BL(opt); note 1
26
21
30
25
34
29
dB
dB
f = 800 MHz; GS = 3.3 mS; BS = BS(opt)
GL = 1 mS; BL = BL(opt); note 1
;
NF
noise figure
f = 10.7 MHz; GS = 20 mS; BS = 0
f = 400 MHz; YS = YS(opt)
−
9
11
1.5
1.8
−
dB
−
0.9
1.1
−
dB
f = 800 MHz; YS = YS(opt)
−
dB
Xmod
cross-modulation
input level for k = 1% at 0 dB AGC;
fw = 50 MHz; funw = 60 MHz; note 2
90
dBµV
input level for k = 1% at 10 dB AGC;
fw = 50 MHz; funw = 60 MHz; note 2
−
92
−
−
dBµV
dBµV
input level for k = 1% at 40 dB AGC;
fw = 50 MHz; funw = 60 MHz; note 2
100
105
Notes
1. For the MOS-FET not in use: VG1-S = 0; VDS = 0.
2. Measured in Fig.19 test circuit.
2001 Apr 25
4
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
ALL GRAPHS FOR ONE MOS-FET
MCD952
MCD953
20
24
handbook, halfpage
handbook, halfpage
V
= 4 V
G2-S
I
2.5 V
D
(mA)
16
V
= 1.5 V
3.5 V
3 V
I
G1-S
D
(mA)
2 V
1.4 V
1.3 V
16
12
8
1.5 V
1.2 V
1.1 V
8
1 V
4
0
1 V
0.9 V
0
0
0
0.4
0.8
1.2
1.6
2
(V)
2
4
6
8
10
(V)
V
V
G1-S
DS
VDS = 5 V.
VG2-S = 4 V.
Tj = 25 °C.
Tj = 25 °C.
Fig.3 Transfer characteristics; typical values.
Fig.4 Output characteristics; typical values.
MCD955
MCD954
100
40
handbook, halfpage
handbook, halfpage
3.5 V
3 V
V
= 4 V
I
G2-S
3.5 V
G1
(µA)
y
fs
(mS)
V
= 4 V
G2-S
80
30
3 V
60
40
2.5 V
2 V
20
10
0
2.5 V
20
0
2 V
1.5 V
1 V
0
0.5
1
1.5
2
2.5
(V)
0
4
8
12
16
I
20
(mA)
V
D
G1-S
VDS = 5 V.
VDS = 5 V.
Tj = 25 °C.
Tj = 25 °C.
Fig.5 Gate 1 current as a function of gate 1
voltage; typical values.
Fig.6 Forward transfer admittance as a function
of drain current; typical values.
2001 Apr 25
5
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
MCD957
MCD956
20
16
handbook, halfpage
handbook, halfpage
I
D
(mA)
16
I
D
(mA)
12
12
8
8
4
4
0
0
0
0
10
20
30
40
I
50
(µA)
1
2
3
4
V
5
(V)
GG
G1
VDS = 5 V; VG2-S = 4 V; Tj = 25 °C.
RG1 = 120 kΩ (connected to VGG); see Fig.19.
VDS = 5 V; VG2-S = 4 V.
Tj = 25 °C.
Fig.7 Drain current as a function of gate 1 current;
typical values.
Fig.8 Drain current as a function of gate 1 supply
voltage (= VGG); typical values.
MCD958
MCD959
20
16
handbook, halfpage
handbook, halfpage
R
= 68 kΩ
I
G1
D
(mA)
16
I
D
(mA)
V
= 5 V
GG
82 kΩ
4.5 V
12
8
4 V
100 kΩ
120 kΩ
3.5 V
3 V
12
8
150 kΩ
180 kΩ
220 kΩ
4
4
0
0
0
2
4
6
(V)
0
2
4
6
V
(V)
V
= V
G2-S
GG
DS
VG2-S = 4 V; Tj = 25 °C.
RG1 connected to VGG; see Fig.19.
VDS = 5 V; Tj = 25 °C.
RG1 = 120 kΩ (connected to VGG); see Fig.19.
Fig.9 Drain current as a function of gate 1 (= VGG
and drain supply voltage; typical values.
)
Fig.10 Drain current as a function of gate 2
voltage; typical values.
2001 Apr 25
6
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
MCD961
MCD960
40
0
handbook, halfpage
handbook, halfpage
gain
I
reduction
(dB)
G1
(µA)
V
= 5 V
GG
−10
30
20
10
0
4.5 V
−20
−30
4 V
3.5 V
3 V
−40
−50
0
2
4
6
0
1
2
3
4
V
(V)
V
(V)
AGC
G2-S
VDS = 5 V; Tj = 25 °C.
RG1 = 120 kΩ (connected to VGG); see Fig.19.
VDS = 5 V; VGG = 5 V; RG1 = 120 kΩ;
f = 50 MHz; Tamb = 25 °C.
Fig.11 Gate 1 current as a function of gate 2
voltage; typical values.
Fig.12 Typical gain reduction as a function of AGC
voltage; see Fig.19.
MCD962
MCD963
120
16
handbook, halfpage
handbook, halfpage
I
V
D
unw
(mA)
(dBµV)
110
12
100
90
8
4
0
80
0
10
20
30
40
50
0
10
20
30
40
50
gain reduction (dB)
gain reduction (dB)
VDS = 5 V; VGG = 5 V; RG1 = 120 kΩ;
f= 50 MHz; funw = 60 MHz; Tamb = 25 °C.
VDS = 5 V; VGG = 5 V; RG1 = 120 kΩ;
f = 50 MHz; Tamb = 25 °C.
Fig.13 Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical
values; see Fig.19.
Fig.14 Drain current as a function of gain
reduction; typical values; see Fig.19.
2001 Apr 25
7
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
MLD429
MLD430
3
2
3
10
10
−10
handbook, halfpage
handbook, halfpage
ϕ
y
rs
Y
is
(mS)
rs
(deg)
(µS)
ϕ
rs
2
2
10
−10
10
b
is
y
rs
g
is
−10
−1
1
10
−1
10
1
2
3
2
3
10
10
10
10
10
10
f (MHz)
f (MHz)
VDS = 5 V; VG2 = 4 V.
VDS = 5 V; VG2 = 4 V.
Fig.15 Input admittance as a function of frequency;
typical values.
Fig.16 Reverse transfer admittance and phase as
a function of frequency; typical values.
MLD431
MLD432
2
2
10
−10
10
handbook, halfpage
handbook, halfpage
ϕ
y
Y
fs
fs
os
(deg)
(mS)
(mS)
y
fs
b
os
1
10
−10
ϕ
fs
−1
10
g
os
−2
−1
1
10
2
3
2
3
10
10
10
10
10
10
f (MHz)
f (MHz)
VDS = 5 V; VG2 = 4 V.
VDS = 5 V; VG2 = 4 V.
Fig.17 Forward transfer admittance and phase as
a function of frequency; typical values.
Fig.18 Output admittance as a function of
frequency; typical values.
2001 Apr 25
8
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
V
AGC
R1
10 kΩ
C1
4.7 nF
C3
4.7 nF
R
50 Ω
L1
≈2.2 µH
L
C2
DUT
C4
4.7 nF
R
GEN
50 Ω
R2
50 Ω
R
G1
4.7 nF
V
V
V
I
GG
DS
MGS315
Fig.19 Cross-modulation test set-up (for one MOS-FET).
Scattering parameters
VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 °C.
s11
s21
s12
s22
f
MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE
(MHz)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
(ratio)
(deg)
50
100
200
300
400
500
600
700
800
900
1000
0.991
0.987
0.981
0.969
0.958
0.939
0.921
0.898
0.874
0.847
0.817
−3.29
−7.12
2.95
2.90
2.86
2.83
2.79
2.74
2.68
2.62
2.55
2.49
2.41
175.78
171.61
163.45
155.11
147.37
139.04
131.35
123.38
115.74
107.84
100.24
0.00060
0.00119
0.00234
0.00339
0.00429
0.00508
0.00565
0.00611
0.00646
0.00662
0.00670
85.25
84.74
80.85
75.77
72.23
68.24
64.97
61.90
57.77
55.04
52.16
0.995
0.994
0.992
0.989
0.987
0.983
0.981
0.976
0.973
0.969
0.966
−1.44
−2.90
−14.21
−21.22
−28.14
−35.01
−41.75
−48.51
−54.96
−61.62
−67.84
−5.70
−8.50
−11.25
−13.96
−16.67
−19.36
−22.04
−24.80
−27.45
2001 Apr 25
9
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
PACKAGE OUTLINE
Plastic surface mounted package; 6 leads
SOT363
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
1
2
3
c
e
1
b
p
L
p
w
M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
97-02-28
SOT363
SC-88
2001 Apr 25
10
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1204
DATA SHEET STATUS
PRODUCT
DATA SHEET STATUS(1)
STATUS(2)
DEFINITIONS
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2001 Apr 25
11
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Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Hungary: Philips Hungary Ltd., H-1119 Budapest, Fehervari ut 84/A,
Tel: +36 1 382 1700, Fax: +36 1 382 1800
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,
Tel. +66 2 361 7910, Fax. +66 2 398 3447
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
Tel. +39 039 203 6838, Fax +39 039 203 6800
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 3341 299, Fax.+381 11 3342 553
Middle East: see Italy
For all other countries apply to: Philips Semiconductors,
Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
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© Philips Electronics N.V. 2001
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613512/02/pp12
Date of release: 2001 Apr 25
Document order number: 9397 750 08297
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