5962L0620601VZA [NSC]
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November 30, 2010
LMP2012QML
Dual High Precision, Rail-to-Rail Output Operational
Amplifier
General Description
Features
The LMP2012 offers unprecedented accuracy and stability.
This device utilizes patented techniques to measure and con-
tinually correct the input offset error voltage. The result is an
amplifier which is ultra stable over time and temperature. It
has excellent CMRR and PSRR ratings, and does not exhibit
the familiar 1/f voltage and current noise increase that
plagues traditional amplifiers. The combination of the
LMP2012 characteristics makes it a good choice for trans-
ducer amplifiers, high gain configurations, ADC buffer ampli-
fiers, DAC I-V conversion, and any other 2.7V-5V application
requiring precision and long term stability.
Total Ionizing Dose
50 krad(Si)
50 krad(Si)
0.015 µV/°C
■
ELDRS Free
TCVIO Temperture Sensitivity (Typical)
■
■
(For VS = 5V, Typical unless otherwise noted)
Low guaranteed VIO over temperature
Low noise with no 1/f
High CMRR
High PSRR
High AVOL
Wide gain-bandwidth product
High slew rate
Rail-to-rail output
60 µV
35nV/
90 dB
90 dB
85 dB
3MHz
4V/µs
■
■
■
■
■
■
Other useful benefits of the LMP2012 are rail-rail output, low
supply current of 930 μA, and wide gain-bandwidth product of
3 MHz. These extremely versatile features found in the
LMP2012 provide high performance and ease of use.
■
30mV
■
No external capacitors required
■
The QMLV version of the LMP2012 has been rated to tolerate
a total dose level of 50krad/(Si) radiation by test method 1019
of MIL-STD-883.
Applications
Attitude and Orbital Controls
■
■
■
■
■
■
Static Earth Sensing
Sun Sensors
Inertial Sensors
Pressure Sensors
Gyroscopes
Earth Observation Systems
■
Ordering Information
NS Part Number
LMP2012WG-QMLV
SMD Part Number
NS Package Number
Package Discription
10LD CERAMIC SOIC
5962-0620601VZA
WG10A
5962L0620601VZA
50 krad(Si)
LMP2012WGLQMLV
WG10A
WG10A
10LD CERAMIC SOIC
10LD CERAMIC SOIC
LMP2012WGLLQMLV
ELDRS Free
5962L0620602VZA
50 krad(Si)
Connection Diagram
10LD Ceramic SOIC
20182202
Top View
See NS Package Number WG10A
© 2010 National Semiconductor Corporation
201822
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Absolute Maximum Ratings (Note 1)
Supply Voltage
Differential Input Voltage
Power Dissipation (Note 2)
5.8V
±Supply Voltage
714mW
Maximum Junction Temperature (TJmax
Common-Mode Input Voltage
)
150°C
-0.3 ≤ VCM ≤ VCC +0.3V
30 mA
Current at Input Pin
Current at Output Pin
30 mA
Current at Power Supply Pin
Operating Temperature Range
Storage Temperature Range
Ceramic SOIC Lead Temperature (soldering 10 sec.)
Thermal Resistance
ꢀꢀθJA
50 mA
-55°C to +125°C
-55°C to +150°C
+260°C
Ceramic SOIC (Still Air)
Ceramic SOIC (500LF/Min Air Flow)
ꢀꢀθJC
175°C/W
115°C/W
Ceramic SOIC
12.3°C/W
Package Weight
Ceramic SOIC
ESD Tolerance (Note 3)
220mg
4000V
Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
Subgroup
Description
Static tests at
Temp (°C)
+25
1
2
Static tests at
+125
-55
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Setting time at
+25
5
+125
-55
6
7
+25
8A
8B
9
+125
-55
+25
10
11
12
13
14
+125
-55
+25
Setting time at
+125
-55
Setting time at
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2
LMP2012 Electrical Characteristics
2.7V DC Parameters
The following conditions apply, unless otherwise specified.
V+ = 2.7V, V- = 0V, V CM = 1.35V, VO = 1.35V and RL > 1 MΩ.
Typ
(Note 4)
Sub-
groups
Symbol
VIO
Parameter
Input Offset Voltage
Offset Calibration Time
Conditions
Notes
Min
Max
Units
μV
0.8
0.5
36
60
10
12
1
2, 3
1
ms
2, 3
TCVIO
Input Offset Voltage
(Temperature Sensitivity)
0.015
µV/°C
IIB
Input Bias Current
−3
6
pA
pA
IIO
Input Offset Current
CMRR
Common Mode Rejection Ratio
130
95
1
−0.3 ≤ VCM ≤ 0.9V
0 ≤ VCM ≤ 0.9V
dB
dB
90
95
2, 3
1
PSRR
AVOL
Power Supply Rejection Ratio
Open Loop Voltage Gain
120
130
90
2, 3
1
95
RL = 10 kΩ
RL = 2 kΩ
90
2, 3
1
dB
V
124
90
85
2, 3
1
VO
Output Swing
2.68
0.033
2.65
0.061
12
2.64
2.63
2, 3
1
RL = 10 kΩ to 1.35V
VIN(diff) = ±0.5V
0.060
0.075
2,3
1
2.615
2.6
2, 3
1
RL = 2 kΩ to 1.35V
VIN(diff) = ±0.5V
V
0.085
0.105
2, 3
1
IO
Output Current
Sourcing, VO = 0V
VIN(diff) = ±0.5V
5
3
5
3
2, 3
1
mA
mA
Sinking, VO = 5V
VIN(diff) = ±0.5V
18
2, 3
1
IS
0.919
1.20
1.50
Supply Current per Channel
2, 3
2.7V AC Parameters
The following conditions apply, unless otherwise specified.
V+ = 2.7V, V - = 0V, VCM = 1.35V, VO = 1.35V, and RL > 1 MΩ.
Typ
(Note 4)
Sub-
groups
Symbol
Parameter
Conditions
Notes
Min
Max
Units
GBW
Gain-Bandwidth Product
Slew Rate
3
4
1
5
MHz
V/μs
Deg
4
SR
θm
Gm
en
Phase Margin
60
Gain Margin
−14
35
dB
Input-Referred Voltage Noise
nV/
enP-P
trec
Input-Referred Voltage Noise
Input Overload Recovery Time
850
50
nVPP
ms
RS = 100Ω, DC to 10 Hz
3
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2.7V DC Parameters – 50 krad(Si) Post Radiation Limits @ +25°C
The following conditions apply, unless otherwise specified.
(Note 5)
V+ = 2.7V, V - = 0V, VCM = 1.35V, VO = 1.35V, and RL > 1 MΩ.
Sub-
groups
Symbol
Parameter
Conditions
Notes
Typ
Min
Max Units
IS
Supply Current per Channel
1.75
mA
1
2.7V Operating Life Test Delta Parameters TA = +25°C
This is worst case drift, deltas are performed at room temperature post operation life. All other parameters, no deltas required.
Symbol
Parameter
Input offset voltage
Conditions
Limit
Units
VIO
2.7 V
±2
μV
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4
5V DC Parameters
The following conditions apply, unless otherwise specified.
V+ = 5V, V- = 0V, V CM = 2.5V, VO = 2.5V and RL > 1MΩ.
Typ
(Note 4)
Sub-
groups
Symbol Parameter
Conditions
Notes
Min
Max Units
VIO
Input Offset Voltage
0.12
0.5
36
μV
60
1
2, 3
1
Offset Calibration Time
10
ms
12
2, 3
TCVIO
Input Offset Voltage
(Temperature Sensitivity)
0.015
µV/°C
IIB
Input Bias Current
−3
6
pA
pA
IIO
Input Offset Current
CMRR
Common Mode Rejection Ratio
130
100
90
1
−0.3 ≤ VCM ≤ 3.2
0 ≤ VCM ≤ 3.2
dB
dB
2, 3
PSRR
AVOL
Power Supply Rejection Ratio
Open Loop Voltage Gain
120
130
95
90
1
2, 3
1
105
100
95
RL = 10 kΩ
RL = 2 kΩ
2, 3
1
dB
132
90
2, 3
1
VO
Output Swing
4.978
0.040
4.92
4.91
RL = 10 kΩ to 2.5V
VIN(diff) = ±0.5V
2, 3
1
V
0.080
0.095
2, 3
1
4.919 4.875
4.855
RL = 2 kΩ to 2.5V
VIN(diff) = ±0.5V
2, 3
1
V
0.091
0.125
0.150
2, 3
1
IO
Output Current
Sourcing, VO = 0V
VIN(diff) = ±0.5V
15
17
8
6
8
6
2, 3
1
mA
Sourcing, VO = 5V
VIN(diff) = ±0.5V
2, 3
1
IS
Supply Current per Channel
0.930
1.20
mA
1.50
2, 3
5
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5V AC Parameters
The following conditions apply, unless otherwise specified.
V+ = 5V, V - = 0V, VCM = 2.5V, VO = 2.5V, and RL > 1 MΩ.
Typ
(Note 4)
Sub-
groups
Symbol
GBW
Parameter
Conditions
Notes
Min
Max
Units
Gain-Bandwidth Product
Slew Rate
3
4
1
5
MHz
V/μs
Deg
4
SR
θm
Gm
en
Phase Margin
60
Gain Margin
−15
35
dB
Input-Referred Voltage Noise
nV/
enP-P
trec
Input-Referred Voltage Noise
Input Overload Recovery Time
850
50
nVPP
ms
RS = 100Ω, DC to 10 Hz
5V DC Parameters – 50 krad(Si) Post Radiation Limits @ +25°C
The following conditions apply, unless otherwise specified.
(Note 5)
V+ = 5V, V - = 0V, VCM = 2.5V, VO = 2.5V, and RL > 1 MΩ.
Sub-
groups
Symbol
Parameter
Conditions
Notes
Typ
Min
Max
Units
IS
Supply Current per Channel
1.75
mA
1
5V Operating Life Test Delta Parameters TA = +25°C
This is worst case drift, deltas are performed at room temperature post operation life. All other parameters, no deltas required.
Symbol
Parameter
Input offset voltage
Conditions
Limit
Units
VIO
5.0 V
±2
μV
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package
junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/
θ
JA or the number given in the Absolute Maximum Ratings, whichever is lower.
Note 3: Human body model, 1.5 kΩ in series with 100 pF.
Note 4: Typical values represent the most likely parametric norm.
Note 5: Pre and post irradiation limits are identical to those listed under DC Parameters, except those listed in the Post Radiation Limit tables.
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6
Application Information
THE BENEFITS OF LMP2012
NO 1/f NOISE
NO EXTERNAL CAPACITORS REQUIRED
The LMP2012 does not need external capacitors. This elimi-
nates the problems caused by capacitor leakage and dielec-
tric absorption, which can cause delays of several seconds
from turn-on until the amplifier's error has settled.
Using patented methods, the LMP2012 eliminates the 1/f
noise present in other amplifiers. That noise, which increases
as frequency decreases, is a major source of measurement
error in all DC-coupled measurements. Low-frequency noise
appears as a constantly-changing signal in series with any
measurement being made. As a result, even when the mea-
surement is made rapidly, this constantly-changing noise sig-
nal will corrupt the result. The value of this noise signal can
be surprisingly large. For example: If a conventional amplifier
MORE BENEFITS
The LMP2012 offers the benefits mentioned above and more.
It has a rail-to-rail output and consumes only 950 µA of supply
current while providing excellent DC and AC electrical per-
formance. In DC performance, the LMP2012 achieves 130 dB
of CMRR, 120 dB of PSRR and 130 dB of open loop gain. In
AC performance, the LMP2012 provides 3 MHz of gain-band-
width product and 4 V/µs of slew rate.
has a flat-band noise level of 10nV/
10 Hz, the RMS noise at 0.001 Hz is 1µV/
and a noise corner of
. This is equiv-
alent to a 0.50 µV peak-to-peak error, in the frequency range
0.001 Hz to 1.0 Hz. In a circuit with a gain of 1000, this pro-
duces a 0.50 mV peak-to-peak output error. This number of
0.001 Hz might appear unreasonably low, but when a data
acquisition system is operating for 17 minutes, it has been on
long enough to include this error. In this same time, the
LMP2012 will only have a 0.21 mV output error. This is smaller
by 2.4 x. Keep in mind that this 1/f error gets even larger at
lower frequencies. At the extreme, many people try to reduce
this error by integrating or taking several samples of the same
signal. This is also doomed to failure because the 1/f nature
of this noise means that taking longer samples just moves the
measurement into lower frequencies where the noise level is
even higher.
HOW THE LMP2012 WORKS
The LMP2012 uses new, patented techniques to achieve the
high DC accuracy traditionally associated with chopper-sta-
bilized amplifiers without the major drawbacks produced by
chopping. The LMP2012 continuously monitors the input off-
set and corrects this error. The conventional chopping pro-
cess produces many mixing products, both sums and
differences, between the chopping frequency and the incom-
ing signal frequency. This mixing causes large amounts of
distortion, particularly when the signal frequency approaches
the chopping frequency. Even without an incoming signal, the
chopper harmonics mix with each other to produce even more
trash. If this sounds unlikely or difficult to understand, look at
the plot (Figure 2), of the output of a typical (MAX432) chop-
per-stabilized op amp. This is the output when there is no
incoming signal, just the amplifier in a gain of -10 with the input
grounded. The chopper is operating at about 150 Hz; the rest
is mixing products. Add an input signal and the noise gets
much worse. Compare this plot with Figure 3 of the LMP2012.
This data was taken under the exact same conditions. The
auto-zero action is visible at about 30 kHz but note the ab-
sence of mixing products at other frequencies. As a result, the
LMP2012 has very low distortion of 0.02% and very low mix-
ing products.
The LMP2012 eliminates this source of error. The noise level
is constant with frequency so that reducing the bandwidth re-
duces the errors caused by noise.
OVERLOAD RECOVERY
The LMP2012 recovers from input overload much faster than
most chopper-stabilized op amps. Recovery from driving the
amplifier to 2X the full scale output, only requires about 40
ms. Many chopper-stabilized amplifiers will take from 250 ms
to several seconds to recover from this same overload. This
is because large capacitors are used to store the unadjusted
offset voltage.
20182216
FIGURE 1.
The wide bandwidth of the LMP2012 enhances performance
when it is used as an amplifier to drive loads that inject tran-
sients back into the output. ADCs (Analog-to-Digital Convert-
ers) and multiplexers are examples of this type of load. To
simulate this type of load, a pulse generator producing a 1V
peak square wave was connected to the output through a 10
pF capacitor. (Figure 1) The typical time for the output to re-
cover to 1% of the applied pulse is 80 ns. To recover to 0.1%
requires 860ns. This rapid recovery is due to the wide band-
width of the output stage and large total GBW.
20182217
FIGURE 2.
7
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PRECISION STRAIN-GAUGE AMPLIFIER
This Strain-Gauge amplifier (Figure 4) provides high gain
(1006 or ~60 dB) with very low offset and drift. Using the re-
sistors' tolerances as shown, the worst case CMRR will be
greater than 108 dB. The CMRR is directly related to the re-
sistor mismatch. The rejection of common-mode error, at the
output, is independent of the differential gain, which is set by
R3. The CMRR is further improved, if the resistor ratio match-
ing is improved, by specifying tighter-tolerance resistors, or
by trimming.
20182204
FIGURE 3.
INPUT CURRENTS
20182218
The LMP2012's input currents are different than standard
bipolar or CMOS input currents in that it appears as a current
flowing in one input and out the other. Under most operating
conditions, these currents are in the picoamp level and will
have little or no effect in most circuits. These currents tend to
increase slightly when the common-mode voltage is near the
minus supply. At high temperatures, the input currents be-
come larger, 0.5 nA typical, and are both positive except when
the VCM is near V−. If operation is expected at low common-
mode voltages and high temperature, do not add resistance
in series with the inputs to balance the impedances. Doing
this can cause an increase in offset voltage. A small resis-
tance such as 1 kΩ can provide some protection against very
large transients or overloads, and will not increase the offset
significantly.
FIGURE 4.
Extending Supply Voltages and Output Swing by Using a
Composite Amplifier Configuration:
In cases where substantially higher output swing is required
with higher supply voltages, arrangements like the ones
shown in Figure 5 and Figure 6 could be used. These config-
urations utilize the excellent DC performance of the LMP2012
while at the same time allow the superior voltage and fre-
quency capabilities of the LM6171 to set the dynamic perfor-
mance of the overall amplifier. For example, it is possible to
achieve ±12V output swing with 300 MHz of overall GBW
(AV = 100) while keeping the worst case output shift due to
VOS less than 4 mV. The LMP2012 output voltage is kept at
about mid-point of its overall supply voltage, and its input
common mode voltage range allows the V- terminal to be
grounded in one case (Figure 5, inverting operation) and tied
to a small non-critical negative bias in another (Figure 6, non-
inverting operation). Higher closed-loop gains are also pos-
sible with a corresponding reduction in realizable bandwidth.
Table 1 shows some other closed loop gain possibilities along
with the measured performance in each case.
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8
20182219
20182220
FIGURE 5.
TABLE 1. Composite Amplifier Measured Performance
FIGURE 6.
It should be kept in mind that in order to minimize the output
noise voltage for a given closed-loop gain setting, one could
minimize the overall bandwidth. As can be seen from Equa-
tion 1 above, the output noise has a square-root relationship
to the Bandwidth.
AV
R1
Ω
200
100
1k
R2
Ω
C2
pF
BW
MHz
SR
(V/μs)
178
174
170
96
en p-p
(mVPP
)
50
100
100
500
1000
10k
10k
100k
100k
100k
8
3.3
2.5
37
In the case of the inverting configuration, it is also possible to
increase the input impedance of the overall amplifier, by rais-
ing the value of R1, without having to increase the feed-back
resistor, R2, to impractical values, by utilizing a "Tee" network
as feedback. See the LMC6442 data sheet (Application Notes
section) for more details on this.
10
70
0.67
1.75
2.2
3.1
70
200
100
1.4
250
400
0.98
64
In terms of the measured output peak-to-peak noise, the fol-
lowing relationship holds between output noise voltage, en p-
p, for different closed-loop gain, AV, settings, where −3 dB
Bandwidth is BW:
20182221
FIGURE 7.
9
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LMP2012 AS ADC INPUT AMPLIFIER
Op amp flatband noise = 8nV/
1/f corner frequency = 100 Hz
AV = 2000
The LMP2012 is a great choice for an amplifier stage imme-
diately before the input of an ADC (Analog-to-Digital Con-
verter), whether AC or DC coupled. See Figure 7 and Figure
8. This is because of the following important characteristics:
Measurement time = 100 sec
Bandwidth = 2 Hz
A) Very low offset voltage and offset voltage drift over time
and temperature allow a high closed-loop gain setting
without introducing any short-term or long-term errors.
For example, when set to a closed-loop gain of 100 as the
analog input amplifier for a 12-bit A/D converter, the over-
all conversion error over full operation temperature and
30 years life of the part (operating at 50°C) would be less
than 5 LSBs.
This example will result in about 2.2 mVPP (1.9 LSB) of
output noise contribution due to the op amp alone, com-
pared to about 594 μVPP (less than 0.5 LSB) when that
op amp is replaced with the LMP2012 which has no 1/f
contribution. If the measurement time is increased from
100 seconds to 1 hour, the improvement realized by using
the LMP2012 would be a factor of about 4.8 times (2.86
mVPP compared to 596 μV when LMP2012 is used) main-
ly because the LMP2012 accuracy is not compromised
by increasing the observation time.
B) Fast large-signal settling time to 0.01% of final value (1.4
μs) allows 12 bit accuracy at 100 KHZ or more sampling
rate.
D) Rail-to-Rail output swing maximizes the ADC dynamic
range in 5-Volt single-supply converter applications. Be-
low are some typical block diagrams showing the
LMP2012 used as an ADC amplifier (Figure 7 and Figure
8).
C) No flicker (1/f) noise means unsurpassed data accuracy
over any measurement period of time, no matter how
long. Consider the following op amp performance, based
on a typical low-noise, high-performance commercially-
available device, for comparison:
20182222
FIGURE 8.
RADIATION ENVIRONMENTS
than 0.082 rad(Si)/s. Wafer level TID data are available with
lot shipments.
Careful consideration should be given to environmental con-
ditions when using a product in a radiation environment.
ELDRS-FREE PRODUCTS
TOTAL IONIZING DOSE
ELDRS-Free products are tested and qualified on a wafer
level basis at a dose rate of 10 mrad(Si)/s per MIL-STD-883G,
Test Method 1019.7, Condition D. Wafer level low dose rate
test data are available with lot shipments.
Radiation hardness assured (RHA) products are those part
numbers with a total ionizing dose (TID) level specified in the
Ordering Information table on the front page. Testing and
qualification of these products is done on a wafer level ac-
cording to MIL-STD-883G, Test Method 1019.7, Condition A
and the “Extended room temperature anneal test” described
in section 3.11 for application environment dose rates less
SINGLE EVENT UPSET
A report on single event upset (SEU) is available upon re-
quest.
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10
Revision History
Date Released
03/19/07
Revision
Section
Changes
A
B
Initial Release
Electrical Section
Initial Release
10/17/08
Added typical parameters to 2.7V and 5V AC
Electrical Sections. Revision A will be Archived.
07/13/09
12/08/09
C
D
E
2.7V DC and 5V DC Electrical Section
Added typical parameter TCVOS to 2.7V DC and 5V
DC Electrical Section. Revision B will be Archived.
Features, Ordering Information and Notes Reference to ELDRS, New ELDRS part number and
added ELDRS Note 6. Revision C will be Archived.
06/08/2010
General Description, 2.7V DC and 5V DC
Electrical Section added New Radiation
Section.
Removed first line. Added Delta Table to Electrical's
to match what is in the SMD and New Radiation
Section. Revision D will be Archived.
11/30/2010
F
AC Electrical 5V parameter table conditions Correct typo to unless otherwise specified
parameters From: V+ = 2.7V, V - = 0V, VCM = 1.35V,
VO = 1.35V, and RL > 1 MΩ. To: V+ = 5V, V - = 0V,
VCM = 2.5V, VO = 2.5V, and RL > 1 MΩ. Revision E
will be Archived.
11
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Physical Dimensions inches (millimeters) unless otherwise noted
10-Pin Ceramic SOIC
NS Package Number WG10A
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12
Notes
13
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