5962L1420901VXC [TI]
具有待机模式和环回功能的耐辐射加固保障 (RHA) 3.3V CAN 收发器 | HKX | 8 | -55 to 125;型号: | 5962L1420901VXC |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有待机模式和环回功能的耐辐射加固保障 (RHA) 3.3V CAN 收发器 | HKX | 8 | -55 to 125 |
文件: | 总32页 (文件大小:928K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SN55HVD233-SP
ZHCSH84A –SEPTEMBER 2017–REVISED DECEMBER 2017
SN55HVD233-SP 3.3V 耐辐射 CAN 收发器
1 特性
3 说明
1
•
符合 MIL-PRF 38535 的 QMLV(QML V 类)耐辐
射 (RHA) SMD 5962L1420901VXC
SN55HVD233-SP 依照 ISO 11898 标准, 用于 使用
控制器区域网络 (CAN) 串行通信物理层的航天器应用
中。作为 CAN 收发器,此器件在差分 CAN 总线和
CAN 控制器间提供传输和接收能力,信令速度高达
1Mbps。
–
单粒子闩锁 (SEL) 在 125°C 下的抗扰度可达
86MeV-cm2/mg
–
电离辐射总剂量 (TID) 在低剂量率下可达
50kRad (Si)
SN55HVD233-SP 专门用于严苛的辐射环境, 具有 交
叉线保护、过压保护、±16V 接地失效保护和过热(热
关断)保护。此器件可在 –7V 至 12V 的宽共模范围内
运行。此收发器是用于卫星应用的微处理器、FPGA
或 ASIC 的主机 CAN 控制器与差分 CAN 总线之间的
接口。
–
–
符合军用温度范围(-55°C 至 125°C)
高性能 8 引脚陶瓷扁平封装 (HKX)
•
•
•
•
•
•
•
符合 ISO 11898-2 标准
总线引脚故障保护大于 ±16V
总线引脚 ESD 保护大于 ±16kV HBM
数据传输速率高达 1Mbps
器件信息(1)
扩展级共模范围:–7V 至 12V
高输入阻抗,允许连接 120 个节点
器件型号
等级
封装
低电压晶体管-晶体管逻辑电路 (LVTTL) I/O 可耐受
5V 电压
QMLV RHA
[50kRad]
8 引线 CFP [HKX]
6.48mm × 6.48mm
5962L1420901VXC
8 引线 CFP [HKX]
6.48mm × 6.48mm
HVD233HKX/EM(2) 工程样片
•
•
•
•
•
•
可调节的驱动器传输次数,用于改善信号质量
未供电节点不会干扰总线
低电流待机模式,200μA 典型值
诊断回送功能
SN55HVD233EVM-
陶瓷评估板
CVAL
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
热关断保护
(2) 这些部件仅适用于工程评估。部件按照不合规的流程进行加工
处理。这些部件不适用于质检、生产、辐射测试或飞行。这些
零部件无法在 –55°C 至 125°C 的完整 MIL 额定温度范围内或
运行寿命中保证其性能。
加电和断电无干扰总线输入和输出
–
–
具有低 VCC 的高输入阻抗
功率循环过程中单片输出
简化原理图
2 应用
VCC
VCC
•
•
航天器背板数据总线通信和控制
VCC
VCC
CANopen、DeviceNet、CAN Kingdom、ISO
D
11783、NMEA 2000、SAE J1939 等 CAN 总线标
准
VCC
RS
SLOPE CONTROL
and MODE
LOGIC
LBK / EN /AB
R
GND
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEI2
SN55HVD233-SP
ZHCSH84A –SEPTEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 (续).............................................................. 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 5
7.5 Driver Electrical Characteristics ................................ 6
7.6 Receiver Electrical Characteristics ........................... 6
7.7 Driver Switching Characteristics ............................... 7
7.8 Receiver Switching Characteristics........................... 8
7.9 Device Switching Characteristics.............................. 8
7.10 Typical Characteristics............................................ 9
Parameter Measurement Information ................ 11
9
Detailed Description ............................................ 15
9.1 Overview ................................................................. 15
9.2 Functional Block Diagram ....................................... 15
9.3 Feature Description................................................. 15
9.4 Device Functional Modes........................................ 19
10 Application and Implementation........................ 20
10.1 Application Information.......................................... 20
10.2 Typical Application ................................................ 22
11 Power Supply Recommendations ..................... 24
12 Layout................................................................... 24
12.1 Layout Guidelines ................................................. 24
12.2 Layout Example .................................................... 26
13 器件和文档支持 ..................................................... 27
13.1 接收文档更新通知 ................................................. 27
13.2 社区资源................................................................ 27
13.3 商标....................................................................... 27
13.4 静电放电警告......................................................... 27
13.5 Glossary................................................................ 27
14 机械、封装和可订购信息....................................... 27
8
4 修订历史记录
Changes from Original (September 2017) to Revision A
Page
•
已更改 将器件状态从高级信息 更改为生产数据...................................................................................................................... 1
2
版权 © 2017, Texas Instruments Incorporated
SN55HVD233-SP
www.ti.com.cn
ZHCSH84A –SEPTEMBER 2017–REVISED DECEMBER 2017
5 说明 (续)
模式:SN55HVD233-SP 的引脚 8 RS 具有三种运行模式:高速、斜率控制或低功耗待机模式。用户可直接将引脚
8 接地以选择高速运行模式,驱动器输出晶体管将尽快开启和关闭,无上升和下降斜率限制。由于斜率与引脚的输
出电流成比例,用户可在引脚 8 连接接地的电阻器以调节上升和下降斜率。斜率控制可通过 0Ω 电阻进行,以实现
约 38V/μs 的转换率;最高可通过 50kΩ电阻进行,从而实现约 4V/μs 的转换率。有关斜率控制的更多信息,请参
阅应用和实现 部分。
如果引脚 8 具有高模式电平,当驱动器关闭且接收器保持工作状态时,SN55HVD233-SP 将进入低电流待机(只
听)模式。当本地协议控制器需要向总线传输时,将会改变此低电流待机模式。有关回送模式的更多信息,请参阅
应用信息 部分。
回送:SN55HVD233-SP 的回送 LBK 引脚 5 逻辑高电平使总线输出和总线输入处于高阻抗状态。其余电路将保持
工作状态,可用于驱动器到接收器的回送和自诊断节点功能,且不会干扰总线。
CAN 总线状态:在器件供电运行期间,CAN 总线具有两种状态:显性和隐性。在总线显性状态下,总线采用差分
驱动方式,D 和 R 引脚相应地置为逻辑低电平。在隐性总线状态下,总线通过接收器的高电阻内部输入电阻器 RIN
偏置为 VCC/2,D 和 R 引脚相应地偏置为逻辑高电平(请参阅总线状态(物理位表示) 和简化的隐性共模偏置和
接收器)。
6 Pin Configuration and Functions
HKX Package
8-Pin CFP
Top View
RS
1
2
3
4
8
7
6
5
D
GND
CANH
CANL
LBK
V
CC
R
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
D
NO.
1
I
CAN transmit data input (LOW for dominant and HIGH for recessive bus states), also called TXD, driver input.
GND
VCC
2
GND Ground connection.
3
Supply Transceiver 3.3-V supply voltage.
CAN receive data output (LOW for dominant and HIGH for recessive bus states), also called RXD, receiver
output.
R
4
O
LBK
5
6
7
I
Loopback mode input pin.
Low-level CAN bus line.
High-level CAN bus line.
CANL
CANH
I/O
I/O
Mode select pin:
Tie to GND = high-speed mode,
Strong pullup to VCC = low power mode,
0-Ω to 50-kΩ pulldown to GND = slope control mode.
RS
8
I
Copyright © 2017, Texas Instruments Incorporated
3
SN55HVD233-SP
ZHCSH84A –SEPTEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature unless otherwise noted(1)(2)
MIN
–0.3
–16
MAX
UNIT
V
VCC Supply voltage
7
16
100
7
Voltage at any bus pin (CANH or CANL)
V
Voltage input, transient pulse, CANH and CANL, through 100 Ω (see Figure 18)
–100
–0.5
–0.5
–10
V
VI
Input voltage, (D, RS, LBK)
Output voltage, (R)
V
VO
IO
7
V
Receiver output current
Operating junction temperature
Storage temperature
10
150
150
mA
°C
°C
TJ
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground pin.
7.2 ESD Ratings
VALUE
±14000
±4000
±500
UNIT
CANH, CANL, and GND
Other pins
Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
NOM
MAX UNIT
VCC
Supply voltage
3
3.6
12
5.5
0.8
6
V
V
Voltage at any bus pin (separately or common mode)
–7
VIH
VIL
VID
High-level input voltage
Low-level input voltage
Differential input voltage
D, LBK
D, LBK
2
V
0
–6
V
V
Resistance from RS to ground for slope control
VI(RS) Input voltage at RS for standby
0
50
5.5
kΩ
V
0.75 VCC
–50
Driver
IOH
High-level output current
mA
Receiver
Driver
–10
50
10
IOL
TJ
Low-level output current
mA
°C
Receiver
Operating junction temperature(1)
–55
125
(1) Maximum junction temperature operation is allowed as long as the device maximum junction temperature is not exceeded.
4
Copyright © 2017, Texas Instruments Incorporated
SN55HVD233-SP
www.ti.com.cn
ZHCSH84A –SEPTEMBER 2017–REVISED DECEMBER 2017
7.4 Thermal Information
SN55HVD233-SP
THERMAL METRIC(1)(2)
HKX (CFP)
8 PINS
97.1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
21.5
79.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
13.7
ψJB
73.6
RθJC(bot)
7.0
(1) All values except RθJC were taken on a JEDEC-51 standard High-K PCB using a nominal lead form. Differences in lead form,
component density, or PCB design can affect these values.
(2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2017, Texas Instruments Incorporated
5
SN55HVD233-SP
ZHCSH84A –SEPTEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
7.5 Driver Electrical Characteristics
The specifications shown below are valid across temperature range of –55°C to 125°C pre-radiation and 25°C post-radiation.
When different, the post-radiation values are shown in a separate row specified by the corresponding RHA level (L = 50
krad).
PARAMETER
TEST CONDITIONS
SUBGROUP(1)
MIN TYP(2) MAX UNIT
Bus output
voltage
(dominant)
CANH
CANL
CANH
CANL
[1, 2, 3]
2.4
0.5
VCC
V(D) = 0 V, V(RS) = 0 V, see Figure 12 and
Figure 13
VO(D)
V
V
[1, 2, 3]
1.25
Bus output
voltage
(recessive)
2.3
2.3
2
V(D) = 3 V, V(RS) = 0 V, see Figure 12 and
Figure 13
VO
1.5
1.4
3
3
V(D) = 0 V, V(RS) = 0 V, see Figure 12 and
Figure 13
[1, 2, 3]
[1, 2, 3]
Differential output voltage
(dominant)
L
VOD(D)
V
V(D) = 0 V, V(RS) = 0 V, see Figure 13 and
Figure 14
1.2
2
V(D) = 3 V, V(RS) = 0 V, see Figure 12 and
Figure 13
[1, 2, 3]
[1, 2, 3]
–120
–0.5
12 mV
Differential output voltage
(recessive)
VOD
V(D) = 3 V, V(RS) = 0 V, no load
0.05
V
V
Peak-to-peak common-
mode output voltage
VOC(pp)
IIH
See Figure 20
1
High-level
D, LBK
V(D) = 2 V
[1, 2, 3]
[1, 2, 3]
–30
30
30
μA
μA
input current
Low-level input
D, LBK
IIL
V(D) = 0.8 V
–30
current
V(CANH) = –7 V, CANL open, see Figure 23
V(CANH) = 12 V, CANL open, see Figure 23
V(CANL) = –7 V, CANH open, see Figure 23
V(CANL) = 12 V, CANH open, see Figure 23
See receiver input capacitance
[1, 2, 3]
[1, 2, 3]
[1, 2, 3]
[1, 2, 3]
–250
1
IOS
Short-circuit output current
Output capacitance
mA
–1
250
CO
RS input current for
standby
IIRS(s)
V(RS) = 0.75 VCC
[1, 2, 3]
–10
μA
μA
Standby
V(RS) = VCC, V(D) = VCC, V(LBK) = 0 V
[1, 2, 3]
[1, 2, 3]
[1, 2, 3]
200 600
ICC
Supply current Dominant V(D) = 0 V, no load, V(LBK) = 0 V, RS = 0 V
Recessive V(D) = VCC, no load, V(LBK) = 0 V, V(RS) = 0 V
6
6
mA
(1) For subgroup definitions, please see Table 1.
(2) All typical values are at 25°C and with a 3.3-V supply.
7.6 Receiver Electrical Characteristics
The specifications shown below are valid across temperature range of –55°C to 125°C pre-radiation and 25°C post-radiation.
When different, the post-radiation values are shown in a separate row specified by the corresponding RHA level (L = 50
krad).
PARAMETER
TEST CONDITIONS
SUBGROUP(1)
MIN TYP(2) MAX UNIT
Positive-going input threshold
voltage
VIT+
VIT–
Vhys
[1, 2, 3]
750 900
650
mV
mV
mV
Negative-going input threshold
voltage
V(LBK) = 0 V, see Table 2
[1, 2, 3]
500
2.4
Hysteresis voltage (VIT+
VIT–
–
100
)
VOH High-level output voltage
VOL Low-level output voltage
IO = –4 mA, see Figure 17
IO = 4 mA, see Figure 17
[1, 2, 3]
[1, 2, 3]
V
V
0.4
(1) For subgroup definitions, please see Table 1.
(2) All typical values are at 25°C and with a 3.3-V supply.
6
Copyright © 2017, Texas Instruments Incorporated
SN55HVD233-SP
www.ti.com.cn
ZHCSH84A –SEPTEMBER 2017–REVISED DECEMBER 2017
Receiver Electrical Characteristics (continued)
The specifications shown below are valid across temperature range of –55°C to 125°C pre-radiation and 25°C post-radiation.
When different, the post-radiation values are shown in a separate row specified by the corresponding RHA level (L = 50
krad).
PARAMETER
TEST CONDITIONS
V(CANH) or V(CANL) = 12 V
SUBGROUP(1)
MIN TYP(2) MAX UNIT
[1, 2, 3]
150
500
V(CANH) or V(CANL) = 12 V,
VCC = 0 V
Other bus pin = 0 V,
V(D) = 3 V,
V(LBK) = 0 V,
V(RS) = 0 V
[1, 2, 3]
[1, 2, 3]
[1, 2, 3]
150
600
II
Bus input current
μA
CANH or CANL = –7 V
–610
–450
–100
–100
CANH or CANL = –7 V,
VCC = 0 V
Input capacitance (CANH or
CANL)
Pin-to-ground, VI = 0.4 sin(4E6πt) + 0.5 V,
V(D) = 3 V, V(LBK) = 0 V
CI
40
20
pF
Pin-to-pin, VI = 0.4 sin(4E6πt) + 0.5 V,
V(D) = 3 V, V(LBK) = 0 V
CID
RID
RIN
Differential input capacitance
Differential input resistance
pF
kΩ
kΩ
[4, 5, 6]
[4, 5, 6]
40
20
105
55
V(D) = 3 V, V(LBK) = 0 V
Input resistance (CANH or
CANL)
Standby
V(RS) = VCC, V(D) = VCC, V(LBK) = 0 V
[1, 2, 3]
[1, 2, 3]
[1, 2, 3]
200 600
μA
mA
mA
Supply
current
ICC
Dominant
V(D) = 0 V, no load, V(RS) = 0 V, V(LBK) = 0 V
V(D) = VCC, no load, V(RS) = 0 V, V(LBK) = 0 V
6
6
Recessive
7.7 Driver Switching Characteristics
The specifications shown below are valid across temperature range of –55°C to 125°C pre-radiation and 25°C post-radiation.
When different, the post-radiation values are shown in a separate row specified by the corresponding RHA level (L = 50
krad).
PARAMETER
TEST CONDITIONS
V(RS) = 0 V, see Figure 15
SUBGROUP(1)
[9, 10, 11]
[9, 10, 11]
[9, 10, 11]
[9, 10, 11]
[9, 10, 11]
[9, 10, 11]
MIN TYP(2) MAX UNIT
35 85
Propagation delay time,
low-to-high-level output
tPLH
tPHL
tsk(p)
RS with 10 kΩ to ground, see Figure 15
RS with 50 kΩ to ground, see Figure 15
V(RS) = 0 V, see Figure 15
70 125
500 870
70 120
130 180
870 1200
35
ns
ns
ns
Propagation delay time,
high-to-low-level output
RS with 10 kΩ to ground, see Figure 15
RS with 50 kΩ to ground, see Figure 15
V(RS) = 0 V, see Figure 15
Pulse skew (|tPHL – tPLH|)
RS with 10 kΩ to ground, see Figure 15
RS with 50 kΩ to ground, see Figure 15
60
370
tr
tf
tr
tf
tr
tf
Differential output signal rise time
Differential output signal fall time
Differential output signal rise time
Differential output signal fall time
Differential output signal rise time
Differential output signal fall time
[9, 10, 11]
[9, 10, 11]
[9, 10, 11]
[9, 10, 11]
[9, 10, 11]
[9, 10, 11]
20
20
70
ns
ns
ns
ns
ns
ns
V(RS) = 0 V, see Figure 15
70
30
135
RS with 10 kΩ to ground, see Figure 15
30
135
350
350
1400
RS with 50 kΩ to ground, see Figure 15
1400
Enable time from standby to
dominant
ten(s)
See Figure 19
[9, 10, 11]
0.6
1.5
μs
(1) For subgroup definitions, please see Table 1.
(2) All typical values are at 25°C and with a 3.3-V supply.
Copyright © 2017, Texas Instruments Incorporated
7
SN55HVD233-SP
ZHCSH84A –SEPTEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
7.8 Receiver Switching Characteristics
The specifications shown below are valid across temperature range of –55°C to 125°C pre-radiation and 25°C post-radiation.
When different, the post-radiation values are shown in a separate row specified by the corresponding RHA level (L = 50
krad).
PARAMETER
TEST CONDITIONS
SUBGROUP(1)
MIN TYP(2) MAX UNIT
Propagation delay time, low-to-high-level
output
tPLH
tPHL
[9, 10, 11]
35
35
105 ns
105 ns
Propagation delay time, high-to-low-level
output
[9, 10, 11]
See Figure 17
tsk(p) Pulse skew (|tPHL – tPLH|)
7
2
2
ns
ns
ns
tr
tf
Output signal rise time
Output signal fall time
(1) For subgroup definitions, please see Table 1.
(2) All typical values are at 25°C and with a 3.3-V supply.
7.9 Device Switching Characteristics
The specifications shown below are valid across temperature range of –55°C to 125°C pre-radiation and 25°C post-radiation.
When different, the post-radiation values are shown in a separate row specified by the corresponding RHA level (L = 50
krad).
PARAMETER
TEST CONDITIONS
See Figure 22
SUBGROUP(1)
MIN TYP(2) MAX UNIT
Loopback delay, driver input to
receiver output
t(LBK)
7.5
ns
V(RS) at 0 V, see Figure 21
[9, 10, 11]
[9, 10, 11]
70 150
105 225
V(RS) with 10 kΩ to ground, see
Figure 21
Total loop delay, driver input to
receiver output, recessive to dominant
t(loop1)
ns
V(RS) with 50 kΩ to ground, see
Figure 21
[9, 10, 11]
[9, 10, 11]
[9, 10, 11]
500 600
70 150
105 225
V(RS) at 0 V, See Figure 21
V(RS) with 10 kΩ to ground, see
Figure 21
Total loop delay, driver input to
receiver output, dominant to recessive
t(loop2)
ns
V(RS) with 50 kΩ to ground, see
Figure 21
[9, 10, 11]
500 600
(1) For subgroup definitions, please see Table 1.
(2) All typical values are at 25°C and with a 3.3-V supply.
Table 1. Quality Conformance Inspection(1)
SUBGROUP
DESCRIPTION
Static tests at
TEMPERATURE (°C)
1
2
25
125
–55
25
Static tests at
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
5
125
–55
25
6
7
8A
8B
9
125
–55
25
10
11
125
–55
(1) MIL-STD-883, Method 5005 - Group A
8
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ZHCSH84A –SEPTEMBER 2017–REVISED DECEMBER 2017
7.10 Typical Characteristics
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D005
D002
V(RS), V(LBK) = 0 V
V(RS), V(LBK) = 0 V
Figure 1. Recessive-To-Dominant Loop Time vs
Temperature
Figure 2. Dominant-To-Recessive Loop Time vs
Temperature
20
19
18
17
16
15
160
140
120
100
80
60
40
20
0
200
400
600
800
1000
0
1
2
3
4
Frequency (kbps)
V(RS), V(LBK) = 0 V
Low-Level Output Voltage (V)
C003
C004
VCC = 3.3 V
TA = 25°C
VCC = 3.3 V
V(RS), V(LBK) = 0 V
TA = 25°C
60-Ω load
Figure 3. Supply Current vs Frequency
Figure 4. Driver Low-Level Output Current vs
Low-Level Output Voltage
2.2
2
0.12
0.10
0.08
0.06
0.04
0.02
0.00
1.8
1.6
1.4
1.2
1
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
High-Level Output Voltage (V)
C005
D001
VCC = 3.3 V
V(RS), V(LBK) = 0 V
TA = 25°C
RL = 60 Ω
V(RS), V(LBK) = 0 V
Figure 5. Driver High-Level Output Current vs
High-Level Output Voltage
Figure 6. Differential Output Voltage vs
Temperature
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Typical Characteristics (continued)
55
48
47
46
45
44
43
42
41
40
39
38
37
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
Temperature (èC)
D007
D006
V(RS), V(LBK) = 0 V
See Figure 17
V(RS), V(LBK) = 0 V
See Figure 17
Figure 7. Receiver Low-To-High Propagation Delay vs
Temperature
Figure 8. Receiver High-To-Low Propagation Delay vs
Temperature
60
55
50
45
40
35
30
25
55
50
45
40
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Temperature (èC)
D003
D004
V(RS), V(LBK) = 0 V
See Figure 15
V(RS), V(LBK) = 0 V
See Figure 15
Figure 10. Driver High-To-Low Propagation Delay vs
Temperature
Figure 9. Driver Low-To-High Propagation Delay vs
Temperature
35
30
25
20
15
10
5
0
œ5
0.0
0.6
1.2
1.8
2.4
3.0
3.6
Supply Voltage (V)
C011
V(RS), V(LBK) = 0 V
RL = 60 Ω
TA = 25°C
Figure 11. Driver Output Current vs Supply Voltage
10
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8 Parameter Measurement Information
I
O(CANH)
D
I
I
60 Ω ±1%
V
OD
V
O(CANH)
V
+ V
O(CANH)
O(CANL)
I
R
S
IRs
2
V
I
V
OC
I
O(CANL)
+
V
I(Rs)
V
O(CANL)
-
Figure 12. Driver Voltage, Current, and Test Definition
Dominant
≈ 3 V
V
O(CANH)
Recessive
≈ 2.3 V
≈ 1 V
V
O(CANL)
Figure 13. Bus Logic State Voltage Definitions
330 Ω ±1%
CANH
D
V
OD
V
I
60 Ω ±1%
+
-7 V ≤ V ≤ 12 V
TEST
R
S
_
CANL
330 Ω ±1%
Figure 14. Driver VOD
CANH
CANL
V
CC
V
/2
CC
V /2
CC
C
= 50 pF ±20%
(see Note B)
L
V
I
0 V
V
D
V
O
t
t
PHL
PLH
R
L
= 60 Ω ±1%
V
I
R
S
O(D)
+
90%
10%
0.9 V
V
O
V
0.5 V
I(Rs)
(see Note A)
V
O(R)
-
t
r
t
f
A. The input pulse is supplied by a generator having the following characteristics:
•
•
•
•
Pulse repetition rate (PRR) ≤125 kHz, 50% duty cycle
tr ≤ 6 ns
tf ≤ 6 ns
ZO = 50 Ω
B. CL includes fixture and instrumentation capacitance.
Figure 15. Driver Test Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
CANH
R
I
O
V
V
ID
I(CANH)
V
+ V
I(CANH
I(CANL)
V
IC
=
2
V
O
CANL
V
I(CANL)
Figure 16. Receiver Voltage and Current Definitions
2.9 V
1.5 V
CANH
CANL
2.2 V
2.2 V
V
I
R
I
O
V
I
t
t
PHL
PLH
C
L
= 15 pF ±20%
1.5 V
V
V
OH
V
O
(see Note A)
(see Note B)
90%
90%
50%
10%
50%
10%
V
O
OL
t
r
t
f
A. The input pulse is supplied by a generator having the following characteristics:
•
•
•
•
PRR ≤125 kHz, 50% duty cycle
tr ≤ 6 ns
tf ≤ 6 ns
ZO = 50 Ω
B. CL includes fixture and instrumentation capacitance.
Figure 17. Receiver Test Circuit and Voltage Waveforms
Table 2. Differential Input Voltage Threshold Test
INPUT
OUTPUT
R
MEASURED
|VID
VCANH
–6.1 V
12 V
VCANL
–7 V
|
L
L
900 mV
900 mV
6 V
11.1 V
–7 V
VOL
–1 V
L
12 V
6 V
L
6 V
–6.5 V
12 V
–7 V
H
H
H
H
H
500 mV
500 mV
6 V
11.5 V
–1 V
–7 V
VOH
6 V
12 V
6 V
Open
Open
X
CANH
CANL
R
100 Ω
Pulse Generator
15 µs Duration
1% Duty Cycle
D at 0 V or V
CC
Rs, LBK, at 0 V or V
CC
t , t ≤ 100 ns
r f
NOTE: This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 18. Test Circuit, Transient Overvoltage Test
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HVD233
R
S
CANH
V
I
D
60 Ω 1%
0 V
LBK
CANL
R
V
O
+
-
15 pF 20%
V
CC
50%
V
I
0 V
V
V
OH
50%
V
O
OL
t
en(s)
Copyright © 2017, Texas Instruments Incorporated
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
•
•
tr or tf ≤ 6 ns
PRR = 125 kHz, 50% duty cycle
Figure 19. Ten(s) Test Circuit and Voltage Waveforms
27 Ω ±±1
27 Ω ±±1
CANH
CANL
V
OC(PP)
D
V
OC
V
I
R
S
V
OC
50 pF ±201
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
•
•
tr or tf ≤ 6 ns
PRR = 125 kHz, 50% duty cycle
Figure 20. VOC(pp) Test Circuit and Voltage Waveforms
0Ω, 10 kΩ,
or 100 kΩ 5%
DUT
R
S
CANH
V
CC
50%
50%
D
V
I
60 Ω 1%
V
I
0 V
LBK
t
t
(loop1)
(loop2)
CANL
V
OH
OL
V
50%
50%
V
O
CC
V
R
+
-
V
O
15 pF 20%
Figure 21. T(loop) Test Circuit and Voltage Waveforms
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HVD233
V
R
CC
S
CANH
50%
50%
V
I
+
D
0 V
V
I
V
OD
60 W 1%
-
t
t
(LBK2)
(LBK1)
V
LBK
R
OH
V
CC
CANL
50%
= t
50%
V
O
V
OL
t
= t
(LBK2)
(LBK)
(LBK1)
V
OD
≈ 2.3 V
+
V
O
15 pF 20%
-
Copyright © 2017, Texas Instruments Incorporated
Figure 22. T(LBK) Test Circuit and Voltage Waveforms
I
OS
I
OS
15 s
CANH
D
0 V
0 V or V
CC
+
I
OS
V
I
12 V
_
CANL
V
I
0 V
0 V
and
10 µs
V
I
-7 V
Figure 23. IOS Test Circuit and Waveforms
3.3 V
T
A
= 25°C
V
= 3.3 V
CC
R2 ± 1%
R1 ± 1%
R1 ± 1%
CANH
CANL
+
ID
-
R
V
V
ac
V
I
R2 ± 1%
The R Output State Does Not Change During
Application of the Input Waveform.
V
ID
R1
R2
500 mV
900 mV
50 Ω
50 Ω
280 Ω
130 Ω
12 V
V
I
-7 V
NOTE: All input pulses are supplied by a generator with ƒ ≤ 1.5 MHz.
Figure 24. Common-Mode Voltage Rejection
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9 Detailed Description
9.1 Overview
The SN55HVD233-SP is used in applications employing the CAN serial communication physical layer in
accordance with the ISO 11898 standard. As a CAN transceiver, the device provides transmit and receive
capability between the differential CAN bus and a CAN controller, with signaling rates up to 1 Mbps.
Designed for operation in especially harsh environments, the SN55HVD233-SP features cross-wire, overvoltage,
and loss of ground protection to ±16 V, overtemperature (thermal shutdown) protection, and common-mode
transient protection of ±100 V. This device operates over a wide –7-V to 12-V common mode range. This
transceiver is the interface between the host CAN controller on the microprocessor, FPGA, or ASIC, and the
differential CAN bus used in satellite applications.
9.2 Functional Block Diagram
8
ws
7
/!bI
1
5
6
/!b[
4
w
ꢀ
[.Y
Copyright © 2017, Texas Instruments Incorporated
9.3 Feature Description
9.3.1 Modes
The RS, pin 8 of the SN55HVD233-SP, provides for three modes of operation: high-speed, slope control, or low-
power standby mode. The user selects the high-speed mode of operation by connecting pin 8 directly to ground,
allowing the driver output transistors to switch on and off as fast as possible with no limitation on the rise and fall
slope. The user can adjust the rise and fall slope by connecting a resistor to ground at pin 8, because the slope
is proportional to the pin's output current. Slope control is implemented with a resistor values of 0 Ω to achieve a
single ended slew rate of approximately 38 V/μs up to a value of 50 kΩ to achieve approximately 4 V/μs slew
rate. For more information about slope control, refer to Application and Implementation.
The SN55HVD233-SP enters a low-current standby (listen-only) mode during which the driver is switched off and
the receiver remains active if a high logic level is applied to pin 8. The local protocol controller reverses this low-
current standby mode when it needs to transmit to the bus.
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Feature Description (continued)
9.3.2 Loopback
A logic high on the loopback LBK pin 5 of the SN55HVD233-SP places the bus output and bus input in a high-
impedance state. The remaining circuit remains active and available for driver-to-receiver loopback, self-
diagnostic node functions without disturbing the bus. For more information on the loopback mode, refer to the
Application Information.
16
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Feature Description (continued)
9.3.3 CAN Bus States
The CAN bus has two states during powered operation of the device: dominant and recessive. A dominant bus
state is when the bus is driven differentially, corresponding to a logic low on the D and R pin. A recessive bus
state is when the bus is biased to VCC / 2 through the high-resistance internal input resistors RIN of the receiver,
corresponding to a logic high on the D and R pins (see Figure 25 and Figure 26).
/!bI
Vdiff(D)
Vdiff(R)
/!b[
Çime, t
wecessive
[ogic I
5ominant
[ogic [
wecessive
[ogic I
Figure 25. Bus States (Physical Bit Representation)
/!bI
wó5
VCC/2
/!b[
Figure 26. Simplified Recessive Common Mode Bias and Receiver
9.3.4 ISO 11898 Compliance of SN55HVD233-SP
9.3.4.1 Introduction
Many users value the low-power consumption of operating their CAN transceivers from a 3.3-V supply. However,
some users are concerned about the interoperability with 5-V supplied transceivers on the same bus. This report
analyzes this situation to address those concerns.
9.3.4.2 Differential Signal
CAN is a differential bus where complementary signals are sent over two wires and the voltage difference
between the two wires defines the logical state of the bus. The differential CAN receiver monitors this voltage
difference and outputs the bus state with a single-ended output signal.
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Feature Description (continued)
NOISE MARGIN
900 mV Threshold
500 mV Threshold
RECEIVER DETECTION WINDOW
75% SAMPLE POINT
NOISE MARGIN
Figure 27. Typical SN55HVD233-SP Differential Output Voltage Waveform
The CAN driver creates the difference in voltage between CANH and CANL in the dominant state. The dominant
differential output of the SN55HVD233-SP is greater than 1.5 V and less than 3 V across a 60-Ω load. The
minimum required by ISO 11898 is 1.5 V and maximum is 3 V. These are the same limiting values for 5-V
supplied CAN transceivers. The bus termination resistors drive the recessive bus state and not the CAN driver.
A CAN receiver is required to output a recessive state with less than 500 mV and a dominant state with more
than 900 mV difference voltage on its bus inputs. The CAN receiver must do this with common-mode input
voltages from –2 V to 7 V. The SN55HVD233-SP receiver meets these same input specifications as 5-V supplied
receivers.
9.3.4.2.1 Common-Mode Signal
A common-mode signal is an average voltage of the two signal wires that the differential receiver rejects. The
common-mode signal comes from the CAN driver, ground noise, and coupled bus noise. The supply voltage of
the CAN transceiver has nothing to do with noise. The SN55HVD233-SP driver lowers the common-mode output
in a dominant bit by a couple hundred millivolts from that of most 5-V drivers. While this does not fully comply
with ISO 11898, this small variation in the driver common-mode output is rejected by differential receivers and
does not effect data, signal noise margins, or error rates.
9.3.4.3 Interoperability of 3.3-V CAN in 5-V CAN Systems
The 3.3-V supplied CAN transceivers are electrically interchangeable with 5-V CAN transceivers. The differential
output is the same. The recessive common mode output is the same. The dominant common mode output
voltage is a couple hundred millivolts lower than 5 V supplied drivers, while the receivers exhibit identical
specifications as 5-V devices.
To help ensure the widest interoperability possible, the SN55HVD233-SP successfully passed the internationally
recognized GIFT ICT conformance and interoperability testing for CAN transceivers. Electrical interoperability
does not always assure interchangeability, however. Most implementers of CAN buses recognize that ISO 11898
does not sufficiently specify the electrical layer and that strict standard compliance alone does not ensure full
interchangeability. Interchangeability is ensured with thorough equipment testing.
18
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Feature Description (continued)
9.3.5 Thermal Shutdown
If the junction temperature of the device exceeds the thermal shutdown threshold, the device turns off the CAN
driver circuits thus blocking the D pin to bus transmission path. The shutdown condition is cleared when the
junction temperature drops below the thermal shutdown temperature of the device. The CAN bus pins are high-
impedance biased to recessive level during a thermal shutdown, and the receiver-to-R pin path remains
operational.
9.4 Device Functional Modes
Table 3. Driver I/O
DRIVER(1)
INPUTS
OUTPUTS
D
LBK
RS
CANH
CANL
BUS STATE
Recessive
Dominant
X
X
> 0.75 VCC
Z
H
Z
Z
Z
L
Z
Z
L
H or open
X
L or open
≤ 0.33 VCC
≤ 0.33 VCC
X
H
Recessive
Recessive
(1) H = High level; L = Low level; Z = High impedance; X = Irrelevant
Table 4. Receiver I/O
RECEIVER(1)
INPUTS
OUTPUT
BUS STATE
Dominant
Recessive
?
VID = V(CANH) – V(CANL)
ID ≥ 0.9 V
ID ≤ 0.5 V or open
0.5 V < VID < 0.9 V
ID ≥ 0.9 V
D
R
L
V
X
V
H or open
H
?
H or open
Dominant
Recessive
Recessive
?
V
X
H
L
L
V
ID ≤ 0.5 V or open
ID ≤ 0.5 V or open
H
L
V
0.5 V < VID < 0.9 V
L
L
(1) H = High level; L = Low level; Z = High impedance; X = Irrelevant; ? = Indeterminate
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Diagnostic Loopback
The diagnostic loopback or internal loopback function of the SN55HVD233-SP is enabled with a high-level input
on pin 7, LBK. This mode disables the driver output while keeping the bus pins biased to the recessive state.
This mode also redirects the D data input (transmit data) through logic to the received data output (R), thus
creating an internal loopback of the transmit-to-receive data path. This mimics the loopback that occurs normally
with a CAN transceiver because the receiver loops back the driven output to the R (receive data) pin. This mode
allows the host microprocessor to input and read back a bit sequence or CAN messages to perform diagnostic
routines without disturbing the CAN bus. Figure 33 shows a typical CAN bus application.
If the LBK pin is not used, it may be tied to ground (GND). However, it is pulled low internally (defaults to a low-
level input) and may be left open if not in use.
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Application Information (continued)
RS INPUT
V
D INPUT
CANH INPUT
V
CC
CC
V
CC
110 kW
45 kW
9 kW
100 kW
1 kW
INPUT
INPUT
9 V
9 kW
40 V
+
_
INPUT
CANL INPUT
CANH AND CANL OUTPUTS
R OUTPUT
V
CC
V
CC
V
CC
110 kW
45 kW
9 kW
5 W
OUTPUT
9 V
INPUT
40 V
OUTPUT
40 V
9 kW
LBK INPUT
V
CC
1 kW
INPUT
100 kW
9 V
Copyright © 2017, Texas Instruments Incorporated
Figure 28. Equivalent Input and Output Schematic Diagrams
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10.2 Typical Application
Bus Lines -- 40 m max
CANH
Stub Lines -- 0.3 m max
120
W
120 W
CANL
3.3 V
Vcc
3.3 V
Vcc
3.3 V
Rs
Rs
Vcc
Rs
0.1
0.1 mF
SN55HVD233-SP
SN55HVD233-SP
SN55HVD233-SP
0.1
m
mF
F
GND
GND
GND
D
R
D
R
D
R
LBK
LBK
LBK
CANTX
CANRX
CANTX
CANRX
GPIO
CANTX
CANRX
GPIO
GPIO
FPGA/MCU
FPGA/MCU
FPGA/MCU
Sensor, Actuator, or Control
Equipment
Sensor, Actuator, or Control
Equipment
Sensor, Actuator, or Control
Equipment
Copyright © 2017, Texas Instruments Incorporated
Figure 29. Typical Application Schematic
10.2.1 Design Requirements
The High-Speed ISO 11898 Standard specifications are given for a maximum signaling rate of 1 Mbps with a bus
length of 40 m and a maximum of 30 nodes. It also recommends a maximum unterminated stub length of 0.3 m.
The cable is specified to be a shielded or unshielded twisted-pair with a 120-Ω characteristic impedance (ZO).
The standard defines a single line of twisted-pair cable with the network topology as shown in Figure 29. It is
terminated at both ends with 120-Ω resistors, which match the characteristic impedance of the line to prevent
signal reflections. According to ISO 11898, placing RL on a node should be avoided because the bus lines lose
termination if the node is disconnected from the bus.
10.2.2 Detailed Design Procedure
Table 5. Suggested Cable Length vs Signaling Rate
BUS LENGTH (m)
SIGNALING RATE (Mbps)
40
100
200
500
1000
1
0.5
0.25
0.1
0.05
Basically, the maximum bus length is determined by, or rather is a trade-off with the selected signaling rate as
listed in Table 5.
A signaling rate decreases as transmission distance increases. While steady-state losses may become a factor
at the longest transmission distances, the major factors limiting signaling rate as distance is increased are time
varying. Cable bandwidth limitations, which degrade the signal transition time and introduce inter-symbol
interference (ISI), are primary factors reducing the achievable signaling rate when transmission distance is
increased.
For a CAN bus, the signaling rate is also determined from the total system delay – down and back between the
two most distant nodes of a system and the sum of the delays into and out of the nodes on a bus with the typical
5 ns/m prop delay of a twisted-pair cable. Also, consideration must be given the signal amplitude loss due to
resistance of the cable and the input resistance of the transceivers. Under strict analysis, skin effects, proximity
to other circuitry, dielectric loss, and radiation loss effects all act to influence the primary line parameters and
degrade the signal.
A conservative rule of thumb for bus lengths over 100 m is derived from the product of the signaling rate in Mbps
and the bus length in meters, which should be less than or equal to 50.
22
Copyright © 2017, Texas Instruments Incorporated
SN55HVD233-SP
www.ti.com.cn
ZHCSH84A –SEPTEMBER 2017–REVISED DECEMBER 2017
Signaling Rate (Mbps) × Bus Length (m) ≤ 50. Operation at extreme temperatures should employ additional
conservatism.
10.2.2.1 Slope Control
Adjust the rise and fall slope of the SN55HVD233-SP driver output by connecting a resistor from the RS (pin 8)
to ground (GND), or to a low-level input voltage as shown in Figure 30.
The slope of the driver output signal is proportional to the pin's output current. This slope control is implemented
with an external resistor value ranging from 0 Ω to achieve a ≈38 V/μs single ended slew rate, and up to 50 kΩ to
achieve a ≈4 V/μs slew rate as displayed in Figure 31. Figure 32 shows typical driver output waveforms with
slope control.
0 kΩ to
50 kΩ
GPIO
RS
1
2
3
4
5
10
9
D
GND
VCC
R
CANH
CANL
LBK
MCU/DSP
8
7
6
N/C
N/C
Figure 30. Slope Control/Standby Connection to a DSP
10.2.2.2 Standby
If a high-level input (> 0.75 VCC) is applied to RS (pin 8), the circuit enters a low-current, listen-only standby
mode during which the driver is switched off and the receiver remains active. The local controller can reverse this
low-power standby mode when the rising edge of a dominant state (bus differential voltage > 900-mV typical)
occurs on the bus.
10.2.3 Application Curves
40
35
30
25
20
15
10
5
0
0
10000
20000
30000
40000
50000
60000
Slope Control Resistance (kW)
D008
Figure 31. HVD233 Driver Output Signal Slope vs Slope
Control Resistance Value
Figure 32. Typical SN55HVD233-SP 250-Kbps Output Pulse
Waveforms With Slope Control
Copyright © 2017, Texas Instruments Incorporated
23
SN55HVD233-SP
ZHCSH84A –SEPTEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
11 Power Supply Recommendations
TI recommends to have localized capacitive decoupling near device VCC pin to GND. Values of 4.7 µF at VCC
pin and 10 µF, 1 µF, and 0.1 µF at supply have tested well on evaluation modules.
12 Layout
12.1 Layout Guidelines
Minimize stub length from node insertion to bus.
12.1.1 Bus Loading, Length, and Number of Nodes
The ISO11898 standard specifies up to 1-Mbps data rate, maximum bus length of 40 m, maximum drop line
(stub) length of 0.3 m, and a maximum of 30 nodes. However, with careful network design, the system may have
longer cables, longer stub lengths, and many more nodes to a bus. Many CAN organizations and standards have
scaled the use of CAN for applications outside the original ISO11898 standard. They made system level trade-
offs for data rate, cable length, and parasitic loading of the bus. Examples of some of these specifications are
ARINC825, CANopen, CAN Kingdom, DeviceNet, and NMEA200.
A high number of nodes requires a transceiver with high input impedance and wide common mode range such
as the SN55HVD233-SP CAN. ISO11898-2 specifies the driver differential output with a 60-Ω load (two 120-Ω
termination resistors in parallel), and the differential output must be greater than 1.5 V. The SN55HVD233-SP is
specified to meet the 1.5-V requirement with a 60-Ω load, and additionally specified with a differential output
voltage minimum of 1.2 V across a common mode range of –2 to 7 V through a 330-Ω coupling network. This
network represents the bus loading of 120 SN55HVD233-SP transceivers based on their minimum differential
input resistance of 40 kΩ. Therefore, the SN55HVD233-SP supports up to 120 transceivers on a single bus
segment with margin to the 1.2-V minimum differential input voltage requirement at each node. For CAN network
design, margin must be given for signal loss across the system and cabling, parasitic loadings, network
imbalances, ground offsets, and signal integrity; thus, a practical maximum number of nodes may be lower. Bus
length may also be extended beyond the original ISO11898 standard of 40 m by careful system design and data
rate tradeoffs. For example, CANopen network design guidelines allow the network to be up to 1 km with
changes in the termination resistance, cabling, less than 64 nodes, and significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO11898 CAN standard. Using this flexibility requires good
network design.
12.1.2 CAN Termination
The ISO11898 standard specifies the interconnect to be a twisted pair cable (shielded or unshielded) with 120-Ω
characteristic impedance (ZO). Use resistors equal to the characteristic impedance of the line to terminate both
ends of the cable to prevent signal reflections. Keep unterminated drop lines (stubs) connecting nodes to the bus
as short as possible to minimize signal reflections. The termination may be on the cable or in a node, but if
nodes may be removed from the bus, the termination must be carefully placed so that it is not removed from the
bus.
24
Copyright © 2017, Texas Instruments Incorporated
SN55HVD233-SP
www.ti.com.cn
ZHCSH84A –SEPTEMBER 2017–REVISED DECEMBER 2017
Layout Guidelines (continued)
Node n
(with termination)
Node 1
Node 2
Node 3
MCU or DSP
MCU or DSP
MCU or DSP
MCU or DSP
CAN
Controller
CAN
Controller
CAN
Controller
CAN
Controller
CAN
Transceiver
CAN
Transceiver
CAN
Transceiver
CAN
Transceiver
RTERM
RTERM
Figure 33. Typical CAN Bus
Termination is typically a 120-Ω resistor at each end of the bus. If filtering and stabilization of the common mode
voltage of the bus is desired, then the user may use split termination (see Figure 34). Split termination uses two
60-Ω resistors with a capacitor in the middle of these resistors to ground. Split termination improves the
electromagnetic emissions behavior of the network by eliminating fluctuations in the bus common mode voltages
at the start and end of message transmissions.
Take care with the power ratings of the termination resistors used, especially for the worst-case condition (if a
system power supply is shorted across the termination resistance to ground). In most cases, under the worst-
case condition, much higher current passes through the termination resistance than the CAN transceiver's
current limit.
Split Termination
Standard Termination
CANH
CANH
R
/2
TERM
CAN
Transceiver
CAN
R
TERM
Transceiver
C
SPLIT
R
/2
TERM
CANL
CANL
Figure 34. CAN Bus Termination Concepts
版权 © 2017, Texas Instruments Incorporated
25
SN55HVD233-SP
ZHCSH84A –SEPTEMBER 2017–REVISED DECEMBER 2017
www.ti.com.cn
12.2 Layout Example
RS
GND
D
R1
GND
GND
R5
GND
U1
C7
VCC
R6
R2
R
LBK
Figure 35. Board Layout Example
26
版权 © 2017, Texas Instruments Incorporated
SN55HVD233-SP
www.ti.com.cn
ZHCSH84A –SEPTEMBER 2017–REVISED DECEMBER 2017
13 器件和文档支持
13.1 接收文档更新通知
如需接收文档更新通知,请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册,即可每周接收产
品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
13.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范,
并且不一定反映 TI 的观点;请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
13.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知和修
订此文档。如欲获取此数据表的浏览器版本,请参阅左侧的导航。
版权 © 2017, Texas Instruments Incorporated
27
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
5962L1420901VXC
HVD233HKX/EM
ACTIVE
CFP
CFP
HKX
8
8
1
RoHS & Green
RoHS & Green
NIAU
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
25 to 25
L1420901VXC
HVD233-SP
Samples
Samples
ACTIVE
HKX
1
NIAU
HVD233HKX/EM
EVAL ONLY
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
OTHER QUALIFIED VERSIONS OF SN55HVD233-SP :
Catalog : SN55HVD233-SEP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
5962L1420901VXC
HVD233HKX/EM
HKX
HKX
CFP (HSL)
CFP (HSL)
8
8
1
1
506.98
506.98
26.16
26.16
6220
6220
NA
NA
Pack Materials-Page 1
PACKAGE OUTLINE
HKX0008A
CFP - 2.785 mm max height
S
C
A
L
E
1
.
0
0
0
CERAMIC FLATPACK
B
6X 1.27
2X 3.81
1
4
8
5
6.725
6.225
0.52
8X
0.42
6.735
6.235
A
0.2
C A B
2.785 MAX
0.20
0.12
0.95 MAX
(4.445)
C
4
5
8
1
PIN 1 ID
24 MAX
4223439/C 08/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermetically sealed with a metal lid.
4. The leads are gold plated.
www.ti.com
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