5962L1422603VXC [RENESAS]
Operational Amplifier;
| 型号： | 5962L1422603VXC |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Operational Amplifier |
| 文件： | 总23页 (文件大小：1383K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL70419SEH, ISL73419SEH
Radiation Hardened 36V Quad Precision Low Power Operational Amplifiers with
Enhanced SET Performance
FN8653
Rev.3.00
Nov 21, 2019
The ISL70419SEH and ISL73419SEH contain four very high
Features
precision amplifiers featuring the perfect combination of low
• Electrically screened to DLA SMD# 5962-14226
noise vs power consumption. Low offset voltage, low I
BIAS
current, and low temperature drift make it the ideal choice for
applications requiring both high DC accuracy and AC
performance. The combination of high precision, low noise,
low power, and small footprint provides the user with
outstanding value and flexibility relative to similar competitive
parts.
• Low input offset voltage. . . . . . . . . . . . . . . . . . . ±110µV, Max.
• Superb offset temperature coefficient. . . . . . . 1µV/°C, Max.
• Input bias current . . . . . . . . . . . . . . . . . . . . . . . . . ±15nA, Max.
• Input bias current TC . . . . . . . . . . . . . . . . . . . . ±5pA/°C, Max.
• Low current consumption . . . . . . . . . . . . . . . . . . . . . . . 440µA
• Voltage noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8nV/Hz
• Wide supply range . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 36V
• Operating temperature range. . . . . . . . . . . .-55°C to +125°C
Applications for these amplifiers include precision active
filters, medical and analytical instrumentation, precision
power supply controls, and industrial controls.
The ISL7x419SEH are offered in a 14 Ld hermetic ceramic
flatpack package. These devices are offered in an industry
standard pin configuration and operate across the extended
temperature range from -55°C to +125°C.
• ISL70419SEH radiation acceptance testing
- High dose rate (50-300rad(Si)/s): 300krad(Si)
- Low dose rate (10mrad(Si)/s): 50krad(Si)
Applications
• Precision instrumentation
• Spectral analysis equipment
• Active filter blocks
• ISL73419SEH radiation acceptance testing
- Low dose rate (10mrad(Si)/s): 50krad(Si)
• SEE hardness (see SEE report for details)
2
- SEL/SEB LET (V = ±18V): 86.4MeV•cm /mg
• Thermocouples and RTD reference buffers
• Data acquisition
TH
S
• Power supply control
Related Literature
For a full list of related documents, visit our website:
• ISL70419SEH, ISL73419SEH device pages
10
CH2 = V
- B
OUT
= ±15V
S
9
8
7
6
5
4
3
2
1
0
V
C
1
8.2nF
V
+
-
ISL70419SEH
+
OUTPUT
R
R
2
1
V
IN
1.84k
4.93k
3.3nF
C
2
V
-
-8
-6
-4
-2
0
2
4
SET EXTREME DEVIATION (V)
SALLEN-KEY LOW PASS FILTER (f = 10kHz)
C
2
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. SET DEVIATION vs DURATION FOR LET = 60MeV•cm /mg
FN8653 Rev.3.00
Nov 21, 2019
Page 1 of 23
ISL70419SEH, ISL73419SEH
Ordering Information
ORDERING/
SMD NUMBER
(Note 2)
PART NUMBER
(Note 1)
RADIATION HARDNESS
(Total Ionizing Dose)
TEMPERATURE
RANGE (°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
5962F1422601VXC
ISL70419SEHVF
HDR to 300krad(Si),
LDR to 50krad(Si)
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
14 Ld Flatpack with EPAD K14.C
5962F1422601V9AX ISL70419SEHVX (Note 3)
DIE
5962L1422603VXC
ISL73419SEHVF
LDR to 50krad(Si)
14 Ld Flatpack with EPAD K14.C
5962L1422603V9A
ISL73419SEHVX (Note 3)
ISL70419SEHF/PROTO (Note 4)
ISL73419SEHF/PROTO (Note 4)
DIE
N/A
N/A
N/A
N/A
14 Ld Flatpack with EPAD K14.C
14 Ld Flatpack with EPAD K14.C
N/A
ISL70419SEHX/SAMPLE (Notes 3, 4) N/A
ISL73419SEHX/SAMPLE (Notes 3, 4) N/A
DIE
DIE
N/A
N/A
ISL70419SEHEV1Z (Note 5)
Evaluation Board
NOTES:
1. These Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb
and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed must be
used when ordering.
3. Die product tested at T = + 25°C. The wafer probe test includes functional and parametric testing sufficient to make the die capable of meeting the
A
electrical performance outlined in “Electrical Specifications” on page 4.
4. The /PROTO and /SAMPLE are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity. These parts are intended for
engineering evaluation purposes only. The /PROTO parts meet the electrical limits and conditions across temperature specified in the DLA SMD and
are in the same form and fit as the qualified device. The /SAMPLE parts are capable of meeting the electrical limits and conditions specified in the
DLA SMD. The /SAMPLE parts do not receive 100% screening across temperature to the DLA SMD electrical limits. These part types do not come
with a Certificate of Conformance because they are not DLA qualified devices.
5. Evaluation boards use the /PROTO parts and /PROTO parts are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity.
FN8653 Rev.3.00
Nov 21, 2019
Page 2 of 23
ISL70419SEH, ISL73419SEH
Pin Configuration
14 LD FLATPACK
TOP VIEW
OUT_A
OUT_D
14
13
12
11
10
9
1
2
3
4
5
6
7
A
D
-IN_A
+IN_A
V+
-IN_D
+IN_D
V-
-
-
+
+
-
-
+IN_B
-IN_B
OUT_B
+IN_C
-IN_C
OUT_C
+
B
+
C
8
Pin Descriptions
PIN NUMBER
PIN NAME
EQUIVALENT CIRCUIT
Circuit 2
Circuit 1
Circuit 1
Circuit 3
Circuit 1
Circuit 1
Circuit 2
Circuit 2
Circuit 1
Circuit 1
Circuit 3
Circuit 1
Circuit 1
Circuit 2
N/A
DESCRIPTION
1
2
OUT_A
-IN_A
+IN_A
V+
Amplifier A output
Amplifier A inverting input
Amplifier A non-inverting input
Positive power supply
3
4
5
+IN_B
-IN_B
OUT_B
OUT_C
-IN_C
+IN_C
V-
Amplifier B non-inverting input
Amplifier B inverting input
Amplifier B output
6
7
8
Amplifier C output
9
Amplifier C inverting input
Amplifier C non-inverting input
Negative power supply
10
11
12
13
14
+IN_D
-IN_D
OUT_D
EPAD
Amplifier D non-inverting input
Amplifier D inverting input
Amplifier D output
EPAD under Package (unbiased, tied to package lid)
V+
V+
V+
500Ω
500Ω
CAPACITIVELY
COUPLED
ESD CLAMP
IN-
IN+
OUT
V-
V-
V-
CIRCUIT 1
CIRCUIT 2
CIRCUIT 3
FN8653 Rev.3.00
Nov 21, 2019
Page 3 of 23
ISL70419SEH, ISL73419SEH
Absolute Maximum Ratings
Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V
Maximum Supply Voltage (LET = 86.4MeV•cm /mg) . . . . . . . . . . . . . 36V
Thermal Resistance (Typical)
14 Ld Flatpack (Notes 6, 7). . . . . . . . . . . . .
(°C/W)
35
(°C/W)
8
JA
JC
2
Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Maximum Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
Max/Min Input current for Input Voltage >V+ or <V-. . . . . . . . . . . . . . . . ±20mA
Output Short-Circuit Duration (1 output at a time). . . . . . . . . . . . . . . . Indefinite
ESD Rating
Human Body Model (Tested per MIL-PRF-883 3015.7). . . . . . . . . . . 2kV
Machine Model (Tested per EIA/JESD22-A115-A) . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 750V
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature (T ) . . . . . . . . . . . . . . . . . . . . .+150°C
JMAX
Recommended Operating Conditions
Ambient Operating Temperature Range . . . . . . . . . . . . . .-55°C to +125°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V (±5V) to 30V (±15V)
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. is measured in free air with the component mounted on a high-effective thermal conductivity test board with direct attach features. See TB379.
JA
7. For , the case temperature location is the center of the package underside.
JC
Electrical Specifications
V
± 15V, V = 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits apply across the operating
CM
S
O
A
temperature range, -55°C to +125°C; over a total ionizing dose of 300krad(Si) with exposure at a high dose rate of 50 - 300rad(Si)/s (ISL70419SEH only);
or across a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s.
MIN
MAX
PARAMETER
Input Offset Voltage
SYMBOL
TEST CONDITIONS
(Note 8)
TYP
10
(Note 8)
UNIT
µV
V
85
110
1
OS
µV
Offset Voltage Drift
Input Bias Current
TCV
Established by characterization not
tested
0.1
µV/°C
OS
I
-2.5
-5
0.08
2.5
5
nA
nA
B
T
= -55°C to +125°C
A
Over high and low dose radiation
-15
-5
15
5
nA
Input Bias Current Temperature
Coefficient
TCI
Established by characterization not
tested
1
pA/°C
B
Input Offset Current
I
-2.5
-3
0.08
2.5
3
nA
nA
OS
T
= -55°C to +125°C
A
Over high and low dose radiation
-10
-3
10
3
nA
Input Offset Current Temperature
Coefficient
TCI
Established by characterization not
tested
0.42
pA/°C
OS
Input Voltage Range
V
Established by CMRR test
-13
120
13
V
dB
dB
dB
dB
V/mV
V
CM
Common-Mode Rejection Ratio
CMRR
V
V
V
= -13V to +13V
145
145
CM
120
Power Supply Rejection Ratio
PSRR
= ±2.25V to ±20V
120
S
120
Open-Loop Gain
A
= -13V to +13V, R = 10kΩ to ground
3,000
13.5
13.2
13.3
13.0
14,000
13.7
VOL
O
L
Output Voltage High
V
R
= 10kΩ to ground
OH
L
V
R
= 2kΩ to ground
13.55
V
L
V
FN8653 Rev.3.00
Nov 21, 2019
Page 4 of 23
ISL70419SEH, ISL73419SEH
Electrical Specifications
V
± 15V, V = 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits apply across the operating
CM
S
O
A
temperature range, -55°C to +125°C; over a total ionizing dose of 300krad(Si) with exposure at a high dose rate of 50 - 300rad(Si)/s (ISL70419SEH only);
or across a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. (Continued)
MIN
MAX
PARAMETER
Output Voltage Low
SYMBOL
TEST CONDITIONS
= 10kΩ to ground
(Note 8)
TYP
(Note 8)
UNIT
V
V
R
R
-13.7
-13.5
-13.2
-13.3
-13.0
0.625
0.75
OL
L
L
V
= 2kΩ to ground
-13.55
0.44
43
V
V
Supply Current/Amplifier
I
mA
mA
mA
V
S
Short-Circuit Current
Supply Voltage Range
AC SPECIFICATIONS
Gain Bandwidth Product
I
SC
V
Established by PSRR
± 2.25
± 20
SUPPLY
GBWP
A
= 1k, R = 2kΩ
1.5
0.25
10
MHz
V
L
Voltage Noise V
e
0.1Hz to 10Hz
f = 10Hz
µV
P-P
P-P
nVp-p
Voltage Noise Density
Voltage Noise Density
Voltage Noise Density
Voltage Noise Density
Current Noise Density
Total Harmonic Distortion
e
e
e
e
nV/Hz
nV/Hz
nV/Hz
nV/Hz
pA/Hz
%
n
n
n
n
f = 100Hz
f = 1kHz
8.2
8
f = 10kHz
f = 1kHz
8
in
THD + N
0.1
1kHz, G = 1, V = 3.5V
, R = 2kΩ
0.0009
0.0005
O
RMS
L
1kHz, G = 1, V = 3.5V
, R = 10kΩ
%
O
RMS
L
TRANSIENT RESPONSE
Slew Rate, V
20% to 80%
SR
A
= 11, R = 2kΩV = 4V
0.3
0.5
130
130
V/µs
V/µs
ns
OUT
V
L
O
P-P
0.2
Rise Time
10% to 90% of V
t , t ,
A
= 1,
V
= 50mV
,
450
625
600
700
r
f
V
OUT
P-P
small signal
RL = 10kΩto V
OUT
OUT
CM
ns
Fall Time
90% to 10% of V
A
= 1,
V
= 50mV , RL = 10kΩto V
P-P CM
ns
V
OUT
ns
Settling Time to 0.1%
10V Step; 10% to V
t
A
A
A
A
= -1,
= -1,
= -1,
= -1,
V
= 10V , RL = 5kΩto V
P-P CM
21
24
13
18
µs
s
V
V
V
V
OUT
OUT
OUT
OUT
OUT
Settling Time to 0.01%
10V Step; 10% to V
V
V
V
= 10V , RL = 5kΩto V
P-P
µs
µs
µs
CM
OUT
Settling Time to 0.1%
4V Step; 10% to V
= 4V , RL = 5kΩto V
P-P
CM
OUT
Settling Time to 0.01%
4V Step; 10% to V
= 4V , RL = 5kΩto V
P-P
CM
OUT
Output Positive Overload Recovery Time
Output Negative Overload Recovery Time
Positive Overshoot
t
A
A
A
= -100, V = 0.2
V
V
RL = 2kΩto V
5.6
10.6
15
µs
µs
%
OL
V
V
V
IN
P-P,
P-P,
CM
= -100, V = 0.2
IN
RL = 2kΩto V
CM
OS+
OS-
= 1,
V
= 10V , R = 0Ω
P-P
OUT
f
RL = 2kΩto V
CM
33
33
%
Negative Overshoot
A
= 1,
V
= 10V , R = 0Ω
P-P
15
%
V
OUT
f
RL = 2kΩto V
CM
%
FN8653 Rev.3.00
Nov 21, 2019
Page 5 of 23
ISL70419SEH, ISL73419SEH
Electrical Specifications
V
± 5V, V = 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits apply over the operating
CM
S
O
A
temperature range, -55°C to +125°C; over a total ionizing dose of 300krad(Si) with exposure at a high dose rate of 50 - 300krad(Si)/s (ISL70419SEH only);
or over a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s.
MAX
MIN
PARAMETER
Input Offset Voltage
SYMBOL
CONDITIONS
TYP
10
(Note 8)
UNIT
µV
(Note 8)
V
150
OS
250
1
µV
Offset Voltage Drift
Input Bias Current
TCV
Established by characterization not
tested
0.1
µV/°C
OS
I
-2.5
-5
0.08
2.5
5
nA
nA
nA
B
T
= -55°C to +125°C
A
Over high and low dose radiation
-15
15
Input Bias Current Temperature
Coefficient
TCI
Established by characterization not
tested
-5
1
5
pA/°C
B
Input Offset Current
I
-2.5
-3
0.08
2.5
3
nA
nA
nA
OS
T
= -55°C to +125°C
A
Over high and low dose radiation
-10
10
Input Offset Current Temperature
Coefficient
TCI
Established by characterization not
tested
-3
0.42
3
pA/°C
OS
Input Voltage Range
V
Established by CMRR test
-3
3
V
dB
CM
Common-Mode Rejection Ratio
CMRR
V
V
V
= -3V to +3V
120
120
120
120
3000
145
145
CM
dB
Power Supply Rejection Ratio
PSRR
= ±2.25V to ±5V
dB
S
dB
Open-Loop Gain
A
= -3.0V to +3.0V
14000
3.7
V/mV
VOL
O
R
= 10kΩ to ground
L
Output Voltage High
V
R
= 10kΩ to ground
= 2kΩ to ground
= 10kΩ to ground
= 2kΩ to ground
3.5
3.2
3.3
3.0
V
V
OH
L
R
R
R
3.55
-3.7
V
L
L
L
V
Output Voltage Low
V
-3.5
-3.2
V
OL
V
-3.55
0.44
43
-3.3
V
-3.0
V
Supply Current/Amplifier
I
0.625
0.75
mA
mA
mA
S
Short-Circuit Current
AC SPECIFICATIONS
Gain Bandwidth Product
Voltage Noise
I
SC
GBWP
A
= 1k, R = 2kΩ
1.5
0.25
12
8.6
8
MHz
V
L
e
0.1Hz to 10Hz
f = 10Hz
µV
P-P
np-p
Voltage Noise Density
Voltage Noise Density
Voltage Noise Density
Voltage Noise Density
Current Noise Density
e
e
e
e
nV/Hz
nV/Hz
nV/Hz
nV/Hz
pA/Hz
n
n
n
n
f = 100Hz
f = 1kHz
f = 10kHz
f = 1kHz
8
in
0.1
FN8653 Rev.3.00
Nov 21, 2019
Page 6 of 23
ISL70419SEH, ISL73419SEH
Electrical Specifications
V
± 5V, V = 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits apply over the operating
CM
S
O
A
temperature range, -55°C to +125°C; over a total ionizing dose of 300krad(Si) with exposure at a high dose rate of 50 - 300krad(Si)/s (ISL70419SEH only);
or over a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. (Continued)
MAX
MIN
PARAMETER
TRANSIENT RESPONSE
SYMBOL
SR
CONDITIONS
TYP
(Note 8)
UNIT
(Note 8)
Slew Rate, V
Rise Time
20% to 80%
A
A
= 11, R = 2kΩV = 4V
0.5
V/µs
ns
OUT
V
L
O
P-P
t , t ,
= 1, V
= 50mV ,
P-P
130
r
f
V
OUT
10% to 90% of V
small signal
R
= 10kΩ to V
OUT
OUT
L
CM
Fall Time
90% to 10% of V
A
= 1,
V
= 50mV
,
130
12
19
7
ns
µs
µs
µs
µs
%
V
OUT
P-P
,
RL = 10kΩto V
CM
Settling Time to 0.1%
4V Step; 10% to V
t
A
= -1,
V
= 4V
CM
s
V
OUT
P-P
RL = 5kΩto V
OUT
Settling Time to 0.01%
4V Step; 10% to V
A
= -1,
V
= 4V
CM
,
V
OUT
P-P
RL = 5kΩto V
OUT
Output Positive Overload Recovery Time
Output Negative Overload Recovery Time
Positive Overshoot
t
A
= -100, V = 0.2V
OL
V IN P-P
RL = 2kΩto V
CM
A
= -100, V = 0.2V
5.8
15
15
V
IN P-P
RL = 2kΩto V
CM
= 10V , R = 0Ω
OS+
OS-
A = 1, V
V
OUT
RL = 2kΩto V
P-P
f
CM
= 10V , R = 0Ω
Negative Overshoot
A
= 1,
V
%
V
OUT
P-P
f
RL = 2kΩto V
CM
NOTE:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.
FN8653 Rev.3.00
Nov 21, 2019
Page 7 of 23
ISL70419SEH, ISL73419SEH
Typical Performance Curves
V
= ±15V, V = 0V, R = Open, T = +25°C, unless otherwise specified.
CM
S
L
A
100
100
80
V
= ±15V
S
V
= ±5V
S
75
50
60
40
25
20
0
0
-20
-40
-60
-80
-100
-25
-50
-75
-100
-70 -50 -30 -10
10
30
50
70
90
110 130
-70 -50 -30 -10
10
30
50
70
90
110 130
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 3. V vs TEMPERATURE
OS
FIGURE 4. V vs TEMPERATURE
OS
500
400
300
200
100
0
500
400
300
200
100
0
V
= ±15V
S
V
= ±15V
S
-100
-200
-300
-400
-500
-100
-200
-300
-400
-500
-70 -50 -30 -10
10
30
50
70
90 110 130
-70 -50 -30 -10
10
30
50
70
90
110 130
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 5. I + vs TEMPERATURE
FIGURE 6. I - vs TEMPERATURE
B
B
500
400
300
200
100
0
500
400
300
200
100
0
V
= ±5V
S
V
= ±5V
S
-100
-200
-300
-400
-500
-100
-200
-300
-400
-500
-70 -50 -30 -10
10
30
50
70
90
110 130
-70 -50 -30 -10
10
30
50
70
90
110 130
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 7. I + vs TEMPERATURE
FIGURE 8. I - vs TEMPERATURE
B
B
FN8653 Rev.3.00
Nov 21, 2019
Page 8 of 23
ISL70419SEH, ISL73419SEH
Typical Performance Curves
V
= ±15V, V = 0V, R = Open, T = +25°C, unless otherwise specified. (Continued)
CM
S
L
A
500
500
400
300
200
100
0
V
= ±5V
V
= ±15V
S
400
300
200
100
0
S
-100
-200
-300
-400
-500
-100
-200
-300
-400
-500
-70 -50 -30 -10
10
30
50
70
90
110 130
-70 -50 -30 -10
10
30
50
70
90 110 130
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 9. I vs TEMPERATURE
OS
FIGURE 10. I vs TEMPERATURE
OS
0.65
25000
20000
15000
10000
0.60
0.55
0.50
0.45
0.40
0.35
0.30
V
= ±13V
O
15V
5V
-75
-50
-25
0
25
50
75
100
125
150
-70 -50 -30 -10
10
30
50
70
90
110 130
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 11. SUPPLY CURRENT PER AMP vs TEMPERATURE
FIGURE 12. AV vs TEMPERATURE
OL
-120
-125
-130
-135
-140
-145
-150
-120
-130
-140
-150
-160
V
= ±2.25V TO ±20V
S
V
= ±13V
CM
-70 -50 -30 -10
10
30
50
70
90
110 130
-70 -50 -30 -10
10
30
50
70
90
110 130
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 13. PSRR vs TEMPERATURE
FIGURE 14. CMRR vs TEMPERATURE
FN8653 Rev.3.00
Nov 21, 2019
Page 9 of 23
ISL70419SEH, ISL73419SEH
Typical Performance Curves
V
= ±15V, V = 0V, R = Open, T = +25°C, unless otherwise specified. (Continued)
CM
S
L
A
-20
60
I
- AT ±15V
SC
I
+ AT ±15V
SC
-25
-30
-35
-40
-45
-50
-55
-60
55
50
45
40
35
30
25
20
-70 -50 -30 -10
10
30
50
70
90
110 130
-70 -50 -30 -10
10
30
50
70
90
110 130
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 15. SHORT CIRCUIT CURRENT vs TEMPERATURE
FIGURE 16. SHORT CIRCUIT CURRENT vs TEMPERATURE
100
100
80
75
50
V
(µ) -55°C
OS
60
+125°C
25
40
0
20
0
+25°C
-55°C
-25
-50
-75
-100
V
(µ) +25°C
OSD
-20
-40
-60
V
(µ) +125°C
OSD
0
-5
-3
-1
1
3
5
-15
-10
-5
5
10
15
VCM (V)
V
(V)
CM
FIGURE 17. INPUT V vs INPUT COMMON MODE VOLTAGE,
OS
FIGURE 18. INPUT V vs INPUT COMMON MODE VOLTAGE,
OS
V
= ±15
V = ±5V
S
S
14.1
14.0
13.9
13.8
13.7
13.6
13.5
13.4
13.3
13.2
13.1
-13.1
-13.2
-13.3
-13.4
-13.5
-13.6
-13.7
-13.8
-13.9
-14.0
-14.1
V
= +15V
S
V
R
= +15V
= 10kΩ
S
R
= 10kΩ
L
L
-70 -50 -30 -10
10
30
50
70
90
110 130
-70 -50 -30 -10
10
30
50
70
90
110 130
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 19. V
vs TEMPERATURE
FIGURE 20. V
vs TEMPERATURE
OUT
OUT
FN8653 Rev.3.00
Nov 21, 2019
Page 10 of 23
ISL70419SEH, ISL73419SEH
Typical Performance Curves
V
= ±15V, V = 0V, R = Open, T = +25°C, unless otherwise specified. (Continued)
CM
S
L
A
14.1
-13.1
V
R
= +15V
= 2kΩ
S
-13.2
-13.3
-13.4
-13.5
-13.6
-13.7
-13.8
-13.9
-14.0
-14.1
14.0
13.9
13.8
13.7
13.6
13.5
13.4
13.3
13.2
13.1
V
R
= +15V
= 2kΩ
S
L
L
.2
-14
-70 -50 -30 -10
10
30
50
70
90
110 130
-70 -50 -30 -10
10
30
50
70
90 110 130
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 22. V
vs TEMPERATURE
FIGURE 21. V
vs TEMPERATURE
OUT
OUT
250
200
150
100
50
100
10
1
V
= ±18.2V
S
AV = 1
0
-50
-100
-150
-200
-250
V+ = 36.4V
= 10, R = 100k
R
g
f
AV = 10,000
1
10
100
1k
10k
100k
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (Hz)
TIME (s)
FIGURE 23. INPUT NOISE VOLTAGE 0.1Hz to 10Hz
FIGURE 24. INPUT NOISE VOLTAGE SPECTRAL DENSITY
1
200
180
160
140
120
100
80
V
= ±18.2V
S
AV = 1
PHASE
60
40
20
0
GAIN
-20
-40
-60
-80
-100
R
C
= 10k
L
= 10pF
L
SIMULATION
0.1
1
0.1m 1m 10m 100m 1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 25. INPUT NOISE CURRENT SPECTRAL DENSITY
FIGURE 26. OPEN-LOOP GAIN, PHASE vs FREQUENCY, R = 10kΩ
L
C = 10pF
L
FN8653 Rev.3.00
Nov 21, 2019
Page 11 of 23
ISL70419SEH, ISL73419SEH
Typical Performance Curves
V
= ±15V, V = 0V, R = Open, T = +25°C, unless otherwise specified. (Continued)
CM
S
L
A
220
200
180
160
140
120
100
80
200
180
160
140
120
100
80
60
40
20
V
= ±2.5V
S
V
S
= ±5V
PHASE
V
= ±15V
S
GAIN
0
-20
-40
-60
60
R
C
= 10k
L
L
R
C
= INF
L
L
= 100pF
40
= 10pF
SIMULATION
20
-80
SIMULATION
-100
0
0.1m 1m 10m 100m
1
10 100 1k 10k 100k 1M 10M 100M
1m 10m 100m
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 27. OPEN-LOOP GAIN, PHASE vs FREQUENCY, R = 10kΩ
FIGURE 28. CMRR vs FREQUENCY, V = ±2.25, ±5V, ±15V
S
L
C = 100pF
L
120
110
100
90
80
70
60
50
40
30
20
10
0
70
R
= 100, R = 100k
f
g
AV = 1000
AV = 100
AV = 10
60
50
40
30
20
10
0
R
= 1k, R = 100k
f
g
V
C
R
= ±20V
= 4pF
= 10k
S
L
PSRR+ AND PSRR- V = ±2.25V
S
L
R
C
= INF
= 4pF
L
L
V
= 50mV
P-P
OUT
AV = +1
= 1V
V
R
= 10k, R = 100k
f
CM
P-P
g
AV = 1
PSRR+ AND PSRR- V = ±15V
S
R
= OPEN, R = 0
f
g
-10
-10
10
100
1k
10k
100k
1M
10M
10M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 29. PSRR vs FREQUENCY, V = ±5V, ±15V
S
FIGURE 30. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
4
2
2
R
= 10k
L
R = R = 100k
1
0
f
g
0
-2
-4
-6
-8
-10
R = R = 10k
-1
-2
-3
-4
-5
-6
-7
-8
f
g
R
= 4.99k
= 1k
L
R = R = 1k
f
g
R
L
R = R = 100
f
g
V
= ±20V
= 10k
S
V
= ±20V
C = 4pF
L
R
R
= 499
S
L
L
L
C
= 4pF
-12
-14
-16
AV = +2
= 50mV
AV = +1
= 50mV
R
= 100
100k
L
V
V
OUT
P-P
OUT
P-P
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 31. FREQUENCY RESPONSE vs FEEDBACK RESISTANCE
R /R
FIGURE 32. GAIN vs FREQUENCY vs R
L
f
g
FN8653 Rev.3.00
Nov 21, 2019
Page 12 of 23
ISL70419SEH, ISL73419SEH
Typical Performance Curves
V
= ±15V, V = 0V, R = Open, T = +25°C, unless otherwise specified. (Continued)
CM
S
L
A
12
2
1
V
= ±2.25V
S
V
= ±2.5V
= 10k
S
10
8
R
L
V
= ±5V
S
0
AV = +1
= 50mV
V
OUT
P-P
6
-1
-2
-3
-4
-5
-6
-7
-8
4
V
= ±15V
S
2
C = 0.01µF
L
C
= 47pF
L
V
= ±20V
S
0
-2
-4
-6
-8
C
= 100pF
C
R
= 4pF
= 10k
L
L
L
C
= 4pF
C
= 270pF
L
L
AV = +1
C
= 470pF
L
V
= 50mV
OUT
P-P
C
= 1000pF
10k
L
10
100
1k
100k
1M
10M
10k
FREQUENCY (Hz)
10
100
1k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 33. GAIN vs FREQUENCY vs C
FIGURE 34. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
L
180
160
140
120
100
80
2.4
2.0
1.6
1.2
0.8
0.4
0
V
S
= ±15V, R = 2k, 10k
L
S
V
= ±15V
S
R -DRIVER CH. = OPEN
V
= ±5V, R = 2k, 10k
L
L
-0.4
-0.8
-1.2
-1.6
-2.0
-2.4
R -RECEIVING CH. = 10k
L
60
C
= 4pF
L
C
= 4pF
L
40
AV = +1
AV = +1
V
= 4V
V
= 1V
OUT
P-P
20
SOURCE
P-P
1k
0
10
100
10k
100k
1M
10M
0
10
20
30
40
50
60
70
80
90 100
FREQUENCY (Hz)
TIME (µs)
FIGURE 35. CROSSTALK, V = ±15V
S
FIGURE 36. LARGE SIGNAL TRANSIENT RESPONSE vs R V = ±5V,
L
S
±15V
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
60
50
40
30
20
10
0
SR+
V
=±5, ±15V
S
R
C
= 10k
= 4pF
L
L
SR-
R
L
= 2k, 10k
= 7pF
AV = +1
= 50mV
C
L
V
OUT
P-P
AV = 1
V
= 4V
OUT
= ±5V, ±15V
P-P
V
S
-10
-70 -50 -30 -10
10
30
50
70
90 110 130
0
5
10
15
20
TIME (µs)
25
30
35
40
TEMPERATURE (°C)
FIGURE 38. SMALL SIGNAL TRANSIENT RESPONSE, V = ±5V, ±15V
S
FIGURE 37. SLEW RATE vs TEMPERATURE V = ±5V, ±15V
S
FN8653 Rev.3.00
Nov 21, 2019
Page 13 of 23
ISL70419SEH, ISL73419SEH
Typical Performance Curves
V
= ±15V, V = 0V, R = Open, T = +25°C, unless otherwise specified. (Continued)
CM
S
L
A
0.04
0.00
14
0.24
2
12
10
8
0.20
0.16
0.12
0.08
0.04
0.00
-0.04
-0.08
0
-0.04
-0.08
-0.12
-2
-4
IN
6
-6
OUT 5V
OUT 15V
IN
OUT 5V
OUT 15V
-0.16
4
-8
-0.20
2
-10
-12
-14
-0.24
-0.28
0
-2
0
10 20 30 40 50 60 70 80 90 100
TIME (µs)
FIGURE 39. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,
= ±5V, ±15V, R = 2k, C = 4pF, A = -100, R = 100k,
0
10 20 30 40 50 60 70 80 90 100
TIME (µs)
FIGURE 40. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,
= ±5V, ±15V, R = 2k, C = 4pF, A = -100, R = 100k,
V
V
S
S
L
L
V
f
L
L
V
f
R
= 1k, V = 200mV
R
= 1k, V = 200mV
g
IN
p-p
g
IN p-p
80
70
60
50
40
30
20
10
0
6
5
V
R
= ±15V
= 10k
S
L
4
AV = 1
= 50mV
3
V
OUT
P-P
2
V
AT -55°C
OUT
1
0
-1
-2
-3
-4
-5
-6
R
= 10k
= 7pF
L
L
V
AT +25°C
OUT
C
AV = 1
= ±5.9V
V
AT +125°C
OUT
V
IN
P-P
V
= ±5V
S
V
IN
1
10
100
1k
10k
100k
0
0.2
0.4
0.6
0.8
1.0 1.2
1.4 1.6 1.8
2.0
CAPACITANCE (pF)
TIME (ms)
FIGURE 42. OUTPUT PHASE REVERSAL RESPONSE vs TEMPERATURE
FIGURE 41. % OVERSHOOT vs LOAD CAPACITANCE, V = ±15V
S
FN8653 Rev.3.00
Nov 21, 2019
Page 14 of 23
ISL70419SEH, ISL73419SEH
Post High Dose Radiation Characteristics Unless otherwise specified, V ± 15V, V = 0, V = 0V, T = +25°C. This data is
S
CM
O
A
typical mean test data post radiation exposure at a high dose rate of 50 - 300rad(Si)/s. This data is intended to show typical parameter shifts due to high
dose rate radiation. These are not limits nor are they guaranteed. ISL70419SEH only.
25
20
15
10
5
3
2
1
0
0
-5
ICC HDR BIASED
IEE HDR BIASED
ICC HDR GROUNDED
IEE HDR GROUNDED
-1
-2
-3
CHA HDR BIASED
CHB HDR BIASED
CHC HDR BIASED
CHD HDR BIASED
CHA HDR GROUNDED
CHB HDR GROUNDED
CHC HDR GROUNDED
CHD HDR GROUNDED
-10
-15
-20
-25
0
50
100
150
200
250
300
0
50
100
150
200
250
300
krad(Si)
krad(Si)
FIGURE 43. SUPPLY CURRENT vs HIGH DOSE RATE RADIATION
FIGURE 44. V vs HIGH DOSE RATE RADIATION
OS
5
4
5
4
3
2
1
0
3
2
1
0
-1
-2
-3
-4
-5
-1
CHA HDR GROUNDED
-2
-3
-4
-5
CHA HDR BIASED
CHA HDR GROUNDED
CHB HDR GROUNDED
CHC HDR GROUNDED
CHD HDR GROUNDED
CHA HDR BIASED
CHB HDR BIASED
CHC HDR BIASED
CHD HDR BIASED
CHB HDR GROUNDED
CHC HDR GROUNDED
CHD HDR GROUNDED
CHB HDR BIASED
CHC HDR BIASED
CHD HDR BIASED
0
50
100
150
200
250
300
0
50
100
150
200
250
300
krad(Si)
krad(Si)
FIGURE 45. I + vs HIGH DOSE RATE RADIATION
B
FIGURE 46. I - vs HIGH DOSE RATE RADIATION
B
5
4
3
2
1
0
-1
CHA HDR GROUNDED
CHB HDR GROUNDED
CHC HDR GROUNDED
CHD HDR GROUNDED
CHA HDR BIASED
CHB HDR BIASED
CHC HDR BIASED
CHD HDR BIASED
-2
-3
-4
-5
0
50
100
150
200
250
300
krad(Si)
FIGURE 47. I vs HIGH DOSE RATE RADIATION
OS
FN8653 Rev.3.00
Nov 21, 2019
Page 15 of 23
ISL70419SEH, ISL73419SEH
Post Low Dose Radiation Characteristics Unless otherwise specified, V ± 15V, V = 0, V = 0V, T = +25°C. This data is
S
CM
O
A
typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to low
dose rate radiation. These are not limits nor are they guaranteed
2.5
2.0
1.5
1.0
0.5
0
50
40
30
ICC GROUNDED
ICC BIASED
20
10
0
-0.5
-1.0
-1.5
-2.0
-2.5
-10
-20
-30
-40
-50
CHA BIASED
CHC BIASED
CHA GROUNDED
CHC GROUNDED
CHB BIASED
CHD BIASED
CHB GROUNDED
CHD GROUNDED
IEE GROUNDED
IEE BIASED
0
10
20
30
40
50
0
10
20
30
40
50
krad(Si)
krad(Si)
FIGURE 48. SUPPLY CURRENT vs LOW DOSE RATE RADIATION
FIGURE 49. V vs LOW DOSE RATE RADIATION
OS
15
10
5
15
10
5
0
0
CHB BIASED
CHA BIASED
CHC BIASED
CHA BIASED
CHC BIASED
CHB BIASED
CHD BIASED
-5
-5
CHD BIASED
CHA GROUNDED
CHC GROUNDED
CHA GROUNDED
CHC GROUNDED
CHB GROUNDED
CHD GROUNDED
CHB GROUNDED
CHD GROUNDED
-10
-15
-10
-15
0
10
20
30
40
50
0
10
20
30
40
50
krad(Si)
krad(Si)
FIGURE 50. I + vs LOW DOSE RATE RADIATION
B
FIGURE 51. I - vs LOW DOSE RATE RADIATION
B
10
8
6
4
2
0
-2
CHB BIASED
CHD BIASED
CHA BIASED
CHC BIASED
CHA GROUNDED
CHC GROUNDED
-4
-6
CHB GROUNDED
CHD GROUNDED
-8
-10
0
10
20
30
40
50
krad(Si)
FIGURE 52. I vs LOW DOSE RATE RADIATION
OS
FN8653 Rev.3.00
Nov 21, 2019
Page 16 of 23
ISL70419SEH, ISL73419SEH
Input ESD Diode Protection
Applications Information
Functional Description
The ISL7x419SEH contain four low noise precision operational
amplifiers (op amps). These devices are fabricated in a precision
40V complementary bipolar DI process. A super-beta NPN input
stage with input bias current cancellation provides low input bias
current (180pA typical), low input offset voltage (13µV typical),
low input noise voltage (8nV/Hz), and low 1/f noise corner
frequency (~8Hz). The ISL7x419SEH also feature high open-loop
gain (14kV/mV) for excellent CMRR (145dB) and THD+N
The input terminals (IN+ and IN-) have internal ESD protection
diodes to the positive and negative supply rails, series connected
500Ω current limiting resistors, and an anti-parallel diode pair
across the inputs (Figure 53).
V+
500
500
V
OUT
performance (0.0005% at 3.5V
, 1kHz into 2kΩ). A
RMS
V
R
IN
L
complementary bipolar output stage enables high capacitive
load drive without external compensation.
V-
Operating Voltage Range
The ISL7x419SEH are designed to operate across the 4.5V
(±2.25V) to 36V (±18V) voltage range and is fully characterized
at 10V (±5V) and 30V (±15V). The Power Supply Rejection Ratio
typically exceeds 140dB across the full operating voltage range
and 120dB minimum across the -55°C to +125°C temperature
range. The worst case common-mode input voltage range
over-temperature is 2V to each rail. With ±15V supplies,
Common-Mode Rejection Ratio (CMRR) performance is typically
>130dB over-temperature. The minimum CMRR performance
across the -55°C to +125°C temperature range is >120dB for
power supply voltages from ±5V (10V) to ±15V (30V).
FIGURE 53. INPUT ESD DIODE CURRENT LIMITING- UNITY GAIN
The series resistors limit the high feed-through currents that can
occur in pulse applications when the input dV/dT exceeds the
0.5V/µs slew rate of the amplifier. Without the series resistors,
the input can forward-bias the anti-parallel diodes, causing
current to flow to the output resulting in severe distortion and
possible diode failure.
Figure 36 provides an example of distortion free large signal
response using a 4V
input pulse with an input rise time of
P-P
<1ns. The series resistors enable the input differential voltage to
be equal to the maximum power supply voltage (36V) without
damage.
Input Performance
The super-beta NPN input pair provides excellent frequency
response while maintaining high input precision. High NPN beta
(>1000) reduces input bias current while maintaining good
frequency response, low input bias current, and low noise. Input
bias cancellation circuits provide additional bias current
reduction to <5nA and excellent temperature stabilization.
Figures 6 through 8 show the high degree of bias current stability
at ±5V and ±15V supplies that is maintained across the -55°C to
+125°C temperature range. The low bias current TC also
produces very low input offset current TC, which reduces DC
input offset errors in precision high impedance amplifiers.
In applications where one or both amplifier input terminals are at
risk of exposure to high voltages beyond the power supply rails,
current limiting resistors may be needed at the input terminal to
limit the current through the power supply ESD diodes to 20mA
maximum.
Output Current Limiting
The output current is internally limited to approximately ±45mA
at +25°C and can withstand a short-circuit to either rail if the
power dissipation limits are not exceeded. This applies to only
one amplifier at a time for the quad operational amplifier.
Continuous operation under these conditions may degrade long
term reliability. Figures 15 and 16 on page 10 show the current
limit variation with temperature.
The +25°C maximum input offset voltage (V ) is 75µV at ±15V
OS
supplies. The input offset voltage temperature coefficient
(V TC) is a maximum of ±1.0µV/°C. The V temperature
OS OS
behavior is smooth (Figures 3 through 4), maintaining constant
TC across the entire temperature range.
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. The ISL7x419SEH are immune to output phase reversal,
even when the input voltage is 1V beyond the supplies.
FN8653 Rev.3.00
Nov 21, 2019
Page 17 of 23
ISL70419SEH, ISL73419SEH
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply conditions. It
is therefore important to calculate the maximum junction
temperature (T
) for all applications to determine if power
JMAX
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related using Equation 1:
(EQ. 1)
T
= T
+ xPD
MAX JA MAXTOTAL
JMAX
where:
• P
is the sum of the maximum power dissipation of
DMAXTOTAL
each amplifier in the package (PD
)
MAX
• PD
for each amplifier can be calculated using Equation 2:
MAX
V
OUTMAX
R
L
----------------------------
PD
= V I
+ V - V
OUTMAX
(EQ. 2)
MAX
S
qMAX
S
where:
• T
= Maximum ambient temperature
MAX
• = Thermal resistance of the package
JA
• PD
= Maximum power dissipation of one amplifier
MAX
• V = Total supply voltage
S
• I
qMAX
= Maximum quiescent supply current of one amplifier
= Maximum output voltage swing of the application
• V
OUTMAX
FN8653 Rev.3.00
Nov 21, 2019
Page 18 of 23
ISL70419SEH, ISL73419SEH
TOP METALLIZATION
Package Characteristics
Weight of Packaged Device
Type: AlCu (99.5%/0.5%)
Thickness: 30kÅ
0.6043 grams (Typical)
BACKSIDE FINISH
Silicon
Lid Characteristics
Finish: Gold
Potential: Unbiased; tied to EPAD
Case Isolation to Any Lead: 20 x 10 Ω (min)
PROCESS
Dielectrically Isolated Complementary Bipolar - PR40
9
ASSEMBLY RELATED INFORMATION
Die Characteristics
Die Dimensions
SUBSTRATE POTENTIAL
Floating
2406µm x 2935µm (95 mils x 116 mils)
Thickness: 483µm ±25µm (19mils ±1 mil)
ADDITIONAL INFORMATION
WORST CASE CURRENT DENSITY
Interface Materials
5
2
< 2 x 10 A/cm
GLASSIVATION
Type: Nitrox
Thickness: 15kÅ
Metallization Mask Layout
-IN_A
OUT_A
OUT_D
-IN_D
+IN_A
+IN_D
PLACE HOLDER
V+
V-
+IN_B
+IN_C
-IN_B
-IN_C
OUT_C
OUT_B
FN8653 Rev.3.00
Nov 21, 2019
Page 19 of 23
ISL70419SEH, ISL73419SEH
TABLE 1. DIE LAYOUT X-Y COORDINATES
X
(µm)
Y
(µm)
dX
(µm)
dY
(µm)
BOND WIRES
PER PAD
PAD NAME
OUT_A
-IN_A
PAD NUMBER
3
4
-445.5
-815
1308.5
1308.5
1092
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+IN_A
V+
5
-1040.5
-1044
-1040.5
-815
9
0
+IN_B
-IN_B
13
14
15
16
17
18
22
26
1
-1092
-1308.5
-1308.5
-1308.5
-1308.5
-1092
0
OUT_B
OUT_C
-IN_C
-445.5
445.5
815
+IN_C
V-
1040.5
1044
+IN_D
-IN_D
OUT_D
1040.5
815
1092
1308.5
1308.5
2
445.5
NOTE:
9. Origin of coordinates is the center of die.
FN8653 Rev.3.00
Nov 21, 2019
Page 20 of 23
ISL70419SEH, ISL73419SEH
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to web to make sure you have the latest Revision.
DATE
REVISION
FN8653.3
CHANGE
Nov 21, 2019
Added the ISL73419SEH to the datasheet.
Updated the rad levels on Features list and included rad levels in the Ordering Information table.
Added Note 3.
Updated figures 39 and 40.
Oct 15, 2018
Jul 11, 2014
FN8653.2
FN8653.1
Updated Related Literature section.
Updated Ordering Information table.
Added Notes 3 and 4.
Removed Pb-Free Reflow reference as it is not applicable to this type of package.
Removed About Intersil section.
Updated disclaimer and moved to end of document.
Modified in Features on page 1
2
SEL/SEB LET (VS = ±36V). . . . . . . . . 86.4MeV•cm /mg
TH
to
2
SEB LET (VS = ±18V). . . . . . . . . 86.4MeV•cm /mg
TH
Added in Features on page 1
"SEL Immune (SOI Process)"
under in the radiation environment section
Jun 24, 2014
FN8653.0
Initial Release
FN8653 Rev.3.00
Nov 21, 2019
Page 21 of 23
ISL70419SEH, ISL73419SEH
For the most recent package outline drawing, see K14.C.
Package Outline Drawing
K14.C
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Rev 0, 9/12
A
A
0.050 (1.27 BSC)
PIN NO. 1
ID AREA
0.390 (9.91)
0.376 (9.55)
1
TOP VIEW
0.022 (0.56)
0.015 (0.38)
0.005 (0.13)
MIN
3
0.115 (2.92)
0.009 (0.23)
0.004 (0.10)
-D-
0.045 (1.14)
0.085 (2.16)
5
0.260 (6.60)
0.248 (6.30)
0.026 (0.66)
-H-
0.370 (9.40)
0.270 (6.86)
0.03 (0.76) MIN
-C-
0.183 (4.65)
0.167 (4.24)
BOTTOM
METAL
6
SEATING AND
BASE PLANE
SIDE VIEW
BOTTOM METAL
0.005 (0.127) REF.
OFFSET FROM
CERAMIC EDGE
OPTIONAL
PIN 1 INDEX
BOTTOM VIEW
NOTES:
Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark.
1.
0.006 (0.15)
0.004 (0.10)
LEAD FINISH
2. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
3. Measure dimension at all four corners.
0.009 (0.23)
0.004 (0.10)
BASE
METAL
4. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
0.019 (0.48)
0.015 (0.38)
5. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
0.0015 (0.04)
MAX
0.022 (0.56)
0.015 (0.38)
6. The bottom of the package is a solderable metal surface.
7. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
8. Dimensions: INCH (mm). Controlling dimension: INCH.
2
SECTION A-A
FN8653 Rev.3.00
Nov 21, 2019
Page 22 of 23
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INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible
for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)
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(Rev.1.0 Mar 2020)
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Contact Information
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