5962L1322002V9A [RENESAS]
Adjustable Positive LDO Regulator;
| 型号： | 5962L1322002V9A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Adjustable Positive LDO Regulator |
| 文件： | 总20页 (文件大小：948K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL75052SEH, ISL73052SEH
1.5A, Radiation Hardened, Positive, High Voltage LDO
FN8456
Rev.7.00
Feb 11, 2019
The ISL75052SEH and ISL73052SEH are radiation hardened,
single output LDOs specified for an output current of 1.5A. The
devices operate from an input voltage range of 4.0V to 13.2V
and provide for output voltages of 0.6V to 12.7V. The output is
adjustable based on a resistor divider setting. Dropout
Features
• DLA SMD 5962-13220
• Input supply range 4.0V to 13.2V
• Output current up to 1.5A at T = +150°C
J
voltages as low as 75mV (at 0.5A) typical can be realized using
the devices. This allows you to improve the system efficiency
• Best in class accuracy ±1.5%
by lowering V to nearly V
.
- Over line, load ,and temperature
IN OUT
The ENABLE feature allows the part to be placed into a low
shutdown current mode of 165µA (typical). When enabled, the
device operates with a low ground current of 11mA (typical),
which provides for operation with low quiescent power
consumption.
• Ultra low dropout:
- 75mV dropout (typical) at 0.5A
- 225mV dropout (typical) at 1.5A
• Noise of 100µV
(typical) between 300Hz to 300kHz
RMS
• SET mitigation with no added filtering/diodes
• Shutdown current of 165µA (typical)
• Externally adjustable output voltage
• PSRR 65dB (typical) at 1kHz
These devices have superior transient response and are
designed keeping single event effects in mind. This results in
reduction of the magnitude of SET seen on the output. There is
no need for additional protection diodes and filters.
A COMP pin is provided to enable the use of external
compensation. This is achieved by connecting a resistor and
capacitor from COMP to ground. The device is stable with
tantalum capacitors as low as 47µF (KEMET T525 series) and
provides excellent regulation all the way from no load to full
load. The programmable soft-start allows you to program the
inrush current by means of the decoupling capacitor used on
the BYP pin. The OCP pin allows the short-circuit output current
limit threshold to be programmed by means of a resistor from
OCP pin to GND. The OCP setting range is from 0.16A
minimum to 3.2A maximum. The resistor sets the constant
current threshold for the output under fault conditions. The
thermal shutdown disables the output if the device
• ENable and PGood feature
• Programmable soft-start/inrush current limiting
• Adjustable overcurrent protection
• Over-temperature shutdown
• Stable with 47µF minimum tantalum capacitor
• 16 Ld flatpack package
• Radiation environment
- High dose rate (50-300rad(Si)/s) . . . . . . . . . . . 100krad(Si)
(ISL75052SEH only)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . . . 50krad(Si)*
temperature exceeds the specified value. It subsequently
enters an ON/OFF cycle until the fault is removed.
2
- SET/SEL/SEB . . . . . . . . . . . . . . . . . . . . . . 86MeV•cm /mg
*See TID report for further characterization details.
Applications
• LDO regulator for space power systems
• DSP, FPGA, and µP core power supplies
• Post regulation of SMPS and down-hole drilling
Related Literature
For a full list of related documents, visit our web page:
• ISL75052SEH, ISL73052SEH device pages
EN
0.30
ISL7x052SEH
VIN
0.25
0.20
0.15
0.10
0.05
0.00
+150°C
VIN
VOUT 1, 2
3, 4, 5
+125°C
200µF 0.1µF
16
8
BYP
OCP
VCCX
PG
ADJ
EN
VOUT
2.5V
15
14
13
12
+25°C
9
GND
COMP
0.1µF 200µF
10
15.8k
4.87k
2.2k
2.2n
0.1µF 0.1µF 300
22k
VIN
1nF
22k
0
0.5
1.0
1.5
2.0
PG
I
(A)
LOAD
FIGURE 2. DROPOUT vs I
FIGURE 1. TYPICAL APPLICATION
OUT
FN8456 Rev.7.00
Feb 11, 2019
Page 1 of 20
ISL75052SEH, ISL73052SEH
Block Diagram
COMP
OCP
3.8V
LDO
VIN
VCCX
CURRENT
LIMIT
+
-
600mV
BYP
REFERENCE
BIAS
VOUT
POWER
PDMOS
THERMAL
SHUTDOWN
EN
UVLO
ADJ
PG
-
DELAY
540mV
+
GND
FIGURE 3. BLOCK DIAGRAM
Typical Application
EN
ISL7x052SEH
1
2
VOUT
VOUT
VIN
16
15
14
BYP
ADJ
EN
0.1µF
3
4
5
6
7
8
VIN
VIN
GND 13
COMP 12
GND 11
PG 10
VCCX
VIN
22k
10k
0.1µF
100µF 100µF
1nF
NC
PG
NC
VOUT = 2.5V
300
OCP
VCCX
9
15.8k
4.87k
2.2k
0.1µF 100µF 100µF
NC = NO CONNECT PIN CAN BE
CONNECTED TO EITHER VIN OR GND
2.2nF
0.1µF
FIGURE 4. TYPICAL APPLICATION
FN8456 Rev.7.00
Feb 11, 2019
Page 2 of 20
ISL75052SEH, ISL73052SEH
Ordering Information
ORDERING SMD NUMBER
PART NUMBER
(Note 1)
PACKAGE
(RoHS COMPLIANT)
(Note 2)
TEMP RANGE (°C)
-55 to +125
PKG DWG. #
K16.E
5962R1322001VXC
ISL75052SEHVFE
ISL75052SEHVX
16 Ld CDFP
5962R1322001V9A
-55 to +125
Die
N/A
ISL75052SEHX/SAMPLE (Note 3)
ISL75052SEHFE/PROTO (Note 3)
ISL73052SEHVFE
-55 to +125
Die Sample
16 Ld CDFP
16 Ld CDFP
Die
N/A
-55 to +125
K16.E
K16.E
5962L1322002VXC
-55 to +125
5962L1322002V9A
ISL73052SEHVX
-55 to +125
N/A
N/A
ISL73052SEHFE/PROTO (Note 3)
ISL73052SEHX/SAMPLE (Note 3)
ISL75052SEHEVAL1Z (Note 4)
-55 to +125
Die Sample
16 Ld CDFP
-55 to +125
K16.E
N/A
Evaluation Board
NOTES:
1. These Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb
and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed must be
used when ordering.
3. The /PROTO and /SAMPLE are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity. These parts are intended for
engineering evaluation purposes only. The /PROTO parts meet the electrical limits and conditions across temperature specified in the DLA SMD and
are in the same form and fit as the qualified device. The /SAMPLE parts are capable of meeting the electrical limits and conditions specified in the
DLA SMD at +25°C only. The /SAMPLE parts do not receive 100% screening across temperature to the DLA SMD electrical limits. These part types
do not come with a Certificate of Conformance because they are not DLA qualified devices.
4. Evaluation boards use the /PROTO parts and /PROTO parts are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity.
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER
RADIATION HARDENED ASSURANCE TESTING
ISL75052SEH
ISL73052SEH
HDR to 100krad(Si)
LDR to 50krad(Si)
LDR to 50krad(Si)
FN8456 Rev.7.00
Feb 11, 2019
Page 3 of 20
ISL75052SEH, ISL73052SEH
Pin Configuration
16 LD CDFP
TOP VIEW
VOUT
VOUT
VIN
1
2
3
4
5
6
7
8
16
BYP
ADJ
EN
15
14
13
12
11
10
9
VIN
GND
VIN
COMP
TMODE
NC
NC
PG
OCP
VCCX
DOTTED LINE SHOWS METAL BOTTOM
Pin Descriptions
PIN NUMBER
PIN NAME
VOUT
VIN
DESCRIPTION
ESD CIRCUIT
Circuit 1
Circuit 1
Circuit 2
Circuit 2
Circuit 2
1, 2
3, 4, 5
6, 7
8
Output voltage pins
Input supply pins
NC
No connect. May be grounded if needed.
OCP
OCP pin allows the current limit to be programmed with an external resistor.
9
VCCX
The 3.8V internal bus is pinned out to accept a decoupling capacitor. Connect a 0.1µF
ceramic capacitor from VCCX pin to GND.
10
PG
This pin is logic high when V
in regulation.
is in regulation signal. A logic low defines when V
OUT
is not
Circuit 2
OUT
11
12
13
14
15
16
TMODE
COMP
GND
EN
Test Mode pin, must be connected to GND.
Circuit 2
Circuit 2
Circuit 2
Circuit 2
Circuit 2
Circuit 2
Circuit 2
Add compensation capacitor and resistor between COMP and GND.
GND pin. Pin 13 is also connected to the metal lid of the package.
V
independent chip enable. TTL and CMOS compatible.
IN
ADJ
ADJ pin allows V
to be programmed with an external resistor divider.
OUT
BYP
Connect a 0.1µF capacitor from BYP pin to GND, to filter the internal VREF.
Bottom Metalization The metal surface on the bottom surface of the package is floating. For mounting
instructions see “Bottom Metal Mounting Guidelines” on page 15.
PAD
PAD
ESD_CL_12V
ESD_RC_7V
GND
GND
ESD CIRCUIT 1
ESD CIRCUIT 2
FN8456 Rev.7.00
Feb 11, 2019
Page 4 of 20
ISL75052SEH, ISL73052SEH
Absolute Maximum Ratings
Thermal Information
VIN Relative to GND Without Ion Beam (Note 5) . . . . . . . . . -0.3 to +16.0V
VIN Relative to GND Under Ion Beam (Note 5) . . . . . . . . . . . -0.3 to +14.7V
VOUT Relative to GND (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +14.7V
PG, EN, OCP/ADJ, COMP, REFIN,
Thermal Resistance (Typical)
16 Ld CDFP Package (Notes 8, 9) . . . . . . .
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
(°C/W)
26
(°C/W)
4.5
JA
JC
Junction Temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
J
REFOUT Relative to GND (Note 5). . . . . . . . . . . . . . . . . . . -0.3 to +6.5V
ESD Rating
DC
Radiation Information
Maximum Total Dose
High Dose (Dose Rate = 50-300radSi/s). . . . . . . . . . . . . . . 100krads (Si)
Low Dose (Dose Rate = 10mradSi/s) (Note 7) . . . . . . . . . . 100krads (Si)
Human Body Model (Tested per MIL-PRF-883 3015.7). . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 750V
SET (V
within ±5% During Events) . . . . . . . . . . . . . . . 86MeV•cm2/mg
SEL/B (No Latch-Up/Burnout). . . . . . . . . . . . . . . . . . . . . . 86MeV•cm2/mg
OUT
Recommended Operating Conditions (Note 6)
Ambient Temperature Range (T ) . . . . . . . . . . . . . . . . . . .-55°C to +125°C
A
The output capacitance used for SEE testing is 2x100µF for C and C
100nF for BYPASS.
,
IN
OUT
Junction Temperature (T ) (Note 5). . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
J
VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0V to 13.2V
VOUT Range (Note 11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.6V to 12.7V
PG, EN, OCP/ADJ Relative to GND . . . . . . . . . . . . . . . . . . . . . . . .0V to +5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. Extended operation at these conditions may compromise reliability. Exceeding these limits results in damage. Recommended operating conditions
define limits where specifications are established.
6. Refer to “Bottom Metal Mounting Guidelines” on page 15.
7. Product capability established by initial characterization. The “EH” version is acceptance tested on a wafer-by-wafer basis to 50krad(Si) at low dose rate.
8. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See TB379.
JA
9. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
10. Electromigration specification defined as lifetime average junction temperature of +150°C where maximum rated DC current = lifetime average
current.
11. SET performance of ±5% applies to V
OUT
≥ 2.5V. For V <2.5V SEE testing needs to be performed to ensure system SET goals are met.
OUT
Electrical Specifications Unless otherwise noted, V = V
+ 0.5V, V
= 4.0V, C = C
= 2x100µF 60mΩ, KEMET type
IN
OUT OUT
IN OUT
T541X107N025AH or equivalent, T = +25°C, I = 0A. Applications must follow thermal guidelines of the package to determine worst case junction
J
L
temperature. Please refer to “Applications Information” on page 15 and TB379. Boldface limits apply across the operating temperature range, -55°C to
+125°C. Pulse load techniques used by ATE to ensure T = T defines established limits.
J
A
MIN
MAX
PARAMETER
DC CHARACTERISTICS
DC Output Voltage Accuracy
SYMBOL
TEST CONDITIONS
(Note 12) TYP (Note 12) UNIT
V
V resistor adjust to: 2.5V and 5.0V
OUT
OUT
V
= 2.5V, 4.0V < V < 5.0V; 0A < I
< 1.5A,
< 1.5A,
< 1.5A,
< 1.5A,
-1.5
-2.0
-1.5
-2.0
0.2
0.2
0.2
0.2
1.5
2.0
1.5
2.0
%
%
%
%
OUT
IN
LOAD
LOAD
LOAD
LOAD
T = -55°C to +125°C
J
V
= 2.5V, 4.0V < V < 5.0V; 0A < I
IN
OUT
T = +25°C, post radiation
J
V
= 5.0V, 5.5V < V < 6.9V; 0A < I
IN
OUT
T = -55°C to +125°C
J
V
= 5.0V, 5.5V < V < 6.9V, 0A < I
IN
OUT
T = +25°C, post radiation
J
V
OUT
resistor adjust to: 10.0V
= 10.0V, 10.5V < V < 13.2V, I
V
= 0A,
= 0A,
-1.5
-2.0
-1.5
-2.0
0.2
0.2
0.2
0.2
1.5
2.0
1.5
2.0
%
%
%
%
OUT
T = -55°C to +125°C
IN
LOAD
J
V
= 10.0V, 10.5V < V < 13.2V, I
IN
OUT
T = +25°C, post radiation
LOAD
J
V
V
= 10.0V, V = 10.5V, I
IN LOAD
= 1.5A,
OUT
= 13.2V, I
= 1.0A, T = -55°C to +125°C
IN
LOAD
J
V
= 10.0V, V = 10.5V; I
= 1.5A, V = 13.2V,
IN
OUT
IN LOAD
I
= 1.0A, T = +25°C, post radiation
LOAD
J
FN8456 Rev.7.00
Feb 11, 2019
Page 5 of 20
ISL75052SEH, ISL73052SEH
Electrical Specifications Unless otherwise noted, V = V
+ 0.5V, V
= 4.0V, C = C = 2x100µF 60mΩ, KEMET type
IN OUT
IN
OUT OUT
T541X107N025AH or equivalent, T = +25°C, I = 0A. Applications must follow thermal guidelines of the package to determine worst case junction
J
L
temperature. Please refer to “Applications Information” on page 15 and TB379. Boldface limits apply across the operating temperature range, -55°C to
+125°C. Pulse load techniques used by ATE to ensure T = T defines established limits. (Continued)
J
A
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 12) TYP (Note 12) UNIT
VCCX Pin
ADJ Pin
ADJ Pin
BYP Pin
V
T = -55°C to +125°C; 4V < V < 13.2V; I
= 0A
3.7
591
588
588
3.9
600
600
600
4.1
609
612
612
V
VCCX
J
IN
LOAD
V
T = -55°C to +125°C
mV
mV
mV
ADJ
J
V
T = 25°C, post radiation
J
ADJ
V
4.0V < V < 13.2V; I
IN
= 0A,
BYP
LOAD
T = -55°C to +125°C
J
DC Input Line Regulation
4.0V < V < 13.2V, V
IN
= 2.5V
= 5.0V
1
1
8
mV
mV
mV
mV
mV
mV
µA
OUT
5.5V < V < 13.2V, V
IN
20
OUT
10.5V < V < 13.2V, V
IN OUT
= 10.0V
1
10
DC Output Load Regulation
V
V
V
= 2.5V; 0A < I
= 5.0V; 0A < I
< 1.5A, V = 4.0V
IN
0.3
1.3
0.1
9.0
18.0
36.0
1
OUT
OUT
OUT
LOAD
LOAD
< 1.5A, V = 5.5V
IN
< 1.5A, V = 10.5V
= 10.0V; 0A < I
= 0.6V
LOAD
IN
ADJ Input Current
Ground Pin Current
V
ADJ
I
V
= 2.5V; I
= 2.5V; I
= 0A, 4.0V < V < 13.2V
IN
6
8
10
mA
mA
mA
mA
µA
Q
OUT
OUT
OUT
OUT
LOAD
LOAD
V
V
V
= 1.5A, 4.0V < V < 13.2V
IN
12
= 10.0V, I
= 0A, 11.0V < V < 13.2V
IN
15
20
LOAD
LOAD
= 10.0V, I
= 1.5A, 11.0V < V < 13.2V
IN
20
25
Ground Pin Current in Shutdown
Ground Pin Current in Shutdown
Dropout Voltage (Note 14)
I
ENABLE pin = 0V, V = 4.0V
IN
70
120
300
160
300
400
0.32
SHDNL
I
ENABLE pin = 0V, V = 13.2V
IN
165
75
µA
SHDNH
V
I
I
I
= 0.5A, V
= 1.0A, V
= 1.5A, V
= 3.6V and 12.7V
= 3.6V and 12.7V
= 3.6V and 12.7V
mV
mV
mV
A
DO
LOAD
LOAD
LOAD
OUT
OUT
OUT
150
225
0.24
Output Short-Circuit Current for
16 Ld CDFP
ISCL
ISCH
TSD
V
SET = 4.0V, V
OUT
+ 0.5V < V < 13.2V,
IN
0.16
1.6
OUT
R
= 3k, (Note 16)
SET
Output Short-Circuit Current for
16 Ld CDFP
V
SET = 4.0V, V
OUT
+ 0.5V < V < 13.2V,
IN
2.4
3.2
196
25
A
OUT
R
= 300Ω, (Note 16)
SET
Thermal Shutdown Temperature
(Note 13)
V
+ 0.5V < V < 13.2V
IN
154
175
°C
°C
OUT
Thermal Shutdown Hysteresis
(Rising Threshold) (Note 13)
TSDn
V
+ 0.5V < V < 13.2V
IN
OUT
AC CHARACTERISTICS
Input Supply Ripple Rejection
(Note 13)
PSRR
PSRR
PSRR
PM
V
V
= 300mV, f = 1kHz, I
= 1.5A;
55
60
40
50
10
65
70
50
dB
dB
dB
°
P-P
IN
LOAD
= 4.9V, V
= 4.0V
OUT
Input Supply Ripple Rejection
(Note 13)
V
V
= 300mV, f = 120Hz, I
= 5mA;
LOAD
P-P
IN
= 4.9V, V
= 2.5V
OUT
Input Supply Ripple Rejection
(Note 13)
V
V
= 300mV, f = 100kHz, I
= 1.5A;
LOAD
P-P
IN
= 4.9V, V
= 4.0V
OUT
Phase Margin (Note 13)
V
= 2.5V, 4.0V and 10V, C
= 2x100µF, R
= 22k,
= 22k,
OUT
OUT
OUT
COMP
C
= 1nF
COMP
Gain Margin (Note 13)
GM
V
= 2.5V, 4.0V and 10V C
= 2x100µF, R
dB
OUT
COMP
C
= 1nF
COMP
Output Noise Voltage (Note 13)
V
= 4.1V, V
= 2.5V, I
= 10mA, BW = 100Hz < f < 100kHz,
100
µV
RMS
IN
OUT
LOAD
BYPASS to GND capacitor = 0.2µF
FN8456 Rev.7.00
Feb 11, 2019
Page 6 of 20
ISL75052SEH, ISL73052SEH
Electrical Specifications Unless otherwise noted, V = V
+ 0.5V, V
= 4.0V, C = C = 2x100µF 60mΩ, KEMET type
IN OUT
IN
OUT OUT
T541X107N025AH or equivalent, T = +25°C, I = 0A. Applications must follow thermal guidelines of the package to determine worst case junction
J
L
temperature. Please refer to “Applications Information” on page 15 and TB379. Boldface limits apply across the operating temperature range, -55°C to
+125°C. Pulse load techniques used by ATE to ensure T = T defines established limits. (Continued)
J
A
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 12) TYP (Note 12) UNIT
DEVICE START-UP CHARACTERISTICS
Enable Pin Characteristics
Turn-On Threshold
4.0V < V < 13.2V
IN
0.5
0.8
1.2
1
V
Enable Pin Leakage Current
Enable Pin Propagation Delay
V
= 13.2V, EN = 5.5V
µA
ms
IN
V
= 4.5V, V
OUT
= 4.0V, I
= 1.5A,
= 1.5A,
0.5
1.4
1.1
170
1.0
IN
LOAD
LOAD
(EN step 1.2V to V
= 100mV)
C
= 22µF, C
= 0.2µF
OUT
OUT
BYP
= 4.0V, I
Enable Pin Turn-On Delay
(EN step 1.2V to PGOOD)
V
= 4.5V, V
3.0
2.5
ms
ms
mV
IN
OUT
= 2x100µF, C
C
= 0.2µF
OUT
BYP
= 4.0V, I
Enable Pin Turn-On Delay
(EN step 1.2V to PGOOD)
V
= 4.5V, V
= 1.5A,
IN
OUT
LOAD
= 0.2µF
BYP
C
= 22µF, C
OUT
4.0V < V < 13.2V
Hysteresis (Falling Threshold)
PG Pin Characteristics
75
IN
V
V
V
Error Flag Rising Threshold
Error Flag Falling Threshold
Error Flag Hysteresis
83
80
88
86
2.50
5
94
91
%V
OUT
OUT
OUT
OUT
OUT
OUT
%V
%V
1.75
Error Flag Low Voltage
Error Flag Low Voltage
Error Flag Leakage Current
NOTES:
I
= 1mA
100
400
1
mV
SINK
I
= 10mA
5
mV
µA
SINK
V
= 13.2V, PG = 5.5V
IN
12. Parameters with bold face MIN and/or MAX limits are 100% tested at -55°C, +25°C and +125°C.
13. Limits established by characterization and are not production tested.
14. Dropout is defined by the difference in supply V and V
IN OUT
when the supply produces a 2% drop in V from its nominal value.
OUT
15. Refer to thermal package guidelines in “Bottom Metal Mounting Guidelines” on page 15.
16. OCP recovery overshoot should be within ±4% of the nominal V set point.
OUT
17. SET performance of <±5% at LET = 86MeV•cm2/mg has been evaluated at V
0.1µF CDR04 X7R capacitor. Capacitor on BYP = 0.1µF CDR04 X7R.
= >2.5V with C = C
IN
= 2x100µF 10V 60mΩ in parallel with
OUT
OUT
High Dose Rate Post Radiation Characteristics
T = +25°C, unless otherwise noted. This data is typical test data post
A
radiation exposure at a rate of 50 to 300rad(Si)/s (ISL75052SEH only). This data is intended to show typical parameter shifts due to high dose rate
radiation (Note 18). These are not limits nor are they guaranteed.
ITEM#
DESCRIPTION
Enable Pin Leakage Current
TEST CONDITIONS
= 13.2V, EN = 0V
0k RAD 100k RAD UNIT
1
2
V
V
-0.0375
-0.0006
-0.0007
68.0
-0.0409
0.0005
-0.0010
67.5
µA
µA
µA
µA
µA
V
IN
Enable Pin Leakage Current
ADJ Input Current
Ground Pin Current in Shutdown
Ground Pin Current in Shutdown
ADJ Pin
= 13.2V, EN = 5.5V
IN
3
VADJ = 0.6V
4
EN pin = 0V, V = 4.0V
IN
5
EN pin = 0V, V = 13.2V
162.7
163.1
IN
6
V
V
V
V
V
V
V
= 4.0V
0.60178
0.60075
3.89156
0.60489
0.60041
3.87454
IN
7
BYP Pin
= 4.0V; I
= 4.0V; I
= 13.2V
= 0A
= 0A
V
IN
LOAD
8
VCCX Pin
V
IN
LOAD
9
ADJ Pin
0.60183 0.60495
0.60105 0.60069
3.89260 3.87503
V
IN
10
11
12
BYP Pin
= 13.2V; I
= 13.2V; I
= 0A
V
IN
LOAD
LOAD
VCCX Pin
= 0A
V
IN
DC Output Voltage Accuracy
= 2.5V, V = 4.0V; I
IN
= 0A, T = +25°C
2.51591
2.52880
V
OUT
LOAD
A
FN8456 Rev.7.00
Feb 11, 2019
Page 7 of 20
ISL75052SEH, ISL73052SEH
High Dose Rate Post Radiation Characteristics
T = +25°C, unless otherwise noted. This data is typical test data post
A
radiation exposure at a rate of 50 to 300rad(Si)/s (ISL75052SEH only). This data is intended to show typical parameter shifts due to high dose rate
radiation (Note 18). These are not limits nor are they guaranteed. (Continued)
ITEM#
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DESCRIPTION
DC Output Voltage Accuracy
TEST CONDITIONS
0k RAD 100k RAD UNIT
V
V
V
= 2.5V, V = 4.0V; I
IN
= 1.5A, = +25°C
2.51606
2.51601
2.51613
0.41881
2.52893
2.52879
2.52894
0.43023
V
OUT
OUT
OUT
LOAD
LOAD
LOAD
DC Output Voltage Accuracy
DC Output Voltage Accuracy
DC Input Line Regulation
DC Output Load Regulation
DC Output Voltage Accuracy
DC Output Voltage Accuracy
DC Output Voltage Accuracy
DC Output Voltage Accuracy
DC Input Line Regulation
DC Output Load Regulation
DC Output Voltage Accuracy
DC Output Voltage Accuracy
DC Output Voltage Accuracy
DC Output Voltage Accuracy
DC Input Line Regulation
DC Output Load Regulation
Ground Pin Current
= 2.5V, V = 5.0V; I
IN
= 0A, = +25°C
V
= 2.5V, V = 5.0V; I
IN
= 1.5A, = +25°C
V
4.0V < V < 13.2V, V
IN
= 2.5V
mV
mV
V
OUT
V
V
V
V
V
= 2.5V; 0A < I
< 1.5A, V = 4.0V
IN
0.15429 0.13063
5.02291 5.04849
5.02425 5.04984
5.02298 5.04900
OUT
OUT
OUT
OUT
OUT
LOAD
= 5.0V, V = 5.5V; I
IN
= 0A, = +25°C
= 1.5A, = +25°C
= 0A, = +25°C
= 1.5A, = +25°C
LOAD
LOAD
LOAD
LOAD
= 5.0V, V = 5.5V; I
IN
V
= 5.0V, V = 6.9V; I
IN
V
= 5.0V, V = 6.9V; I
IN
5.02425
0.43559
5.05003
0.71168
V
5.5V < V < 13.2V, V
IN
= 5.0V
mV
mV
V
OUT
V
V
V
V
V
= 5.0V; 0A < I
< 1.5A, V = 5.5V
IN
1.34488 1.34957
10.05084 10.10237
10.04956 10.10146
10.05112 10.10158
10.05334 10.10470
0.28300 -0.78996
-1.28285 -0.90861
OUT
OUT
OUT
OUT
OUT
LOAD
= 10.0V, V = 10.5V; I
IN
= 0A, = +25°C
= 1.5A, = +25°C
= 0A, = +25°C
= 1.5A, = +25°C
LOAD
LOAD
LOAD
LOAD
= 10.0V, V = 10.5V; I
IN
V
= 10.0V, V = 13.2V; I
IN
V
= 10.0V, V = 13.2V; I
IN
V
10.5V < V < 13.2V, V
IN
= 10.0V
mV
mV
mA
mA
mA
mA
mA
mA
mA
mA
mV
mV
mV
mV
mV
mV
µA
mV
mV
%
OUT
V
V
V
V
V
V
V
V
V
= 10.0V; 0A < I
< 1.5A, V = 10.5V
IN
OUT
OUT
LOAD
= 2.5V; I
= 2.5V; I
= 2.5V; I
= 2.5V; I
= 0A, V = 4.0V
IN
5.4
7.1
5.3
7.1
LOAD
LOAD
LOAD
LOAD
Ground Pin Current
= 1.5A, V = 4.0V
IN
OUT
Ground Pin Current
= 0A, V = 13.2V
IN
5.6
5.6
OUT
Ground Pin Current
= 1.5A, V = 13.2V
IN
5.6
5.6
OUT
Ground Pin Current
= 10.0V; I
= 10.0V; I
= 10.0V; I
= 10.0V; I
= 0A, V = 4.0V
IN
13.5
13.4
OUT
LOAD
LOAD
LOAD
LOAD
Ground Pin Current
= 1.5A, V = 4.0V
IN
13.8
13.8
OUT
Ground Pin Current
= 0A, V = 13.2V
IN
11.7
11.7
OUT
Ground Pin Current
= 1.5A, V = 13.2V
IN
13.3
13.6
OUT
Dropout Voltage
I
I
I
I
I
I
= 0.5A, V
= 1.0A, V
= 1.5A, V
= 0.5A, V
= 1.0A, V
= 1.5A, V
= 3.6V
63.79
130.74
200.22
67.06
133.59
202.13
-0.0404
2.74
65.87
134.93
205.87
69.05
137.09
207.74
-0.0108
2.69
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
OUT
OUT
OUT
OUT
OUT
OUT
Dropout Voltage
= 3.6V
Dropout Voltage
= 3.6V
Dropout Voltage
= 12.7V
= 12.7V
= 12.7V
Dropout Voltage
Dropout Voltage
Error Flag Leakage Current
Error Flag Low Voltage
Error Flag Low Voltage
V
= 13.2V, PG = 5.5V
IN
I
= 1mA
= 10mA
= 13.2V
= 13.2V
= 13.2V
= 4.0V
SINK
I
2.95
2.89
SINK
V
V
V
V
Error Flag Rising Threshold
Error Flag Falling Threshold
Error Flag Hysteresis
V
V
V
V
88.6
88.0
OUT
OUT
OUT
OUT
IN
IN
IN
IN
86.1
85.5
%
2.5
2.5
%
Error Flag Rising Threshold
88.5
87.9
%
FN8456 Rev.7.00
Feb 11, 2019
Page 8 of 20
ISL75052SEH, ISL73052SEH
High Dose Rate Post Radiation Characteristics
T = +25°C, unless otherwise noted. This data is typical test data post
A
radiation exposure at a rate of 50 to 300rad(Si)/s (ISL75052SEH only). This data is intended to show typical parameter shifts due to high dose rate
radiation (Note 18). These are not limits nor are they guaranteed. (Continued)
ITEM#
51
DESCRIPTION
Error Flag Falling Threshold
Error Flag Hysteresis
TEST CONDITIONS
0k RAD 100k RAD UNIT
V
V
V
V
V
V
V
V
V
= 4.0V
86.0
2.5
85.4
2.5
%
%
OUT
IN
IN
IN
IN
IN
IN
IN
52
= 4.0V
OUT
53
Turn-On Threshold (Rising)
Hysteresis
= 4.0V
0.930
163.8
0.981
188.6
483.9
0.928
163.3
0.975
186.6
489.4
V
54
= 4.0V
mV
V
55
Turn-On Threshold (Rising)
Hysteresis
= 13.2V
= 13.2V
= 4.5V, V
56
mV
µs
57
Enable Pin Propagation Delay (EN step 1.2V to
= 4.0V, I
= 4.0V, I
= 1.5A, C
= 1.5A, C
= 22μF,
= 22μF,
OUT
LOAD
LOAD
LOAD
OUT
OUT
OUT
V
= 100mV)
C
= 0.2μF
OUT
BYP
58
59
Enable Pin Turn-On Delay (EN step 1.2V to PGOOD)
Enable Pin Turn-On Delay (EN step 1.2V to PGOOD)
V
= 4.5V, V
1007.6
1312.8
984.1
µs
µs
IN
OUT
= 0.2μF
C
BYP
V
= 4.5V, V
= 4.0V, I
= 1.5A, C
= 2x100μF,
1319.1
IN
OUT
CBYP = 0.2μF
60
61
62
63
Output Short-Circuit Current
Output Short-Circuit Current
Output Short-Circuit Current
Output Short-Circuit Current
V
V
V
V
= 4.0V, V = 4.5V, R
IN
= 3k
0.235
0.240
2.524
2.538
0.234
0.239
2.526
2.540
A
A
A
A
OUT
OUT
OUT
OUT
SET
= 4.0V, V = 13.2V, R
= 3k
= 300
IN SET
= 4.0V, V = 4.5V, R
IN
SET
= 4.0V, V = 13.2V, R
= 300
IN SET
Low Dose Rate Post Radiation Characteristics
T = +25°C, unless otherwise noted. This data is typical test data post
A
radiation exposure at a rate of 10mrad(Si)/s. This data is intended to show typical parameter shifts due to low dose rate radiation (Note 18). These are
not limits nor are they guaranteed (applies only to ISL75052SEH initial LDR characterization).
ITEM#
1
DESCRIPTION
Enable Pin Leakage Current
Enable Pin Leakage Current
ADJ Input Current
TEST CONDITIONS
0k RAD
-0.0390
-0.0010
-0.0115
68.8
50k RAD
-0.0298
0.0092
UNIT
µA
µA
µA
µA
µA
V
V
V
= 13.2V, EN = 0V
IN
2
= 13.2V, EN = 5.5V
= 0.6V
IN
3
V
-0.0070
65.1
ADJ
4
Ground Pin Current in Shutdown
Ground Pin Current in Shutdown
ADJ Pin
ENABLE Pin = 0V, V = 4.0V
IN
ENABLE Pin = 0V, V = 13.2V
5
163.4
159.9
IN
6
V
V
V
V
V
V
V
V
V
V
= 4.0V
0.60162
0.60019
3.88673
0.60168
0.60049
3.88770
2.51577
2.51596
2.51598
2.51611
0.51044
0.19541
5.02321
5.02434
5.02324
5.02443
0.10020
1.13716
0.60174
0.60048
3.88170
0.60179
0.60057
3.88246
2.51488
2.51508
2.51504
2.51520
0.44539
0.20233
5.02138
5.02257
5.02155
5.02267
0.16807
1.19041
IN
7
BYP Pin
= 4.0V; I
= 4.0V; I
= 13.2V
= 0A
= 0A
V
IN
LOAD
8
VCCX Pin
V
IN
LOAD
9
ADJ Pin
V
IN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
BYP Pin
= 13.2V; I
= 13.2V; I
= 0A
V
IN
LOAD
LOAD
VCCX Pin
= 0A
V
IN
DC Output Voltage Accuracy
DC Output Voltage Accuracy
DC Output Voltage Accuracy
DC Output Voltage Accuracy
DC Input Line Regulation
DC Output Load Regulation
DC Output Voltage Accuracy
DC Output Voltage Accuracy
DC Output Voltage Accuracy
DC Output Voltage Accuracy
DC Input Line Regulation
DC Output Load Regulation
= 2.5V, V = 4.0V; I
IN
= 0A, T = +25°C
V
OUT
OUT
OUT
OUT
LOAD
LOAD
LOAD
LOAD
A
= 2.5V, V = 4.0V; I
IN
= 1.5A, T = +25°C
V
A
= 2.5V, V = 5.0V; I
IN
= 0A, T = +25°C
V
A
= 2.5V, V = 5.0V; I
IN
= 1.5A, T = +25°C
V
A
4.0V < V < 13.2V, V
IN
= 2.5V
mV
mV
V
OUT
V
V
V
V
V
= 2.5V; 0A < I
< 1.5A, V = 4.0V
IN
OUT
OUT
OUT
OUT
OUT
LOAD
= 5.0V, V = 5.5V; I
IN
= 0A, T = +25°C
A
LOAD
LOAD
LOAD
LOAD
= 5.0V, V = 5.5V; I
IN
= 1.5A, T = +25°C
V
A
= 5.0V, V = 6.9V; I
IN
= 0A, T = +25°
V
A
= 5.0V, V = 6.9V; I
IN
= 1.5A, T = +25°C
V
A
5.5V < V < 13.2V, V
IN
= 5.0V
mV
mV
OUT
V
= 5.0V; 0A < I
< 1.5A, V = 5.5V
IN
OUT
LOAD
FN8456 Rev.7.00
Feb 11, 2019
Page 9 of 20
ISL75052SEH, ISL73052SEH
Low Dose Rate Post Radiation Characteristics
T = +25°C, unless otherwise noted. This data is typical test data post
A
radiation exposure at a rate of 10mrad(Si)/s. This data is intended to show typical parameter shifts due to low dose rate radiation (Note 18). These are
not limits nor are they guaranteed (applies only to ISL75052SEH initial LDR characterization). (Continued)
ITEM#
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
DESCRIPTION
DC Output Voltage Accuracy
DC Output Voltage Accuracy
DC Output Voltage Accuracy
DC Output Voltage Accuracy
DC Input Line Regulation
DC Output Load Regulation
Ground Pin Current
TEST CONDITIONS
0k RAD
50k RAD
UNIT
V
V
V
V
V
= 10.0V, V = 10.5V; I
IN
= 0A, T = +25°C
10.04951 10.04602
10.04930 10.04583
10.05009 10.04631
10.05191 10.04823
OUT
OUT
OUT
OUT
LOAD
LOAD
LOAD
LOAD
A
= 10.0V, V = 10.5V; I
IN
= 1.5A, T = +25°C
V
A
= 10.0V, V = 13.2V; I
IN
= 0A, T = +25°C
V
A
= 10.0V, V = 13.2V; I
IN
= 1.5A, T = +25°C
V
A
10.5V < V < 13.2V, V
IN
= 10.0V
0.58653
-0.20163
5.5
0.29418
-0.18742
5.8
mV
mV
mA
mA
mA
mA
mA
mA
mA
mA
mV
mV
mV
mV
mV
mV
µA
mV
mV
%
OUT
V
V
V
V
V
V
V
V
V
= 10.0V; 0A < I
< 1.5A, V = 10.5V
IN
OUT
OUT
LOAD
= 2.5V; I
= 2.5V; I
= 2.5V; I
= 2.5V; I
= 0A, V = 4.0V
IN
LOAD
LOAD
LOAD
LOAD
Ground Pin Current
= 1.5A, V = 4.0V
IN
7.2
7.4
OUT
Ground Pin Current
= 0A, V = 13.2V
IN
5.6
5.9
OUT
Ground Pin Current
= 1.5A, V = 13.2V
IN
5.6
5.9
OUT
Ground Pin Current
= 10.0V; I
= 10.0V; I
= 10.0V; I
= 10.0V; I
= 0A, V = 4.0V
IN
14.0
14.3
OUT
LOAD
LOAD
LOAD
LOAD
Ground Pin Current
= 1.5A, V = 4.0V
IN
14.1
14.5
OUT
Ground Pin Current
= 0A, V = 13.2V
IN
11.9
12.3
OUT
Ground Pin Current
= 1.5A, V = 13.2V
IN
13.5
13.9
OUT
Dropout Voltage
I
I
I
I
I
I
= 0.5A, V
= 1.0A, V
= 1.5A, V
= 0.5A, V
= 1.0A, V
= 1.5A, V
= 3.6V
67.19
138.01
210.09
70.54
140.61
212.35
-0.0581
2.72
68.88
140.62
213.41
72.94
143.23
215.80
-0.0364
2.81
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
OUT
OUT
OUT
OUT
OUT
OUT
Dropout Voltage
= 3.6V
Dropout Voltage
= 3.6V
Dropout Voltage
= 12.7V
= 12.7V
= 12.7V
Dropout Voltage
Dropout Voltage
Error Flag Leakage Current
Error Flag Low Voltage
Error Flag Low Voltage
V
= 13.2V, PG = 5.5V
IN
I
I
= 1mA
= 10mA
= 13.2V
= 13.2V
= 13.2V
= 4.0V
SINK
2.92
2.97
SINK
V
V
V
V
V
V
Error Flag Rising Threshold
Error Flag Falling Threshold
Error Flag Hysteresis
V
V
V
V
V
V
V
V
V
V
88.6
88.5
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
86.0
86.0
%
2.5
2.5
%
Error Flag Rising Threshold
Error Flag Falling Threshold
Error Flag Hysteresis
88.4
88.4
%
= 4.0V
85.9
85.9
%
= 4.0V
2.5
2.5
%
Turn-On Threshold (Rising)
Hysteresis
= 4.0V
0.925
162.6
0.975
186.9
531.5
0.923
161.3
0.972
185.0
531.8
V
= 4.0V
mV
V
Turn-On Threshold (Rising)
Hysteresis
= 13.2V
= 13.2V
mV
µs
Enable Pin Propagation Delay (EN step 1.2V V = 4.5V, V
IN
= 4.0V, I
= 4.0V, I
= 1.5A, C
= 1.5A, C
= 22μF, C
= 22μF, C
=
=
OUT
OUT
OUT
LOAD
LOAD
LOAD
OUT
OUT
OUT
BYP
BYP
to V
= 100mV)
0.2μF
OUT
58
59
Enable Pin Turn-On Delay (EN step 1.2V to
PGOOD)
V
= 4.5V, V
1033.7
1297.9
1031.8
1305.7
µs
µs
IN
0.2μF
Enable Pin Turn-On Delay (EN step 1.2V to
PGOOD)
V
= 4.5V, V
= 4.0V, I
= 1.5A, C
= 2x100μF, C
BYP
IN
= 0.2μF
60
61
Output Short-Circuit Current
Output Short-Circuit Current
Output Short-Circuit Current
Output Short-Circuit Current
V
V
V
V
= 4.0V, V = 4.5V, R
IN
= 3k
0.236
0.240
2.575
2.584
0.236
0.241
2.564
2.573
A
A
A
A
OUT
OUT
OUT
OUT
SET
= 4.0V, V = 13.2V, R
= 3k
= 300
IN SET
62
= 4.0V, V = 4.5V, R
IN
SET
63
= 4.0V, V = 13.2V, R
= 300
IN SET
NOTE:
18. See the Radiation report.
FN8456 Rev.7.00
Feb 11, 2019
Page 10 of 20
ISL75052SEH, ISL73052SEH
Typical Operating Performance
2.605
2.600
2.595
2.590
10.35
10.30
10.25
10.20
10.15
10.10
10.05
10.00
V
AT +25°C
V
= 12V
V
= 10.8V
OUT
IN
IN
2.585
2.580
2.575
2.570
2.565
2.560
2.555
V
AT +125°C
OUT
V
AT -55°C
V
= 13.2V
V
= 14.7V
OUT
IN
IN
0
2
4
6
8
10
(V)
12
14
16
18
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.6
1.6
V
I
(A)
IN
OUT
FIGURE 5. LINE REGULATION vs TEMPERATURE (°C),
FIGURE 6. LOAD REGULATION V
= 10.17V AT +25°C
OUT
V
= 2.579V, I
= 0mA
OUT
OUT
10.35
10.30
10.25
10.20
10.35
10.30
10.25
10.20
10.15
10.10
10.05
10.00
V
= 10.8V
V
= 12V
IN
IN
V
= 12V
IN
V
= 10.8V
IN
V
= 14.7V
IN
10.15
10.10
10.05
10.00
V
= 13.2V
IN
V
= 14.7V
0.6
IN
V
= 13.2V
IN
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
0.2
0.4
0.8
1.0
1.2
1.4
1.6
I
(A)
I
(A)
OUT
OUT
FIGURE 7. LOAD REGULATION V
= 10.13V AT +125°C
FIGURE 8. LOAD REGULATION V
= 10.22V AT -55°C
OUT
OUT
2.61
2.60
2.59
2.61
2.60
2.59
V
= 12V
IN
V
= 10.5V
IN
V
= 4.5V
IN
V
= 4.0V
2.58
2.57
2.56
2.55
2.54
2.53
2.52
2.58
2.57
2.56
2.55
2.54
2.53
2.52
IN
V
= 14.7V
IN
V
= 13.2V
IN
V
= 5.5V
IN
V
= 5.0V
IN
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
0.2
0.4
0.6
0.8
(A)
1.0
1.2
1.4
1.6
I
(A)
I
OUT
OUT
FIGURE 9. LOAD REGULATION V
OUT
= 2.567V AT +25°C
FIGURE 10. LOAD REGULATION V
= 2.571V AT +125°C
OUT
FN8456 Rev.7.00
Feb 11, 2019
Page 11 of 20
ISL75052SEH, ISL73052SEH
Typical Operating Performance(Continued)
2.61
2.60
2.59
13.00
12.95
12.90
12.85
12.80
12.75
12.70
12.65
12.60
12.55
12.50
V
= 12V
2.58
2.57
2.56
2.55
2.54
2.53
2.52
IN
V
= 10.5V
IN
V
= 13.2V
IN
V
= 14.7V
= 16.2V
IN
V
= 14.7V
IN
V
= 13.2V
IN
V
IN
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0
0.2
0.4
0.6
0.8
(A)
1.0
1.2
1.4
1.6
I
(A)
I
OUT
OUT
FIGURE 11. LOAD REGULATION V
= 2.564V AT -55°C
FIGURE 12. LOAD REGULATION V
= 12.75V AT +25°C
OUT
OUT
13.00
12.95
12.90
12.85
12.80
12.75
13.00
12.95
12.90
12.85
12.80
V
= 14.7V
V
= 13.2V
IN
IN
12.75
12.70
12.65
12.60
12.55
12.50
V
= 16.2V
IN
V
= 14.7V
V
= 13.2V
IN
IN
12.70
12.65
12.60
12.55
12.50
V
= 16.2V
IN
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0
0.2
0.4
0.6
0.8
(A)
1.0
1.2
1.4
1.6
I
(A)
I
OUT
OUT
FIGURE 13. LOAD REGULATION V
OUT
= 12.63V AT +125°C
FIGURE 14. LOAD REGULATION V = 12.7V AT -55°C
OUT
TIMEBASE = 500µs/DIV
TIMEBASE = 500µs/DIV
V
= 20mV/DIV
OUT
V
= 20mV/DIV
OUT
I
= 500mA/DIV
OUT
I
= 500mA/DIV
OUT
FIGURE 15. LOAD STEP RESPONSE +25°C, V = 4.0V, V
IN OUT
= 2.5V,
FIGURE 16. LOAD STEP RESPONSE, +25°C, V = 4.0V, V
IN OUT
= 2.5V,
I
= 0A TO 1.6A, C
= 200µF, 30mΩ
I
= 0.15A TO 1.6A, C
= 200µF, 30mΩ
OUT
OUT
OUT
OUT
FN8456 Rev.7.00
Feb 11, 2019
Page 12 of 20
ISL75052SEH, ISL73052SEH
Typical Operating Performance(Continued)
TIMEBASE = 500µs/DIV
TIMEBASE = 500µs/DIV
V
= 50mV/DIV
V
= 50mV/DIV
OUT
OUT
I
= 500mA/DIV
I
= 500mA/DIV
OUT
OUT
FIGURE 18. LOAD STEP RESPONSE, +25°C, V = 13.2V, V
IN OUT
= 10V,
FIGURE 17. LOAD STEP RESPONSE, +25°C, V = 13.2V, V
IN OUT
= 10V,
I
= 0.15A TO 1.5A, C
= 200µF, 30mΩ
I
= 0A TO 1.5A, C
= 200µF, 30mΩ
OUT
OUT
OUT
OUT
70
60
50
40
30
60
50
180
150
120
90
180
150
120
90
PHASE (°)
PHASE (°)
40
30
20
60
60
20
10
30
10
30
0
0
0
0
-10
-20
-30
-40
-50
-60
-70
-10
-20
-30
-40
-50
-60
-30
-60
-90
-120
-150
-180
-30
-60
-90
-120
-150
-180
GAIN (dB)
GAIN (dB)
500
5k
50k
FREQUENCY (Hz)
500k
500
5k
50k
500k
FREQUENCY (Hz)
FIGURE 19. GAIN PHASE PLOTS, V = 4V, V
IN
= 2.5V, I
= 200µF, 30mΩ,
= 1.5A,
OUT
FIGURE 20. GAIN PHASE PLOTS, V = 11V, V
IN OUT
= 10V, I
= 1.5A,
OUT
OUT
OUT
R
= 22k, C
= 1nF, C
R
= 22k, C
= 1nF, C
= 200µF, 30mΩ,
COMP
COMP
COMP
COMP
OUT
PHASE MARGIN = 98.68°, GAIN MARGIN = 23.01dB
PHASE MARGIN = 84.56°, GAIN MARGIN = 18.06dB
-30
-40
-50
-60
-70
-80
-90
-100
100
10
+125°C PSRR (dB)
1
V
V
I
= 6V
IN
+25°C PSRR (dB)
-55°C PSRR (dB)
= 5V
OUT
= 1A
0.1
0.01
OUT
TEMP = +25oC
e
= 582.11 nV/√Hz AT 1kHz
n
100
1k
10k
100k
0.1
1.0
10.0
100.0
1,000.0
10,000.0 100,000.0
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 22. OUTPUT NOISE DENSITY
FIGURE 21. PSRR, V = 4.9V, V
IN OUT
= 4.0V, I
= 1.5A,
OUT
R
= 22k, C = 1nF, C
= 200µF, 30mΩ
COMP
COMP
OUT
FN8456 Rev.7.00
Feb 11, 2019
Page 13 of 20
ISL75052SEH, ISL73052SEH
Typical Operating Performance(Continued)
TIMEBASE = 1ms/DIV
C1 TO C4 = 1V/DIV
TIMEBASE = 1ms/DIV
C1 TO C4 = 1V/DIV
EN
EN
V
V
IN
IN
V
V
OUT
OUT
P
P
GOOD
GOOD
FIGURE 23. +25°C START-UP WITH ENABLE, V = 4V, V
IN OUT
= 2.5V,
FIGURE 24. +25°C START-UP WITH ENABLE, V = 4V, V = 2.5V,
IN OUT
I
= 0.1A
I
= 1.5A
OUT
OUT
TIMEBASE = 5ms/DIV
TO C = 1V/DIV
TIMEBASE = 5ms/DIV
TO C = 1V/DIV
V
C
1
C
OUT
4
V
1
4
OUT
V
IN
V
IN
P
P
GOOD
GOOD
EN
EN
FIGURE 25. +25°C SHUTDOWN WITH ENABLE, V = 4V, V
IN OUT
= 2.5V,
FIGURE 26. +25°C SHUTDOWN WITH ENABLE, V = 4V, V = 2.5V,
IN OUT
I
= 0.1A
I
= 1.5A
OUT
OUT
TIMEBASE = 200µs/DIV
EN
V
IN
V
OUT
P
GOOD
FIGURE 27. +25°C PROPAGATION DELAY, V = 4.5V, V
IN OUT
= 4V, I
= 1.5A, EN 50% TO V 5%
OUT
OUT
FN8456 Rev.7.00
Feb 11, 2019
Page 14 of 20
ISL75052SEH, ISL73052SEH
ESD Clamps
Applications Information
The ESD_CL_12V ESD clamps break down at nominally 17V. The
ESD_RC_7V clamps break down at nominally 7.5V with a
tolerance of ±10%. The PG pin has a diode to GND. The VOUT pin
has a diode to VIN (see “Pin Descriptions” on page 4).
Input Voltage Requirements
This RH LDO works from a V in the range of 4.0V to 13.2V. The
IN
input supply can have a tolerance of as much as ±10% for
conditions noted in the specification table. The minimum
assured input voltage is 4.0V. However, due to the nature of an
Soft-Start
LDO, V must be some margin higher than the output voltage
Soft-start is achieved by means of the charging time constant of
the BYP pin. The capacitor value on the pin determines the time
constant and can be calculated using Equation 2:
IN
plus dropout at the maximum rated current of the application if
active filtering (PSRR) is expected from V to V . The Dropout
IN
OUT
specification of this family of LDOs has been generously
specified in order to allow design for efficient operation.
t
= (3.3338E-6 C
) + (9.5725E-8 T – 9.2628E-6
(EQ. 2)
BYP A
SS
Where:
= Soft-start time in seconds.
External Capacitor Requirements
t
SS
GENERAL GUIDELINES
C
= Bypass capacitance in nF.
BYP
External capacitors are required for proper operation. Careful
attention must be paid to layout guidelines and selection of
capacitor type and value to ensure optimal performance.
T = Ambient temperature in °C.
A
COMP Pin
OUTPUT CAPACITORS
This pin helps compensate the device for various load conditions.
For 4.0V < V < 6.0V use R = 40k and C = 1nF. For
It is recommended to use a combination of tantalum and
ceramic capacitors to achieve a good volume to capacitance
ratio. The recommended combination is a 2x100µF 60mΩ rated,
KEMET T541 series tantalum capacitor, in parallel with a 0.1µF
IN
COMP
= 40k and C
COMP
= 4.7nF. The
COMP
6V < V < 13.2V use R
IN COMP
maximum current of the COMP pin when shorted to GND is
160µA.
MIL-PRF-49470 ceramic capacitor to be connected to V
and
OUT
ground pins of the LDO with PCB traces no longer than 0.5cm.
Undervoltage Lockout
The undervoltage lockout function detects when VCCX exceeds
3.2V. When that level is reached, the LDO feedback loop is closed
and the LDO can begin regulating. This is achieved by freeing the
BYP net to charge up and act as a reference voltage to the EA.
Prior to that happening, the LDO Power PMOS device is clamped
off.
INPUT CAPACITORS
It is recommended to use a combination of tantalum and
ceramic capacitors to achieve a good capacitance to volume
ratio. The recommended combination is a 2x100µF 60mΩ rated,
KEMET T541 series tantalum capacitor in parallel with a 0.1µF
MIL-PRF-49470 ceramic capacitor to be connected to V and
IN
ground pins of the LDO with PCB traces no longer than 0.5cm.
Bottom Metal Electrical Potential
The package bottom metal is electrically isolated and unbiased.
The bottom metal may be electrically connected to any potential,
which offers the best thermal path through conductive mounting
materials (such as conductive epoxy or solder) or can be left
unbiased through the use of electrically nonconductive mounting
materials (nonconductive epoxy, Sil-pad, kapton film, etc.).
Current Limit Protection
The RH LDO incorporates protection against overcurrent due to
any short or overload condition applied to the output pin. The
current limit circuit performs as a constant current source when
the output current exceeds the current limit threshold, which can
be adjusted by means of a resistor connected between the OCP
pin and GND. If the short or overload condition is removed from
Bottom Metal Mounting Guidelines
The package bottom is a solderable metal surface. The following
JESD51-5 guidelines can be used to mount the package:
V
, then the output returns to normal voltage mode regulation.
OUT
In the event of an overload condition, the LDO begins to cycle on
and off due to the die temperature exceeding thermal fault
condition. However, you may never witness thermal cycling if the
heatsink used for the package can keep the die temperature
below the limits specified for thermal shutdown. The R
be calculated using Equation 1:
• Place a thermal land on the PCB under the bottom metal.
• The land should be approximately the same size to 1mm
larger than the 0.19inx0.41in bottom metal.
can
OCP
• Place an array of thermal vias below the thermal land.
• Via array size: ~4 x 9 = 36 thermal vias
762.8
-----------------------------------------------------------------------------------------------------------------------------------------------------------
=
R
OCP
I
– 1.382E-03 V – 2.629E-04 T + 4.493E-02
OCP
IN A
• Via diameter: ~0.3mm drill diameter with plated copper on
the inside of each via.
(EQ. 1)
where:
= The OCP setting resistor in ohms.
R
OCP
• Via pitch: ~1.2mm.
V
= Supply voltage in volts.
IN
Vias should drop to and contact as much buried metal area as
feasible to provide the best thermal path.
I
= The required OCP threshold in amps.
OCP
T = The ambient temperature in °C.
A
FN8456 Rev.7.00
Feb 11, 2019
Page 15 of 20
ISL75052SEH, ISL73052SEH
Thermal Fault Protection
In the event the die temperature exceeds +170°C (typical) the
output of the LDO shuts down until the die temperature can cool
down to +150°C (typical). The level of power combined with the
thermal impedance of the package ( of 5°C/W for the 16 Ld
JC
CDFP package) determine if the junction temperature exceeds the
thermal shutdown temperature specified in the specification table
(see “Bottom Metal Mounting Guidelines” on page 15).
Package Characteristics
Weight of Packaged Device
Assembly Related Information
0.59 Grams (typical)
SUBSTRATE POTENTIAL
Ground
Lid Characteristics
Finish: Gold
Potential: Connected to Pin 13 (GND)
Case Isolation to Any Lead: 20x10 Ω (minimum)
Additional Information
9
WORST CASE CURRENT DENSITY
5
2
<2x10 A/cm
Die Characteristics
Die Dimensions
TRANSISTOR COUNT
1074
2819μmx5638μm (111 milsx222 mils)
Thickness: 304.8μm ±25.4μm (12.0 mils ±1 mil)
PROCESS
0.6µm BiCMOS Junction Isolated
Interface Materials
GLASSIVATION
Type: Silicon Oxide and Silicon Nitride
Thickness: 0.3µm ±0.03µm to 1.2µm ±0.12µm
TOP METALLIZATION
Type: AlCu (99.5%/0.5%)
Thickness: 2.7µm ±0.4µm
SUSTRATE
Type: Silicon
BACKSIDE FINISH
Silicon
FN8456 Rev.7.00
Feb 11, 2019
Page 16 of 20
ISL75052SEH, ISL73052SEH
Metallization Mask Layout
11
9
8
12
7
13
14
10
15
6
3
1
4
2
5
TABLE 2. DIE LAYOUT X-Y COORDINATES
PAD
1
X
Y
DX
DY
PIN NAME
VOUT
VOUT
VIN
1019
1249
3070
3300
5037
5253
5099
4635
3824
2840
1799
668
1021
390
185
185
185
185
185
185
185
185
185
185
185
185
185
185
185
450
449
450
450
185
185
185
185
185
450
185
185
185
184
450
2
3
1030
399
4
VIN
5
256
OCP
VCC
6
1635
2436
2436
2436
1660
2436
2436
2381
1972
1652
7
PG
8
NC
9
COMP
VIN
10
11
12
13
14
15
GND
EN
168
ADJ
168
BYP
789
VOUT
FN8456 Rev.7.00
Feb 11, 2019
Page 17 of 20
ISL75052SEH, ISL73052SEH
Revision History The revision history provided is for informational purposes only and is believed to be accurate, however, not
warranted. Please go to the web to make sure that you have the latest revision.
DATE
REVISION
FN8456.7
CHANGE
Feb 11, 2019
Added ISL73052SEH part information throughout document.
Updated Features note.
Added Notes 3 and 4.
Removed 100k RAD column from LDR Post Radiation Characteristics table on page 9.
Removed About Intersil section.
Updated Disclaimer.
Oct 25, 2016
FN8456.6
Updated Related Literature section.
Updated Ordering information table and Note 2.
Added Figure 22 on page 13.
Nov 5, 2015
FN8456.5
FN8456.4
Updated Equation 1 on page 15.
Aug 31, 2015
Updated Equation 2 on page 15.
Thermal Information table on page 5: Removed reference to TB493.
Dec 4, 2014
FN8456.3
FN8456.2
Updated Figure 1 for clarity.
Added ESD Ratings to “Absolute Maximum Ratings” on page 5.
July 11, 2014
1) Pages 7 thru 10 - Added Radiation tables
2) Page 15 - Added paragraph for Soft Start: " The Soft-start is achieved by means of the charging time
constant of the BYP pin. The capacitor value on the pin determines the time constant and can be
calculated using Equation 2.
Ts = (2961xCs) -121] EQ. 2
Where Ts = soft-start time in ms, and Cs = BYPASS capacitor in nF.
3) Page 15 - Changed in 1st paragraph, 2nd sentence “( of 5°C/W....” to “( of 4.5°C/W.....”
JC
JC
4) Page 17 - Rotated and changed pad numbers on Metallization Mask layout
Updated Die layout X-Y Coordinates table
Sep19, 2013
FN8456.1
FN8456.0
Recommended operating conditions table on page 5, changed VOUT min from 2.5V to 0.6V, and added
Note 11.
Electrical spec on page 6, Output Noise Voltage, changed test conditions from
I
I
= 10mA, BW = 300Hz < f <300 kHz, BYPASS to GND capacitor = 0.2µF to V = 4.1V, V T = 2.5V,
LOAD
LOAD
IN
OU
= 10mA, BW = 100Hz < f <100 kHz, BYPASS to GND capacitor = 0.2µF.
= 0.2A to I = 1.5A.
Figure 19 on page 11, changed the value from I
OUT
OUT
Figure 20 on page 11, changed the values from V = 4V to V = 11V and V
= 2.5V to V
= 10V.
IN IN OUT
OUT
May 29, 2013
Initial Release
FN8456 Rev.7.00
Feb 11, 2019
Page 18 of 20
ISL75052SEH, ISL73052SEH
For the most recent package outline drawing, see K16.E.
Package Outline Drawing
K16.E
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Rev 1, 1/12
0.015 (0.38)
0.008 (0.20) ID OPTIONAL
PIN NO. 1
1
2
A
A
0.050 (1.27 BSC)
PIN NO. 1
ID AREA
0.420
0.400
0.005 (0.13)
MIN
4
TOP VIEW
0.022 (0.56)
0.015 (0.38)
0.115 (2.92)
0.085 (2.16)
0.009 (0.23)
0.004 (0.10)
0.045 (1.14)
0.026 (0.66)
6
0.278 (7.06)
0.262 (6.65)
-D-
-H-
-C-
0.370 (9.40)
0.250 (6.35)
0.198 (5.03)
0.182 (4.62)
BOTTOM
METAL
0.03 (0.76) MIN
7
SEATING AND
BASE PLANE
SIDE VIEW
BOTTOM METAL
0.005 (0.127) REF.
OFFSET FROM
CERAMIC EDGE
OPTIONAL
PIN 1 INDEX
BOTTOM VIEW
NOTES:
Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark. Alternately, a tab may be used to identify pin one.
1.
0.006 (0.15)
0.004 (0.10)
LEAD FINISH
2. If a pin one identification mark is used in addition to a tab, the limits
of the tab dimension do not apply.
0.009 (0.23)
0.004 (0.10)
BASE
METAL
3. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
0.019 (0.48)
0.015 (0.38)
4. Measure dimension at all four corners.
0.0015 (0.04)
MAX
5. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
0.022 (0.56)
0.015 (0.38)
6. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
3
SECTION A-A
7. The bottom of the package is a solderable metal surface.
8. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
9. Dimensions: INCH (mm). Controlling dimension: INCH.
FN8456 Rev.7.00
Feb 11, 2019
Page 19 of 20
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