5962L1321403VXC [RENESAS]
Operational Amplifier;
| 型号： | 5962L1321403VXC |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Operational Amplifier 放大器 |
| 文件： | 总27页 (文件大小：1887K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL70444SEH, ISL73444SEH
19MHz Radiation Hardened 40V Quad Rail-to-Rail Input - Output,
Low-Power Operational Amplifiers
FN8411
Rev.7.00
Aug 16, 2019
The ISL70444SEH and ISL73444SEH (ISL7x444SEH) feature
Features
four low-power amplifiers optimized to provide maximum
dynamic range. These operational amplifiers (op amps)
feature a unique combination of rail-to-rail operation on the
input and output as well as a slew enhanced front-end that
provides ultra fast slew rates positively proportional to a given
step size, thereby increasing accuracy under transient
conditions, whether it’s periodic or momentary. The
ISL7x444SEH also offer low power, low offset voltage, and low
temperature drift, making them ideal for applications
requiring both high DC accuracy and AC performance. With
<5µs recovery for Single Event Transients (SET)
(LETTH = 86.4MeV•cm2/mg), the number of filtering
components needed is drastically reduced. The ISL7x444SEH
are also immune to single event latch-up because they are
fabricated using the Renesas proprietary PR40 Silicon On
Insulator (SOI) process.
• Electrically screened to DLA SMD# 5962-13214
• Acceptance tested to 50krad(Si) (LDR) wafer-by-wafer
• <5µs recovery from SEE (LETTH = 86.4MeV•cm2/mg)
• Unity gain stable
• Rail-to-rail input and output
• Wide gain·bandwidth product . . . . . . . . . . . . . . . . . . . . 19MHz
• Wide single and dual supply range. . . . . . . . 2.7V to 40V max
• Low input offset voltage . . . . . . . . . . . . . . . . . . . . . . . . . 400µV
• Low current consumption (per amplifier) . . . . . . . 1.1mA, typ
• No phase reversal with input overdrive
• Slew rate
- Large signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60V/µs
The amplifiers are designed to operate over a single supply
range of 2.7V to 40V or a split supply voltage range of ±1.35V to
±20V. Applications for these amplifiers include precision
instrumentation, data acquisition, precision power supply
controls, and process controls.
• Operating temperature range. . . . . . . . . . . .-55°C to +125°C
• ISL70444SEH radiation acceptance (see TID report)
- High dose rate (50-300rad(Si)/s). . . . . . . . . . . 300krad(Si)
(ISL70444SEH only)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . . . .50krad(Si)
• ISL73444SEH radiation acceptance (see TID report)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . . . .50krad(Si)
• SEE hardness (see SEE report for details)
- SEB LETTH (VS = ±21V). . . . . . . . . . . . . . 86.4MeV•cm2/mg
- SEL immune (SOI Process)
The ISL7x444SEH are available in a 14 Ld hermetic ceramic
flatpack and die forms that operate across the temperature
range of -55°C to +125°C.
Applications
• Precision instruments
• Active filter blocks
• Data acquisition
Related Literature
• For a full list of related documents, visit our website:
- ISL70444SEH, ISL73444SEH device pages
• Power supply control
• Process control
R
F
100kΩ
30
+2.7V
to 40V
R
-
IN
-IN
V ±18V
S
-
V
+
20
10
OUT
+
10kΩ
V
R
ISL7x444
SENSE
-
R
+
V
IN
+IN
+
V
= 10
OUT
0
10kΩ
GROUNDED
BIASED
(I
* R
)
SENSE
LOAD
R
+
REF
-10
-20
-30
LOAD
100kΩ
V
REF
0
50
100
150
200
250
300
krad (Si)
FIGURE 1. TYPICAL APPLICATION: SINGLE-SUPPLY, HIGH-SIDE
CURRENT SENSE AMPLIFIER
FIGURE 2. VOS SHIFT vs HIGH DOSE RATE RADIATION
FN8411 Rev.7.00
Aug 16, 2019
Page 1 of 27
ISL70444SEH, ISL73444SEH
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications VS = ±18V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications VS = ±2.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications VS = ±1.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications VS = ±18V - Post Radiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Specifications VS = ±2.5V - Post Radiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical Specifications VS = ±1.5V - Post Radiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Post High Dose Rate Radiation Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Post Low Dose Rate Radiation Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input ESD Diode Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output Short-Circuit Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output Phase Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Slew Rate Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Unused Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Die Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Interface Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Assembly Related Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Weight of Packaged Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Lid Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Metallization Mask Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
FN8411 Rev.7.00
Aug 16, 2019
Page 2 of 27
ISL70444SEH, ISL73444SEH
Pin Configuration
14 LD FLATPACK
TOP VIEW
OUT
14
13
12
11
10
9
OUT
1
A
D
2
3
4
5
6
7
A
D
-IN
+IN
V
-IN
D
A
-
-
+
+
-
-
+IN
A
+
D
C
-
V
+IN
-IN
+IN
-IN
B
B
B
+
B
+
C
C
8
OUT
C
OUT
Pin Descriptions
PIN NUMBER
PIN NAME
OUTA
-INA
EQUIVALENT ESD CIRCUIT
Circuit 2
DESCRIPTION
1
2
Amplifier A output
Circuit 1
Amplifier A inverting input
Amplifier A non-inverting input
Positive power supply
3
+INA
V+
Circuit 1
4
Circuit 3
5
+INB
-INB
Circuit 1
Amplifier B non-inverting input
Amplifier B inverting input
Amplifier B output
6
Circuit 1
7
OUTB
OUTC
-INC
Circuit 2
8
Circuit 2
Amplifier C output
9
Circuit 1
Amplifier C inverting input
Amplifier C non-inverting input
Negative power supply
10
11
12
13
14
-
+INC
V-
Circuit 1
Circuit 3
+IND
-IND
Circuit 1
Amplifier D non-inverting input
Amplifier D inverting input
Amplifier D output
Circuit 1
OUTD
E-Pad
Circuit 2
None
E-Pad under package (Unbiased, tied to package lid)
+
V
+
+
V
V
CAPACITIVELY
TRIGGERED ESD
CLAMP
600Ω
600Ω
OUT
IN-
IN+
-
V
-
V
-
V
CIRCUIT 2
CIRCUIT 3
CIRCUIT 1
FN8411 Rev.7.00
Aug 16, 2019
Page 3 of 27
ISL70444SEH, ISL73444SEH
Ordering Information
ORDERING/SMD NUMBER
PART NUMBER
RADIATION HARDNESS
(Total Ionizing Dose)
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
(Note 2)
(Note 1)
5962F1321401VXC
ISL70444SEHVF
HDR to 300krad(Si),
LDR to 50krad(Si)
-55 to +125
-55 to +125
-55 to +125
+25
14 Ld Flatpack
K14.C
N/A
ISL70444SEHF/PROTO
(Note 3)
N/A
14 Ld Flatpack
DIE
K14.C
5962F1321401V9A
ISL70444SEHVX
HDR to 300krad(Si),
LDR to 50krad(Si)
N/A
N/A
ISL70444SEHX/SAMPLE
(Note 3)
N/A
DIE
ISL73444SEHF/PROTO
(Note 3)
N/A
-55 to +125
14 Ld Flatpack
K14.C
K14.C
5962L1321403VXC
5962F1321403V9A
N/A
ISL73444SEHVF
ISL73444SEHVX
LDR to 50krad(Si)
LDR to 50krad(Si)
N/A
-55 to +125
-55 to +125
+25
14 Ld Flatpack
DIE
DIE
ISL73444SEHX/SAMPLE
(Note 3)
N/A
ISL70444SEHEVAL1Z
(Note 4)
N/A
Evaluation Board
NOTES:
1. These Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb
and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed must be
used when ordering.
3. The /PROTO and /SAMPLE are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity. These parts are intended for
engineering evaluation purposes only. The /PROTO parts meet the electrical limits and conditions across the temperature range specified in the DLA
SMD and are in the same form and fit as the qualified device. The /SAMPLE die is capable of meeting the electrical limits and conditions specified
in the DLA SMD at +25°C only. The /SAMPLE is a die and does not receive 100% screening across the temperature range to the DLA SMD electrical
limits. These part types do not come with a certificate of conformance because there is no radiation assurance testing and they are not DLA qualified
devices.
4. The evaluation board uses /PROTO parts. The /PROTO parts are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE)
immunity.
FN8411 Rev.7.00
Aug 16, 2019
Page 4 of 27
ISL70444SEH, ISL73444SEH
Absolute Maximum Ratings
Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V
Maximum Supply Voltage (Note 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V
Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Maximum Differential Input Voltage . . . . . . . . 42V or V- - 0.5V to V+ + 0.5V
Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . 42V or V- - 0.5V to V+ + 0.5V
Max/Min Input Current for Input Voltage >V+ or <V- . . . . . . . . . . . . ±20mA
ESD Tolerance
Human Body Model (Tested per MIL-PRF-883 3015.7). . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per CDM-22CI0ID). . . . . . . . . . . . . . 750V
Thermal Resistance (Typical)
14 Ld Flatpack Package (Notes 5, 6). . . . .
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
JA (°C/W)
JC (°C/W)
9
35
Recommended Operating Conditions
Ambient Operating Temperature Range . . . . . . . . . . . . . .-55°C to +125°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C
Single Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . 3V ±10% to 36V ±10%
Split Rail Supply Voltage . . . . . . . . . . . . . . . . .. ±1.5V ±10% to ±18V ±10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379.
6. For JC, the “case temp” location is the center of the package underside.
7. Tested in a heavy ion environment at LET = 86.4MeV•cm2/mg at +125°C (TC) for SEB. See Single Event Effects Test Report for more information.
Electrical Specifications V = ±18V
V
= V = 0V, R = Open, T = +25°C, unless otherwise noted. Boldface limits apply
CM O L A
S
across the operating temperature range, -55°C to +125°C.
MIN
MAX
PARAMETER
Offset Voltage
SYMBOL
VOS
TEST CONDITIONS
VCM = 0V
CM = V+ to V-
(Note 8)
TYP
20
(Note 8)
UNIT
µV
400
V
80
500
µV
Offset Voltage Temperature Coefficient
Input Offset Channel-to-Channel Match
TCVOS
VCM = V+ - 2V to V- + 2V
0.5
µV/°C
VOS
VCM = V+
VCM = V-
VCM = 0V
77
800
800
370
µV
µV
nA
117
189
Input Bias Current
IB
V
V
V
V
CM = V+
200
262
200
257
0
370
650
370
650
30
nA
nA
nA
nA
nA
nA
V
CM = V-
CM = V+ - 0.5V
CM = V- + 0.5V
Input Offset Current
IOS
VCM = V+ to V-
-30
-50
V-
0
50
Common-Mode Input Voltage Range
Common-Mode Rejection Ratio
VCMIR
V+
CMRR
V
CM = V- to V+
112
111
128
dB
dB
dB
dB
dB
VCM = V- to V+
70
80
VCM = V+ - 0.5V to V- + 0.5V
VCM = V+ - 0.5V to V- + 0.5V
Power Supply Rejection Ratio
Open-Loop Gain
PSRR
AVOL
VOH
V- = -18V; V+ = 0.5V to 18V
V+ = 18V; V- = -0.5V to -18V
83
96
dB
dB
RL = 10kΩ to ground
125
dB
Output Voltage High (VOUT to V+)
Output Voltage Low (VOUT to V-)
Output Short-Circuit Current
RL = No load
RL = 10kΩ
78
118
73
160
175
160
175
mV
mV
mV
mV
mA
VOL
RL = No load
RL = 10kΩ
110
ISRC
Sourcing; VIN = 0V, VOUT = -18V
10
FN8411 Rev.7.00
Aug 16, 2019
Page 5 of 27
ISL70444SEH, ISL73444SEH
Electrical Specifications V = ±18V
V
= V = 0V, R = Open, T = +25°C, unless otherwise noted. Boldface limits apply
CM O L A
S
across the operating temperature range, -55°C to +125°C. (Continued)
MIN
MAX
PARAMETER
SYMBOL
ISNK
TEST CONDITIONS
(Note 8)
TYP
(Note 8)
UNIT
mA
Output Short-Circuit Current
Sinking; VIN = 0V, VOUT = +18V
10
Supply Current/Amplifier
IS
Unity gain
1.5
1.75
mA
mA
1.95
2.4
AC SPECIFICATIONS
Gain Bandwidth Product
Voltage Noise Density
Current Noise Density
Large Signal Slew Rate
GBW
en
A
CL = 101, RL = 10k
19
MHz
nV/√Hz
pA/√Hz
V/µs
f = 10kHz
f = 10kHz
11.3
0.312
in
SR
AV = 1, RL = 10kΩVO = 10VP-P
60
Electrical Specifications V = ±2.5V
V
= V = 0V, R = Open, T = +25°C, unless otherwise noted. Boldface limits apply
CM O L A
S
across the operating temperature range, -55°C to +125°C.
MIN
MAX
PARAMETER
Offset Voltage
SYMBOL
VOS
TEST CONDITIONS
VCM = 0V
CM = V+ to V-
(Note 8)
TYP
20
(Note 8)
UNIT
µV
400
V
80
500
µV
Offset Voltage Temperature Coefficient
Input Offset Channel-to-Channel Match
TCVOS
VCM = V+ - 2V to V- + 2V
0.5
µV/°C
VOS
VCM = V+
VCM = V-
VCM = 0V
79
800
800
340
µV
µV
nA
119
202
Input Bias Current
IB
V
V
V
V
CM = V+
182
229
181
224
0
340
580
340
580
30
nA
nA
nA
nA
nA
nA
V
CM = V-
CM = V+ - 0.5V
CM = V- + 0.5V
Input Offset Current
IOS
VCM = V+ to V-
-30
-50
V-
0
50
Common-Mode Input Voltage Range
Common-Mode Rejection Ratio
VCMIR
V+
CMRR
V
CM = V- to V+
92
91
dB
dB
dB
dB
dB
VCM = V- to V+
70
74
VCM = V+ - 0.5V to V- + 0.5V
VCM = V+ - 0.5V to V- + 0.5V
Power Supply Rejection Ratio
PSRR
V- = -2.5V; V+ = 0.5V to 2.5V
V+ = 2.5V; V- = -0.5V to -2.5V
TA = +25°C, +125°C
123
80
70
dB
dB
V- = -2.5V; V+ = 0.5V to 2.5V
V+ = 2.5V; V- = -0.5V to -2.5V
TA = -55°CC
Open-Loop Gain
AVOL
RL = 10kΩ to ground
118
dB
dB
90
Output Voltage High (VOUT to V+)
VOH
RL = No load
RL = 10kΩ
RL = 600Ω
53
53
85
mV
mV
mV
105
400
FN8411 Rev.7.00
Aug 16, 2019
Page 6 of 27
ISL70444SEH, ISL73444SEH
Electrical Specifications V = ±2.5V
V
= V = 0V, R = Open, T = +25°C, unless otherwise noted. Boldface limits apply
CM O L A
S
across the operating temperature range, -55°C to +125°C. (Continued)
MIN
MAX
PARAMETER
SYMBOL
VOL
TEST CONDITIONS
RL = No load
(Note 8)
TYP
53
(Note 8)
UNIT
mV
Output Voltage Low (VOUT to V-)
85
105
400
1.25
1.8
RL = 10kΩ
RL = 600Ω
Unity gain
53
mV
mV
mA
mA
Supply Current/Amplifier
IS
1.1
1.6
AC SPECIFICATIONS
Gain Bandwidth Product
Voltage Noise Density
Current Noise Density
Large Signal Slew Rate
GBW
en
A
CL = 101, RL = 10k
17
12.3
0.313
35
MHz
nV/√Hz
pA/√Hz
V/µs
f = 10kHz
in
f = 10kHz
SR
AV = 1, RL = 10kΩVO = 3VP-P
Electrical Specifications V = ±1.5V
V
= V = 0V, R = Open, T = +25°C, unless otherwise noted. Boldface limits apply
CM O L A
S
across the operating temperature range, -55°C to +125°C.
MIN
MAX
PARAMETER
Offset Voltage
SYMBOL
VOS
TEST CONDITIONS
VCM = 0V
CM = V+ to V-
(Note 8)
TYP
51
(Note 8)
UNIT
µV
400
V
80
500
µV
Input Offset Channel-to-Channel Match
Input Bias Current
VOS
VCM = V+
VCM = V-
VCM = 0V
79
800
800
330
µV
µV
nA
119
220
IB
V
V
V
V
CM = V+
180
225
180
223
0
330
565
330
565
30
nA
nA
nA
nA
nA
nA
V
CM = V-
CM = V+ - 0.5V
CM = V- + 0.5V
Input Offset Current
IOS
VCM = V+ to V-
CM = V+ to V-
-30
-50
V-
V
0
50
Common-Mode Input Voltage Range
Output Voltage High (VOUT to V+)
VCMIR
VOH
V+
RL = No load
RL = 10kΩ
RL = No load
RL = 10kΩ
Unity Gain
26
30
39
mV
mV
mV
mV
mA
mA
60
Output Voltage Low (VOUT to V-)
Supply Current/Amplifier
VOL
26
39
42
60
IS
1.1
1.57
1.24
1.8
AC SPECIFICATIONS
Gain Bandwidth Product
Voltage Noise Density
Current Noise Density
GBW
en
A
CL = 101, RL = 10k
16
12
MHz
f = 10kHz
f = 10kHz
nV/√Hz
pA/√Hz
in
0.312
FN8411 Rev.7.00
Aug 16, 2019
Page 7 of 27
ISL70444SEH, ISL73444SEH
Electrical Specifications V = ±18V - Post Radiation
V
= V = 0V, R = Open, T = +25°C, unless otherwise
CM O L A
S
noted. Boldface limits apply across a total ionizing dose of 300krad(Si) with exposure of a high dose rate of 50 to 300rad(Si)/s (ISL70444SEH only) and
across a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s.
MIN
MAX
PARAMETER
Offset Voltage
SYMBOL
VOS
TEST CONDITIONS
VCM = V+ to V-
VCM = V+
CM = V-
VCM = V+
CM = V-
VCM = V+ to V-
(Note 8)
TYP
(Note 8
UNIT
µV
µV
µV
nA
nA
nA
V
500
800
800
650
Input Offset Channel-to-Channel
Match
VOS
V
Input Bias Current
IB
V
-650
-50
V-
Input Offset Current
IOS
50
V+
Common-Mode Input Voltage Range
Common-Mode Rejection Ratio
VCMIR
CMRR
V
CM = V- to V+
70
dB
VCM = V- to V+
VCM= V+ - 0.5V to V- + 0.5V
dB
dB
V
CM= V+ - 0.5V to V- + 0.5V
80
Power Supply Rejection Ratio
PSRR
V- = -18V; V+ = 0.5V to 18V
V+ = 18V; V- = -0.5V to -18V
dB
83
dB
Open-Loop Gain
AVOL
VOH
RL = 10kΩ to ground
RL = No load
96
dB
Output Voltage High (VOUT to V+)
160
175
150
165
mV
mV
mV
mV
mA
mA
mA
V/µs
RL = 10kΩ
Output Voltage Low (VOUT to V-)
VOL
RL = No load
RL = 10kΩ
Output Short-Circuit Current
Output Short-Circuit Current
Supply Current/Amplifier
Large Signal Slew Rate
ISRC
ISNK
IS
Sourcing; VIN = 0V, VOUT = -18V
Sinking; VIN = 0V, VOUT = +18V
Unity gain
10
10
2.4
SR
AV = 1, RL = 10kΩ, VO = 10VP-P
60
FN8411 Rev.7.00
Aug 16, 2019
Page 8 of 27
ISL70444SEH, ISL73444SEH
Electrical Specifications V = ±2.5V - Post Radiation
V
= V = 0V, R = Open, T = +25°C, unless otherwise
CM O L A
S
noted. Boldface limits apply a total ionizing dose of 300krad(Si) with exposure of a high dose rate of 50 to 300rad(Si)/s (ISL70444SEH only) and across
a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s.
MIN
MAX
PARAMETER
Offset Voltage
SYMBOL
VOS
TEST CONDITIONS
VCM = V+ to V-
(Note 8)
TYP
(Note 8)
UNIT
µV
500
Input Offset Channel-to-Channel Match
VOS
VCM = V+
VCM = V-
VCM = V+
800
800
650
µV
µV
nA
Input Bias Current
IB
V
CM = V-
VCM = V+ to V-
-650
-50
V-
nA
nA
V
Input Offset Current
IOS
50
V+
Common-Mode Input Voltage Range
Common-Mode Rejection Ratio
VCMIR
CMRR
V
CM = V- to V+
dB
dB
dB
dB
dB
VCM = V- to V+
70
74
VCM= V+ - 0.5V to V- + 0.5V
V
CM= V+ - 0.5V to V- + 0.5V
Power Supply Rejection Ratio
PSRR
V- = -2.5V; V+ = 0.5V to 2.5V
V+ = 2.5V; V- = -0.5V to -2.5V
80
dB
dB
Open-loop Gain
AVOL
VOH
RL = 10kΩ to ground
RL = No load
RL = 10kΩ
90
Output Voltage High (VOUT to V+)
85
105
400
85
mV
mV
mV
mV
mV
mV
mA
RL = 600Ω
Output Voltage Low (VOUT to V-)
Supply Current/Amplifier
VOL
RL = No load
RL = 10kΩ
105
400
1.8
RL = 600Ω
IS
Unity gain
Electrical Specifications V = ±1.5V - Post Radiation
V
= V = 0V, R = Open, T = +25°C, unless otherwise
CM O L A
S
noted. Boldface limits apply a total ionizing dose of 300krad(Si) with exposure of a high dose rate of 50 to 300rad(Si)/s (ISL70444SEH only) and across
a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s.
MIN
MAX
PARAMETER
Offset Voltage
SYMBOL
VOS
TEST CONDITIONS
VCM = V+ to V-
(Note 8)
TYP
(Note 8)
UNIT
µV
500
Input Offset Channel-to-Channel Match
VOS
VCM = V+
VCM = V-
VCM = V+
800
800
650
µV
µV
nA
Input Bias Current
IB
V
CM = V-
-650
-50
V-
nA
nA
Input Offset Current
IOS
VCMIR
VOH
VCM = V+ to V-
50
V+
Common-Mode Input Voltage Range
Output Voltage High (VOUT to V+)
V
RL = No load
RL = 10kΩ
RL = No load
RL = 10kΩ
Unity gain
160
175
150
165
1.8
mV
mV
mV
mV
mA
Output Voltage Low (VOUT to V-)
VOL
Supply Current/Amplifier
NOTE:
IS
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.
FN8411 Rev.7.00
Aug 16, 2019
Page 9 of 27
ISL70444SEH, ISL73444SEH
Typical Performance Curves Unless otherwise specified, V ±18V, V = 0, V = 0V, T = +25°C.
S
CM
O
A
120
100
80
300
200
100
0
60
40
20
0
-100
-200
-300
-20
-40
-60
-20
-15
-10
-5
0
5
10
15
20
-20
-15
-10
-5
0
5
10
15
20
COMMON MODE VOLTAGE (V)
COMMON MODE VOLTAGE (V)
FIGURE 3. OFFSET VOLTAGE vs COMMON-MODE VOLTAGE
FIGURE 4. IBIAS vs COMMON-MODE VOLTAGE
300
250
200
150
100
50
IB+
250
200
150
100
50
IB+
IB-
IB-
0
-100
0
-50
0
50
100
150
-100
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 6. IBIAS vs TEMPERATURE (VS = ±2.5V)
FIGURE 5. IBIAS vs TEMPERATURE (VS = ±18V)
2.5
2.0
1.5
1.0
0.5
0
300
250
200
150
100
50
IB+
IB-
I
OS
0
-100
-100
-50
0
50
100
150
-50
0
50
TEMPERATURE (°C)
FIGURE 7. IBIAS vs TEMPERATURE, (VS = ±1.5V)
100
150
TEMPERATURE (°C)
FIGURE 8. IOS vs TEMPERATURE (VS = ±18V)
FN8411 Rev.7.00
Aug 16, 2019
Page 10 of 27
ISL70444SEH, ISL73444SEH
Typical Performance Curves Unless otherwise specified, V ±18V, V = 0, V = 0V, T = +25°C. (Continued)
S
CM
O
A
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2.5
2.0
1.5
1.0
0.5
0
I
OS
I
OS
-100
-50
0
50
100
150
-100
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 9. IOS vs TEMPERATURE (VS = ±2.5V)
FIGURE 10. IOS vs TEMPERATURE (VS = ±1.5V)
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
V
OS
V
OS
-100
-50
0
50
100
150
-100
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 11. VOS vs TEMPERATURE (VS = ±18V)
FIGURE 12. VOS vs TEMPERATURE (VS = ±2.5V)
135
130
125
120
115
110
105
100
50
±18V
40
30
20
10
0
V
OS
±1.5V
±2.5V
-75
-25
25
75
125
-100
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 14. AVOL vs TEMPERATURE vs SUPPLY VOLTAGE
FIGURE 13. VOS vs TEMPERATURE (VS = ±1.5V)
FN8411 Rev.7.00
Aug 16, 2019
Page 11 of 27
ISL70444SEH, ISL73444SEH
Typical Performance Curves Unless otherwise specified, V ±18V, V = 0, V = 0V, T = +25°C. (Continued)
S
CM
O
A
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
2.5
2.0
1.5
1.0
0.5
0.0
+125°C
+25°C
-55°C
+25°C
-55°C
+125°C
30
0
10
20
40
0
10
20
30
40
+
-
+
-
SUPPLY DIFFERENTIAL (V TO V ) (V)
SUPPLY DIFFERENTIAL (V TO V ) (V)
FIGURE 16. POSITIVE SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 15. NEGATIVE SUPPLY CURRENT vs SUPPLY VOLTAGE
135
135
130
±18V
130
±18V
125
±2.5V
125
±2.5V
120
115
120
115
±1.5V
±1.5V
110
110
105
100
105
100
-75
-25
25
75
125
-75
-25
25
75
125
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 18. PSRR- vs TEMPERATURE vs SUPPLY VOLTAGE
FIGURE 17. PSRR+ vs TEMPERATURE vs SUPPLY VOLTAGE
120
110
70
60
±18V
100
50
±15V
±5V
±18V
90
80
40
30
20
10
0
±1.5V
±2.5V
70
60
50
40
±2.5V
±1.5V
-75
-25
25
75
125
-75
-25
25
75
125
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 20. SHORT-CIRCUIT CURRENT vs TEMPERATURE
FIGURE 19. CMRR vs TEMPERATURE vs SUPPLY VOLTAGE
FN8411 Rev.7.00
Aug 16, 2019
Page 12 of 27
ISL70444SEH, ISL73444SEH
Typical Performance Curves Unless otherwise specified, V ±18V, V = 0, V = 0V, T = +25°C. (Continued)
S
CM
O
A
50
40
30
20
10
0
70
60
50
40
30
20
10
0
R
= 2kΩ
L
R
= 2kΩ
L
R
= 10kΩ
L
R
= 10kΩ
L
R
= OPEN
125
L
R
= OPEN
L
-75
-25
25
75
175
-75
-25
25
75
125
175
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 22. (VS = ±2.5V) VOH vs TEMPERATURE
FIGURE 21. (VS = ±1.5V) VOH vs TEMPERATURE
350
300
250
200
150
100
50
50
40
30
20
10
0
R
= 2kΩ
L
R
= 2kΩ
L
R
= 10kΩ
L
R
= 10kΩ
R = OPEN
L
L
R
= OPEN
125
L
0
-75
-25
25
75
125
175
-75
-25
25
75
175
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 23. (VS = ±18V) VOH vs TEMPERATURE
FIGURE 24. (VS = ±1.5V) VOL vs TEMPERATURE
70
60
50
40
30
20
10
0
350
300
250
200
150
100
50
R
= 2kΩ
L
R
= 2kΩ
L
R
= 10kΩ
L
R
= 10kΩ
L
R
= OPEN
L
R
= OPEN
L
0
-75
-25
25
75
125
175
-75
-25
25
75
125
175
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 26. (VS = ±18V) VOL vs TEMPERATURE
FIGURE 25. (VS = ±2.5V) VOL vs TEMPERATURE
FN8411 Rev.7.00
Aug 16, 2019
Page 13 of 27
ISL70444SEH, ISL73444SEH
Typical Performance Curves Unless otherwise specified, V ±18V, V = 0, V = 0V, T = +25°C. (Continued)
S
CM
O
A
10
10,000
1,000
100
10
1
0.1
0.1
1
0.01
0.1
1
10
100
1k
10k
100k
1
10
100
FREQUENCY (Hz)
1k
10k
100k
FREQUENCY (Hz)
FIGURE 27. INPUT NOISE VOLTAGE SPECTRAL DENSITY (VS = ±18V)
FIGURE 28. INPUT NOISE CURRENT SPECTRAL DENSITY (VS = ±18V)
150
100
50
200
150
100
50
150
100
50
250
200
150
100
50
PHASE
PHASE
0
0
0
0
-50
-50
GAIN
GAIN
-100
-150
-200
-250
-300
-50
-100
-150
-50
-100
-150
-100
-150
-200
-250
SIMULATION
10
SIMULATION
10
0
1k
100k
10M
1G
0
1k
100k
10M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 29. OPEN LOOP FREQUENCY RESPONSE (CL = 0.01pF)
FIGURE 30. OPEN LOOP FREQUENCY RESPONSE (CL = 10pF)
150
100
50
250
150
100
50
250
200
150
100
50
200
150
100
50
PHASE
GAIN
PHASE
GAIN
0
0
0
0
-50
-50
-100
-150
-200
-250
-300
-100
-150
-200
-250
-300
-50
-100
-150
-50
-100
-150
SIMULATION
10
SIMULATION
10
0
1k
100k
10M
1G
0
1k
100k
10M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 31. OPEN LOOP FREQUENCY RESPONSE (CL = 22pF)
FIGURE 32. OPEN LOOP FREQUENCY RESPONSE (CL = 47pF)
FN8411 Rev.7.00
Aug 16, 2019
Page 14 of 27
ISL70444SEH, ISL73444SEH
Typical Performance Curves Unless otherwise specified, V ±18V, V = 0, V = 0V, T = +25°C. (Continued)
S
CM
O
A
250
200
150
100
50
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
-10
100
150
100
50
PHASE
±1.5V
0
±18V
0
-50
GAIN
-100
-150
-200
-250
-300
-50
-100
-150
±2.5V
1M
SIMULATION
10
0
1k
100k
10M
1G
1k
10k
100k
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 33. OPEN LOOP FREQUENCY RESPONSE (CL = 100pF)
FIGURE 34. CMRR vs FREQUENCY
120
110
100
90
70
60
50
G = 1000
40
±1.5V
80
30
G = 100
70
20
60
50
40
30
20
10
0
±18V
G = 10
10
0
-10
-20
-30
-40
-50
G = 1
±2.5V
-10
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 35. PSRR vs FREQUENCY
FIGURE 36. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
20
10
10
0
R
= 10kΩ
F
0
-10
-20
-30
-40
-50
-60
-70
R
R
= 5kΩ
= 2kΩ
= 1kΩ
L
R
= 100Ω
F
R
= 10kΩ
L
L
R
= 1kΩ
-10
-20
-30
F
R
L
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 37. FREQUENCY RESPONSE vs FEEDBACK RESISTANCE (RF)
FIGURE 38. FREQUENCY RESPONSE vs LOAD RESISTANCE
FN8411 Rev.7.00
Aug 16, 2019
Page 15 of 27
ISL70444SEH, ISL73444SEH
Typical Performance Curves Unless otherwise specified, V ±18V, V = 0, V = 0V, T = +25°C. (Continued)
S
CM
O
A
10
10
0
0
12pF
-10
-20
-30
-40
-50
±1.5V
-10
-20
-30
-40
27pF
47pF
68pF
±2.5V
±18V
ACL = 1
R
= 10kΩ
= ±18V
L
S
V
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 39. UNITY GAIN RESPONSE vs LOAD CAPACITANCE
FIGURE 40. FREQUENCY RESPONSE vs SUPPLY VOLTAGE
35
140
130
120
-55°C
±18V
30
25
20
15
10
5
±2.5V
110
100
+125°C
90
80
70
60
50
40
30
20
10
0
±1.5V
+25°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
100
1k
10k
100k
1M
10M
100M
STEP SIZE (V)
FREQUENCY (Hz)
FIGURE 41. CROSSTALK REJECTION
FIGURE 42. SLEW RATE vs STEP SIZE vs TEMPERATURE (VS = ±1.5V)
450
400
80
70
60
50
40
30
20
10
0
-55°C
350
300
+125°C
+25°C
250
+125°C
200
150
100
50
-55°C
+25°C
0
0
5
10
15
20
25
0
1
2
3
4
5
6
STEP SIZE (V)
STEP SIZE (V)
FIGURE 43. SLEW RATE vs STEP SIZE vs TEMPERATURE (VS = ±2.5V)
FIGURE 44. SLEW RATE vs STEP SIZE vs TEMPERATURE (VS = ±18V)
FN8411 Rev.7.00
Aug 16, 2019
Page 16 of 27
ISL70444SEH, ISL73444SEH
Typical Performance Curves Unless otherwise specified, V ±18V, V = 0, V = 0V, T = +25°C. (Continued)
S
CM
O
A
(INPUT)
(INPUT)
200mV/DIV
200mV/DIV
(OUTPUT)
= ±5V
(OUTPUT)
= ±18V
A
R
R
V
= -100
= 1kΩ
= 100kΩ, R = 1kΩ
= 400mV
P-P
A
R
R
V
= -100
= 2kΩ
= 100kΩ, R = 1kΩ
V
V
L
F
V
L
F
S
V
S
G
G
= 400mV
P-P
IN
IN
1µs/DIV
1µs/DIV
FIGURE 45. SATURATION RECOVERY (VS = ±18V)
FIGURE 46. SATURATION RECOVERY (VS = ±5V)
40
V
= ±18V
= 10kΩ
= 1
S
35
30
25
20
15
10
5
R
A
V
(INPUT)
L
V
200mV/DIV
OS-
= 25mV
OUT
P-P
OS+
(OUTPUT)
= -100
A
R
R
V
L
V
= ±2.5V
= 2kΩ
= 100kΩ, R = 1kΩ
S
F
G
V
= 400mV
IN
P-P
0
1
10
CAPACITANCE (pF)
100
1µs/DIV
FIGURE 47. SATURATION RECOVERY (VS = ±2.5V)
FIGURE 48. OVERSHOOT (%) vs LOAD CAPACITANCE
2V/DIV, INPUT
V
V
= ±5V
= 12V
2V/DIV, OUTPUT
10µs/DIV
S
No Output Phase Reversal
IN
P-P
FIGURE 49. INPUT OVERDRIVE RESPONSE
FN8411 Rev.7.00
Aug 16, 2019
Page 17 of 27
ISL70444SEH, ISL73444SEH
Post High Dose Rate Radiation Characteristics Unless otherwise specified, VS ±18V, VCM = 0,
VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a high dose rate of 50 to 300rad(Si)/s (ISL70444SEH only). This data
is intended to show typical parameter shifts due to high dose rate radiation. These are not limits nor are they guaranteed.
30
30
V
= ±18V
V = ±18V
S
S
GROUNDED
20
20
GROUNDED
10
10
0
0
BIASED
-10
-20
-30
-10
-20
-30
BIASED
0
50
100
150
200
250
300
0
50
100
150
200
250
300
krad (Si)
krad (Si)
FIGURE 51. IBIAS SHIFT vs HIGH DOSE RATE RADIATION
FIGURE 50. VOS SHIFT vs HIGH DOSE RATE RADIATION
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
V
= ±18V
S
V
= ±18V
S
BIASED
GROUNDED
GROUNDED
-0.2
-0.4
-0.6
-0.8
-0.2
-0.4
-0.6
-0.8
BIASED
0
50
100
150
200
250
300
0
50
100
150
200
250
300
krad (Si)
krad (Si)
FIGURE 52. I- SHIFT vs HIGH DOSE RATE RADIATION
FIGURE 53. I+ SHIFT vs HIGH DOSE RATE RADIATION
2.0
1.5
1.0
0.5
0
V
= ±18V
S
BIASED
-0.5
GROUNDED
-1.0
-1.5
-2.0
0
50
100
150
200
250
300
krad (Si)
FIGURE 54. IOS SHIFT vs HIGH DOSE RATE RADIATION
FN8411 Rev.7.00
Aug 16, 2019
Page 18 of 27
ISL70444SEH, ISL73444SEH
Post Low Dose Rate Radiation Characteristics Unless otherwise specified, VS ±18V, VCM = 0,
VO = 0V, TA = +25°C. This data is typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This data is intended to show typical
parameter shifts due to high dose rate radiation. These are not limits nor are they guaranteed.
30
30
20
10
0
V
= ±18V
V
= ±18V
S
S
20
GROUNDED
BIASED
BIASED
10
0
-10
-20
-30
-10
-20
-30
GROUNDED
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
100
krad (Si)
krad (Si)
FIGURE 55. VOS SHIFT vs LOW DOSE RATE RADIATION
FIGURE 56. IBIAS SHIFT vs LOW DOSE RATE RADIATION
0.8
0.6
6
4
V
= ±18V
V
= ±18V
S
S
0.4
0.2
0
BIASED
2
GROUNDED
BIASED
0
-0.2
-0.4
-0.6
-0.8
GROUNDED
-2
-4
-6
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
100
krad (Si)
krad (Si)
FIGURE 58. I+ SHIFT vs LOW DOSE RATE RADIATION
FIGURE 57. IOS SHIFT vs LOW DOSE RATE RADIATION
0.8
0.6
V
= ±18V
S
BIASED
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
GROUNDED
0
10
20
30
40
50
60
70
80
90
100
krad (Si)
FIGURE 59. I- SHIFT vs LOW DOSE RATE RADIATION
FN8411 Rev.7.00
Aug 16, 2019
Page 19 of 27
ISL70444SEH, ISL73444SEH
not violated. This applies to only one amplifier at a given time.
Continued use of the device in these conditions may degrade the
long term reliability of the part and is not recommended.
Figure 20 shows the typical short-circuit currents that can be
expected. The ISL7x444SEH’s current limiting circuitry
automatically lowers the current limit of the device if short-circuit
conditions carry on for extended periods of time. This protects
the device from malfunction; however, extended operation in this
mode degrades the output rail-to-rail performance by increasing
the VOH/VOL levels.
Applications Information
Functional Description
The ISL7x444SEH contain four high-speed and low-power op amps
designed to take advantage of their full dynamic input and output
voltage range with rail-to-rail operation. By offering low power, low
offset voltage and low temperature drift coupled with its high
bandwidth and enhanced slew rates upwards of 50V/µs, these op
amps are ideal for applications requiring both high DC accuracy
and AC performance. The ISL7x444SEH are manufactured using
the Renesas PR40 silicon-on-insulator process, which makes
these devices immune to single event latch-up and provides
excellent radiation tolerance. These features make the devices an
ideal choice for high reliability applications in harsh radiation-
prone environments.
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. The ISL7x444SEH are immune to output phase reversal,
even when the input voltage is 1V beyond the supplies. This is
illustrated in Figure 49 on page 17.
Operating Voltage Range
The ISL7x444SEH are designed to operate with a split supply rail
from ±1.35V to ±20V or a single supply rail from 2.7V to 40V. The
ISL7x444SEH are fully characterized in production for supply rails
of 5V (±2.5V) and 36V (±18V). The power supply rejection ratio is
typically 120dB over the full operating voltage range. The worst
case Common-Mode Rejection Ratio (CMRR) across temperature
is within 1.5V to 2V of each rail. When VCM is inside that range, the
CMRR performance is typically >110dB with a ±18V supply. The
minimum CMRR performance across the -55°C to +125°C
temperature range and radiation is >70dB over the full
common-mode input range for power supply voltages from ±2.5V
(5V) to ±18V (36V).
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperature under certain load and power supply conditions. It is
therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if power
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating range. These
parameters are related using Equation 1:
(EQ. 1)
T
= T
+
x PD
JA MAXTOTAL
JMAX
MAX
where:
• PDMAXTOTAL is the sum of the maximum power dissipation of
Input Performance
each amplifier in the package (PDMAX
)
The slew enhanced front-end is a block that is placed in parallel
with the main input stage and functions based on the input
differential.
• Calculate PDMAX for each amplifier using Equation 2:
V
OUTMAX
R
L
----------------------------
PD
= V I
+ V - V
OUTMAX
(EQ. 2)
MAX
S
qMAX
S
Input ESD Diode Protection
where:
The input terminals (IN+ and IN-) have internal ESD protection
diodes to the positive and negative supply rails, series connected
600Ω current limiting resistors and an anti-parallel diode pair
across the inputs.
• TMAX = Maximum ambient temperature
• JA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of one amplifier
• VS = Total supply voltage
+
V
• IqMAX = Maximum quiescent supply current of one amplifier
• VOUTMAX = Maximum output voltage swing of the application
600Ω
600Ω
V
OUT
Slew Rate Enhancement
V
R
IN
L
The ISL7x444SEH have slew enhanced front-end that increases
the drive on the output transistors proportional to the differential
voltage across the inputs. This increase in output drive shows up
as increased transient current on top of the op amp’s steady
state supply current. If the voltage differential between the
inputs remains constant, as in comparator applications, the
added drive current to the output transistors becomes steady
state and increases the DC power supply current of the IC. For
this reason, we do not recommended using the ISL7x444SEH in
a comparator configuration.
-
V
FIGURE 60. INPUT ESD DIODE CURRENT LIMITING, UNITY GAIN
Output Short-Circuit Current Limiting
The output current limit has a worst case minimum limit of
±8mA but may reach as high as ±100mA. The op amp can
withstand a short-circuit to either rail for a short duration
(<1s) as long as the maximum operating junction temperature is
FN8411 Rev.7.00
Aug 16, 2019
Page 20 of 27
ISL70444SEH, ISL73444SEH
Unused Channel Configuration
V+
If the application does not require the use of all four op amps,
you must configure the unused channels to prevent it from
oscillating. Any unused channels oscillate if the input and output
pins are floating. The oscillationresults in higher than expected
supply currents and possible noise injection into any of the active
channels in use. The proper way to prevent oscillation is to short
the output to the inverting input and tie the positive input to a
known voltage, such as mid-supply.
V-
FIGURE 61. PREVENTING OSCILLATIONS IN UNUSED CHANNELS,
SPLIT SUPPLY
-
When the V supply is less than or equal to -1.0V, configure your
op amp as in Figure 61, or follow the configuration shown in
Figure 62. The resistors in Figure 62 are of equal value and high
resistance (≥10kΩ) to minimize current draw, while keeping the
positive input at mid-supply. All unused op amps can have their
inputs tied to the same resistor divider to minimize the number
of components.
V+
V-
-
Tying the positive input to ground in Figure 62 (where V = GND)
would produce a voltage differential across the inputs, as the
inverting input would be at the op amp’s VOL and the positive
input would be at GND, causing an increase in the steady state
supply current. While this does not damage the op amp, the
increased supply current would result in additional unnecessary
power dissipation.
FIGURE 62. PREVENTING OSCILLATIONS IN UNUSED CHANNELS,
SINGLE SUPPLY
FN8411 Rev.7.00
Aug 16, 2019
Page 21 of 27
ISL70444SEH, ISL73444SEH
Die Characteristics
Assembly Related Information
SUBSTRATE POTENTIAL
Die Dimensions
Floating
2410µm x 3175µm (95 mils x 125 mils)
Thickness: 483µm ±25µm (19 mils ±1 mil)
Additional Information
Interface Materials
WORST CASE CURRENT DENSITY
< 2 x 105 A/cm2
GLASSIVATION
Type: Nitrox
Thickness: 15kÅ
TRANSISTOR COUNT
730
TOP METALLIZATION
Weight of Packaged Device
Type: AlCu (99.5%/0.5%)
Thickness: 30kÅ
0. 5952 grams (Typical)
BACKSIDE FINISH
Lid Characteristics
Silicon
Finish: Gold
Potential: Unbiased, tied to E-pad under package
Case Isolation to Any Lead: 20 x 109 Ω (min)
PROCESS
PR40
Metallization Mask Layout
FN8411 Rev.7.00
Aug 16, 2019
Page 22 of 27
ISL70444SEH, ISL73444SEH
TABLE 1. DIE LAYOUT X-Y COORDINATES
BOND WIRES
PER PAD
PAD NAME
OUTB
OUTC
-INC
PAD NUMBER
X (µm)
599.0
1472.0
2071.0
2071.0
2071.0
2071.0
2071.0
1472.0
599.0
0.0
Y (µm)
-11.5
dX (µm)
70
dY (µm)
70
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
-11.5
70
70
4
0.0
70
70
+INC
V-
12
20
21
22
23
24
25
33
41
42
1
347.5
70
70
1406.5
2465.5
2813.0
2824.5
2824.5
2813.0
2465.5
1406.5
347.5
70
70
+IND
-IND
70
70
70
70
OUTD
OUTA
-INA
70
70
70
70
70
70
+INA
V+
0.0
70
70
0.0
70
70
+INB
-INB
0.0
70
70
0.0
0.0
70
70
NOTE:
9. Origin of coordinates is the centroid of pad 42, “IN-B”.
FN8411 Rev.7.00
Aug 16, 2019
Page 23 of 27
ISL70444SEH, ISL73444SEH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure
that you have the latest revision.
DATE
REVISION
FN8411.7
CHANGE
Aug 16, 2019
Updated SEE and TID ratings in Features section.
Added radiation levels to ordering information table.
Removed Table 1.
Mar 28, 2019
Jan 19, 2018
Jul 6, 2017
FN8411.6
FN8411.5
FN8411.4
Updated links throughout document.
Added ISL73444SEH information throughout document.
Added Table 1.
Updated Disclaimer.
Added “Slew Rate Enhancement” section on page 20.
On page 21 - Updated “Unused Channel Configuration” section, updated Figure 61 and added Figure 62.
Removed “About Intersil” section.
Added new disclaimer.
Updated Related Literature section.
Changed low input voltage from 300µV to 400µV in features list.
Added Notes 3 and 4.
Electrical Specification updates:
VS = ±18V table:
Updated Offset Voltage from “300” to “400” and “400” to “500”.
Updated Input Offset Current from “-17” to “-30” (min) and “17” to “30” (max) unbolded values.
Added another Input Offset Current line and bolded.
Updated PSRR min from “88” to “83”
VS = ±2.5V table:
Updated Offset Voltage from “300” to “400” and “400” to “500”.
Updated Input Offset Current from “-17” to “-30” (min) and “17” to “30” (max) unbolded values.
Added another Input Offset Current line and bolded.
Unbolded PSRR min value and added a new line with 70 min bolded.
VS = ±1.5V table:
Updated Offset Voltage from “300” to “400” and “400” to “500”.
Updated Input Offset Current from “-17” to “-30” (min) and “17” to “30” (max) unbolded values.
Added another Input Offset Current line and bolded.
VS = ±18V table (RAD):
Updated Offset Voltage from “400” to “500”.
Updated Input Offset Current from “-17” to “-50” (min) and “17” to “50” (max).
Updated PSRR min from “88” to “83”
VS = ±2.5V table (RAD):
Updated Offset Voltage from “400” to “500”.
Updated Input Offset Current from “-17” to “-50” (min) and “17” to “50” (max).
VS = ±1.5V table (RAD):
Updated Offset Voltage from “400” to “500”.
Updated Input Offset Current from “-17” to “-50” (min) and “17” to “50” (max).
Jun 5, 2015
FN8411.3
Changed Die Dimensions on page 22:
From
2410µm x 3175µm (80mils x 101mils)
Thickness: 483µm ± 25µm (19mils ± 1 mil)
To:
Die Dimensions
2410µm x 3175µm (95mils x 125mils)
Thickness: 483µm ± 25µm (19mils ± 1 mil)
Jul 31, 2014
FN8411.2
On page 1: Updated Features bullet from:
- SEL/SEB LETTH. . . . . . . . . . . . . . . . . . . . 86.4MeVocm2/mg
To:
- SEB LETTH (VS = ±21V). . . . . . . . . . . . . . . . 86.4 MeV/mg/cm2
- SEL Immune (SOI Process)
Ordering Information table on page 4: Removed MSL note.
Updated About Intersil verbiage.
FN8411 Rev.7.00
Aug 16, 2019
Page 24 of 27
ISL70444SEH, ISL73444SEH
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure
that you have the latest revision. (Continued)
DATE
REVISION
FN8411.1
CHANGE
Jun 14, 2013
Changed Radiation tolerance High dose rate from 100krad(Si) to 300krad(Si) on page 1 features and in
Electrical Spec Table conditions on pages 7 and 8.
Added SR spec for VS = ±18V to Electrical Spec Table on page 8.
Removed Max limit of 300 for VOS Offset Voltage in VS = ±18V, VS = ±2.5V and VS = ±1.5V Spec tables.
May 23, 2013
FN8411.0
Initial Release.
FN8411 Rev.7.00
Aug 16, 2019
Page 25 of 27
ISL70444SEH, ISL73444SEH
For the most recent package outline drawing, see K14.C.
Package Outline Drawing
K14.C
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Rev 0, 9/12
A
A
0.050 (1.27 BSC)
PIN NO. 1
ID AREA
0.390 (9.91)
0.376 (9.55)
1
TOP VIEW
0.022 (0.56)
0.015 (0.38)
0.005 (0.13)
MIN
3
0.115 (2.92)
0.009 (0.23)
0.004 (0.10)
-D-
0.045 (1.14)
0.085 (2.16)
5
0.260 (6.60)
0.248 (6.30)
0.026 (0.66)
-H-
0.370 (9.40)
0.270 (6.86)
0.03 (0.76) MIN
-C-
0.183 (4.65)
0.167 (4.24)
BOTTOM
METAL
6
SEATING AND
BASE PLANE
SIDE VIEW
BOTTOM METAL
0.005 (0.127) REF.
OFFSET FROM
CERAMIC EDGE
OPTIONAL
PIN 1 INDEX
BOTTOM VIEW
NOTES:
Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark.
1.
0.006 (0.15)
0.004 (0.10)
LEAD FINISH
2. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
3. Measure dimension at all four corners.
0.009 (0.23)
0.004 (0.10)
BASE
METAL
4. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
0.019 (0.48)
0.015 (0.38)
5. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
0.0015 (0.04)
MAX
0.022 (0.56)
0.015 (0.38)
6. The bottom of the package is a solderable metal surface.
7. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
8. Dimensions: INCH (mm). Controlling dimension: INCH.
2
SECTION A-A
FN8411 Rev.7.00
Aug 16, 2019
Page 26 of 27
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