5962L0924402VHA [ADI]
Aerospace High Voltage Current Shunt Monitor;
| 型号： | 5962L0924402VHA |
| 厂家： | 
ADI |
| 描述： | Aerospace High Voltage Current Shunt Monitor 放大器 |
| 文件： | 总19页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
REVISIONS
LTR
A
DESCRIPTION
DATE (YR-MO-DA)
12-02-08
APPROVED
C. SAFFLE
Add device type 02 tested at low dose rate. Make changes to paragraphs
1.2.2, 1.5, 4.4.1c, 4.4.4.1, Table I and figure 1. - ro
Add single event latchup (SEL) testing information. Delete device class M
references. - ro
B
13-06-13
C. SAFFLE
REV
SHEET
REV
B
B
B
B
SHEET
15
16
17
18
REV STATUS
OF SHEETS
PMIC N/A
REV
SHEET
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
B
9
B
B
B
B
B
10
11
12
13
14
PREPARED BY
RICK OFFICER
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
STANDARD
MICROCIRCUIT
DRAWING
CHECKED BY
RAJESH PITHADIA
APPROVED BY
CHARLES F. SAFFLE
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
MICROCIRCUIT, LINEAR, HIGH VOLTAGE,
CURRENT SHUNT MONITOR, MONOLITHIC
SILICON
DRAWING APPROVAL DATE
10-12-16
REVISION LEVEL
B
SIZE
A
CAGE CODE
AMSC N/A
5962-09244
67268
SHEET
1 OF 18
DSCC FORM 2233
APR 97
5962-E445-13
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and
space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or
Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
R
09244
01
V
H
A
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
01
Generic number
AD8212
Circuit function
Radiation hardened, high voltage,
current shunt monitor
02
AD8212
Radiation hardened, high voltage,
current shunt monitor
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Q or V
Device requirements documentation
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
H
Descriptive designator
GDFP1-F10
Terminals
10
Package style
Flat pack
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V.
SIZE
STANDARD
5962-09244
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
B
SHEET
COLUMBUS, OHIO 43218-3990
2
DSCC FORM 2234
APR 97
1.3 Absolute maximum ratings. 1/
Supply voltage (V to COM) ........................................................................................................ 68 V
S
I
voltage ................................................................................................................................. V to COM - 5.2 V
S
OUT
Reverse supply voltage (V to COM)............................................................................................ -0.3 V
S
Power dissipation (P ) ................................................................................................................. 8 mW
D
Output short circuit duration ......................................................................................................... Indefinite
Maximum junction temperature (T ) ............................................................................................. 150°C
J
Lead temperature (soldering, 10 seconds) ................................................................................... 300°C
Storage temperature range .......................................................................................................... -65°C to +150°C
Thermal resistance, junction-to-case (θ ) .................................................................................. 56°C/W 2/
JC
Thermal resistance, junction-to-ambient (θ ) ............................................................................. 93°C/W 2/
JA
1.4 Recommended operating conditions.
Supply voltage (V to COM) ........................................................................................................ 7 V to 65 V 3/
S
Ambient operating temperature range (T ) .................................................................................. -55°C to +125°C
A
1.4.1 Operating performance characteristics.
Input / output characteristics: (T = +25°C, +V to COM = 15 V)
A
S
Input impedance differential ...................................................................................................... 2 kΩ
Input impedance common mode (+V to COM = 7 V to 65 V) ................................................. 5 MΩ
S
Output impedance .................................................................................................................... 20 MΩ
Input to output transconductance ............................................................................................. 1000 µA / V
Dynamic response: (T = +25°C, +V to COM = 15 V) 4/
A
S
Small signal bandwidth - 3dB (Gain = 10) ................................................................................ 1000 kHz
Small signal bandwidth - 3dB (Gain= 20) ................................................................................. 500 kHz
Small signal bandwidth - 3dB (Gain = 50) ................................................................................ 100 kHz
Noise performance: (T = +25°C, +V to COM = 15 V)
A
S
Voltage noise (referred to input (RTI), f = 0.1 Hz to 10 Hz) ...................................................... 1.1 µVp-p
Voltage noise (referred to input (RTI), special density, f = 1 kHz) ............................................ 40 nV / Hz
______
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability. Note COM and BIAS pins can be treated as essentially
the same voltage for absolute maximum ratings.
2/ Measurement taken under absolute worse case condition of still air. Data taken with a thermal camera for highest power
density location. See MIL-STD-1835 for average package θ thermal numbers.
JC
3/ This device has high voltage operation which is achieved by using external voltage breakdown PNP transistor.
In this configuration, the common mode range of the device is equal to the breakdown of the external PNP transistor.
Refer to section 6.7 for more information.
4/ External input filtering should be considered to trade off desired dynamic response versus undesired response to system
transients and electromagnetic interference (EMI). Refer to section 6.7 for more information.
SIZE
STANDARD
5962-09244
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
B
SHEET
COLUMBUS, OHIO 43218-3990
3
DSCC FORM 2234
APR 97
1.5 Radiation features.
Maximum total dose available (dose rate = 50 – 300 rads(Si)/s):
Device type 01 ............................................................................................................................. 100 krads(Si) 5/
Maximum total dose available (dose rate ≤ 10 mrads(Si)/s) :
Device type 02 ............................................................................................................................. 50 krads(Si) 6/
Single event phenomenon (SEP):
2
No single event latchup (SEL) occurs at effective linear energy transfer (LET) (see 4.4.4.2)....... ≤ 80 MeV-cm /mg 7/
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883
-
Test Method Standard Microcircuits.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://quicksearch.dla.mil or from the Standardization Document Order
Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation or contract.
ASTM INTERNATIONAL (ASTM)
ASTM F1192 – Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion
Irradiation of Semiconductor Devices.
(Copies of this document is available online at http://www.astm.org/ or from ASTM International, P.O. Box C700,
100 Bar Harbor Drive, West Conshohocken, PA 19428-2959).
_____
5/ Device type 01 may be dose rate sensitive in a space environment and may demonstrate enhanced low dose rate effects.
Radiation end point limits for the noted parameters are guaranteed only for the conditions specified in MIL-STD-883,
method 1019, condition A.
6/ For device type 02, radiation end point limits for the noted parameters are guaranteed for the conditions specified in
MIL-STD-883, method 1019, condition D.
7/ Limits are characterized at initial qualification and after any design or process changes that may affect the SEP
characteristics, but are not production lot tested unless specified by the customer through the purchase order or contract.
For more information on single event effect (SEE) test results, customers are requested to contact the manufacturer.
SIZE
STANDARD
5962-09244
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
B
SHEET
COLUMBUS, OHIO 43218-3990
4
DSCC FORM 2234
APR 97
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 as specified herein, or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein.
3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Block diagram. The block diagram shall be as specified on figure 2.
3.2.4 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document
revision level control and shall be made available to the preparing and acquiring activity upon request.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the
full ambient operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table IA.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance
submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the
manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall
be provided with each lot of microcircuits delivered to this drawing.
SIZE
STANDARD
5962-09244
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
B
SHEET
COLUMBUS, OHIO 43218-3990
5
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics.
Test
Symbol
Conditions 1/ 2/
Group A
subgroups
Device
type
Limits
Unit
-55°C ≤ T ≤ +125°C
A
V
to COM = 7 V to 65 V
Min
Max
720
S
unless otherwise specified
I
= I + I
,
S
OUT BIAS
Total supply current 3/
1,2,3
01, 02
µA
I
S
7 V ≤ +V ≤ 65 V,
S
(normal operation)
M,D,P,L,R
M,D,P,L
4/
1
1
01
02
720
720
I
= I
OUT
+ I ,
BIAS
S
1,2,3
01,02
1500
high voltage operation, using
external PNP transistor
M,D,P,L,R
M,D,P,L
1
1
01
02
1500
1500
Voltage offset section
Offset voltage
Gain = 1
1
2,3
1
01,02
-2
-3
-2
-2
+2
+3
+2
+2
mV
V
OS
M,D,P,L,R
M,D,P,L
01
02
1
∆V
∆T
/
OS
Offset voltage drift
Input section
Gain = 1
5/
2,3
01,02
-10
+10
µV / °C
Input voltage between +V and
S
Differential input voltage range
1,2,3
01,02
0
500
mV
V
IN
V
SENSE
M,D,P,L,R
M,D,P,L
1
1
01
02
0
0
500
500
See footnotes at end of table.
SIZE
STANDARD
5962-09244
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
B
SHEET
COLUMBUS, OHIO 43218-3990
6
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics – Continued.
Conditions 1/ 2/
-55°C ≤ T ≤ +125°C
unless otherwise specified
Test
Symbol
Group A
subgroups
Device
type
Limits
Max
Unit
A
Min
Input section – continued.
7 V ≤ +V ≤ 65 V,
S
1,2,3
01,02
200
nA
V
input pin current
I
SENSE
SENSE
(normal operation)
M,D,P,L,R
M,D,P,L
1
1
01
02
200
200
3/ 4/ 6/
High voltage operation,
using external PNP
transistor
1,2,3
01,02
1000
M,D,P,L,R
M,D,P,L
1
1
01
02
1000
1000
Output section
Output current range 3/
1,2,3
01,02
01
0
0
0
500
500
500
µA
I
V
= 0 mV to 500 mV
OUT
IN
M,D,P,L,R
M,D,P,L
= R = 1 kΩ,
1
1
02
R
7/
shunt
L
Circuit gain
G
1,2,3
01,02
0.99
1.01
V / V
V
IN
= 50 mV and 500 mV
M,D,P,L,R
1
1
01
02
0.99
0.99
1.01
1.01
M,D,P,L
+V to COM regulator section
S
Regulator voltage
1,2,3
01,02
01
4.80
4.80
4.80
5.20
5.20
5.20
V
V
REG
M,D,P,L,R
M,D,P,L
1
1
02
Regulator power supply
rejection ratio
PSRR
1,2,3
01,02
-100
100
µV/V
∆V
/ ∆+V
S
REG
M,D,P,L,R
M,D,P,L
1
1
01
02
-100
-100
100
100
See footnotes at end of table.
SIZE
STANDARD
5962-09244
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
B
SHEET
COLUMBUS, OHIO 43218-3990
7
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics – Continued.
Test
Symbol
Conditions 1/ 2/
Group A
subgroups
Device
type
Limits
Unit
-55°C ≤ T ≤ +125°C
A
V
to COM = 7 V to 65 V
Min
Max
220
S
unless otherwise specified
+V to COM regulator section - continued.
S
7 V ≤ +V ≤ 65 V
S
Bias current 3/
1,2,3
01,02
µA
I
BIAS
(normal operation)
M,D,P,L,R
1
1
01
02
220
220
M,D,P,L
High voltage operation 4/ 6/
using external PNP transistor
1,2,3
01,02
200
1000
M,D,P,L,R
M,D,P,L
1
1
01
02
200
200
1000
1000
Minimum ALPHA pin input
current
8/
1,2,3
1
01,02
01
25
µA
µs
I
t
ALPHA
S_rise
M,D,P,L,R
M,D,P,L
25
25
1
02
Rising step response settling
time
9,10,11
01,02
2.2
V
S
= 0 - 15 V,
5/ 9/
R
Shunt
= 1 kΩ, G = 20,
V
= 0 m V - 500 mV,
IN
SR = 23 V/µs,
settling to 1%,
V
OUT
see 4.4.1c
Falling step response settling
time
9,10,11
01,02
1.5
µs
t
V
= 15 - 0 V,
5/ 9/
= 1 kΩ, G = 20,
S_fall
S
R
Shunt
V
= 500 mV - 0 mV,
IN
SR = 23 V/µs,
settling to 1%,
V
OUT
see 4.4.1c
See footnotes at end of table.
SIZE
STANDARD
5962-09244
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
B
SHEET
COLUMBUS, OHIO 43218-3990
8
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics – Continued.
1/ Device type 01 supplied to this drawing has been characterized through all levels M, D, P, L, and R of irradiation.
Device type 02 supplied to this drawing has been characterized through all levels M, D, P, L of irradiation.
However, device type 01 is only tested at the "R" level and device type 02 is only tested at the “L” level.
Pre and Post irradiation values are identical unless otherwise specified in table IA. When performing post irradiation
electrical measurements for any RHA level, T = +25°C.
A
2/ Device type 01 may be dose rate sensitive in a space environment and may demonstrate enhanced low dose rate effects.
Radiation end point limits for the noted parameters are guaranteed only for the conditions specified in MIL-STD-883,
method 1019, condition A for device type 01 and condition D for device type 02.
Device type 02 has been tested at low dose rate.
3/ The device supply current in normal voltage operation (+V = 7 V to 65 V) is the bias current (I
) added to output
). Output current varies upon input differential voltage and can range from 0 µA to 500 µA. For high voltage
S
BIAS
current (I
OUT
operation mode with an external PNP transistor, refer to section 6.7 for more information.
4/ Maximum +V voltage to COM dependent in the collector emitter voltage breakdown of the transistor. R
BIAS
must be
S
selected to ensure I
information.
within specification via I
BIAS
= ( +V - V ) / R
. Refer to section 6.7 for more
BIAS
BIAS
S
REGmax
5/ Parameter not tested post irradiation.
6/ The current of the amplifier into V
pin increases when operating in high voltage external PNP transistor configuration
mode. Refer to section 6.7 for more information.
SENSE
7/ Gain measured by ( V
at 500 mV - V
OUT
at 50 mV ) / ( V at 500 mV - V at 50 mV ).
IN IN
OUT
8/ The ALPHA pin current in the high voltage operation using external PNP mode equals the I base current of the external
B
PNP transistor. The I maximum current must not exceed this minimum I
ALPHA
specification.
B
9/ Subgroups 9, 10, and 11 are tested initially as part of device characterization, after subsequent wafer lots and as part of
design and process changes.
TABLE IB. SEP test limits. 1/
Effective linear energy
Device type
01, 02
SEP
Temperature
Bias V
S
transfer (LET)
2
No SEL
+125°C
±30 V
LET ≤ 80 MeV-cm /mg
1/ For single event phenomenon (SEP) test conditions, see 4.4.4.2 herein.
SIZE
STANDARD
5962-09244
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
B
SHEET
COLUMBUS, OHIO 43218-3990
9
DSCC FORM 2234
APR 97
Device types
Case outline
01 and 02
H
Terminal
number
Terminal
symbol
Description
1
2
Supply voltage (inverting amplifier input).
Regulator low side.
+V
S
COM
BIAS
NC
3
Bias circuit low side.
No connection.
4
5
NC
No connection.
6
NC
No connection.
7
Output current.
I
OUT
8
ALPHA
NC
Current compensation circuit input.
No connection.
9
10
Noninverting amplifier input.
V
SENSE
FIGURE 1. Terminal connections.
SIZE
STANDARD
5962-09244
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
B
SHEET
COLUMBUS, OHIO 43218-3990
10
DSCC FORM 2234
APR 97
FIGURE 2. Block diagram.
SIZE
STANDARD
5962-09244
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
B
SHEET
COLUMBUS, OHIO 43218-3990
11
DSCC FORM 2234
APR 97
4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection.
4.2.1 Additional criteria for device classes Q and V.
a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b. Interim and final electrical test parameters shall be as specified in table IIA herein.
c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections, and as specified herein.
4.4.1 Group A inspection.
a. Tests shall be as specified in table IIA herein.
b. Subgroups 4, 5, 6, 7, and 8 in table I, method 5005 of MIL-STD-883 shall be omitted.
c. Subgroups 9, 10, and 11 are tested initially as part of device characterization, after subsequent wafer lots and as part
of design and process changes.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
SIZE
STANDARD
5962-09244
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
B
SHEET
COLUMBUS, OHIO 43218-3990
12
DSCC FORM 2234
APR 97
TABLE IIA. Electrical test requirements.
Test requirements
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Device
class Q
Device
class V
Interim electrical
1
1
parameters (see 4.2)
Final electrical
1, 2, 3, 1/ 3/
9, 10, 11
1, 2, 3, 1/ 2/ 3/
9,10,11
parameters (see 4.2)
Group A test
1, 2, 3,
9, 10, 11
1, 2, 3
3/
1, 2, 3, 3/
9, 10, 11
requirements (see 4.4)
Group C end-point electrical
parameters (see 4.4)
Group D end-point electrical
parameters (see 4.4)
Group E end-point electrical
parameters (see 4.4)
1, 2, 3 2/
1, 2, 3
---
1, 2, 3
1
1/ PDA applies to subgroup 1.
2/ Delta limits as specified in table IIB shall be required where specified,
and the delta limits shall be completed with reference to the zero hour
electrical parameters (see table IA).
3/ Subgroups 9, 10, and 11 are tested initially as part of device characterization,
after subsequent wafer lots and as part of design and process changes.
TABLE IIB. Burn-in and operating life test delta parameters. T = +25°C. 1/ 2/
A
Parameters
Bias current
Symbol
Delta limits
Units
±10.00
µA
I
BIAS
(normal operation)
Offset voltage
mV
V/V
±0.40
V
OS
Gain
G
±0.0032
1/ If device is tested at or below delta limit in table, no deltas are required.
Deltas are performed at room temperature.
2/ Delta parameters are performed at normal operation 7 V supply, normal
operation 65 V supply, and with external PNP operation mode.
SIZE
STANDARD
5962-09244
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
B
SHEET
COLUMBUS, OHIO 43218-3990
13
DSCC FORM 2234
APR 97
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a. End-point electrical parameters shall be as specified in table IIA herein.
b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. All device classes must meet the postirradiation end-point
electrical parameter limits as defined in table IA at T = +25°C ±5°C, after exposure, to the subgroups specified in
A
table IIA herein.
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883
method 1019 condition A for device type 01 and condition D for device type 02 and as specified herein.
4.4.4.2 Single event phenomena (SEP). When specified in the purchase order or contract, SEP testing shall be performed on
class V devices. SEP testing shall be performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as
approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or
latchup characteristics. Test four devices with zero failures. ASTM F1192 may be used as a guideline when performing SEP
testing. The recommended test conditions for SEP are as follows:
a. The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive
(i.e. 0° ≤ angle ≤ 60°). No shadowing of the ion beam due to fixturing or package related effects is allowed.
7
2.
b. The fluence shall be ≥ 10 ions/cm
2
5
2
c. The flux shall be between 10 and 10 ions/cm /s.
d. The particle range shall be ≥ 20 microns in silicon.
e. The test temperature shall be +125°C and the maximum rated operating temperature ±10°C for single event
latchup testing.
f. Bias conditions shall be V
CC
= ±30 V for latchup measurements.
g. For SEP test limits, see Table IB herein.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V.
SIZE
STANDARD
5962-09244
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
B
SHEET
COLUMBUS, OHIO 43218-3990
14
DSCC FORM 2234
APR 97
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires
configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users and
this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108.
6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990,
or telephone (614) 692-0540.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in
MIL-HDBK-103 and QML-38535. The vendors listed in MIL-HDBK-103 and QML-38535 have submitted a certificate of
compliance (see 3.6 herein) to DLA Land and Maritime-VA and have agreed to this drawing.
6.7 Application notes.
6.7.1 Normal operation (7 V to 65 V supply range). In normal applications as shown in figure 3, the device measures a small
differential input voltage generated by a load current flowing through a shunt resistor. The operational amplifier (A1) is
connected across the shunt resistor (R
SHUNT
) with its inverting input connected to the battery/supply side, and the noninverting
input connected to the load side of the system. Amplifier A1 is powered via an internal series regulator (depicted as a zener
diode). This regulator maintains a constant 5 V between the battery/supply terminal of the device and COM, which represents
the lowest common point of the internal circuitry. A load current flowing through the external shunt resistor produces a voltage
at the input terminals of the device. Amplifier A1 responds by causing transistor Q1 to conduct the necessary current through
resistor R1 to equalize the potential at both the inverting and noninverting inputs of amplifier A1.
SIZE
STANDARD
5962-09244
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
B
SHEET
COLUMBUS, OHIO 43218-3990
15
DSCC FORM 2234
APR 97
6.7.1 Normal operation (7 V to 65 V supply range) - continued. The current through the emitter of transistor Q1 (I
) is
OUT
proportional to the input voltage (V
SENSE
), and, therefore, the load current (I
) through the shunt resistor (R
LOAD SHUNT
). The
output current (I
) is converted to a voltage by using an external resistor, the value of which is dependent on the input to
OUT
output gain equation desired in the application.
The transfer function for the device is:
I
= (gm × V ) where: gm = 1000 μA / V.
SENSE
OUT
V
V
V
= I
× R
SHUNT
,
SENSE
LOAD
= I
× R
,
OUT
OUT
OUT
OUT
= (V
× R
) / 1000
SENSE
OUT
When using the device as described, the battery / supply voltage (+V) in the system must be between 7 V to 65 V. The 7 V
minimum supply range is necessary to turn on the internal regulator (shown as a zener). This regulated voltage then remains a
constant 5 V, regardless of the supply voltage (+V ). The 65 V maximum limit in this mode of operation is due to the breakdown
S
voltage limitation of the device process. A 1% resistor can be used to convert the output current to a voltage where gain in V/V
is set by R
OUT
in kΩ.
FIGURE 3. Normal configuration circuit.
SIZE
STANDARD
5962-09244
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
B
SHEET
COLUMBUS, OHIO 43218-3990
16
DSCC FORM 2234
APR 97
6.7.2 High voltage operation using an external PNP transistor. In high voltage applications, the device can be configured as
shown in figure 4. The device offers features that simplify measuring current in the presence of common-mode voltages greater
than 65 V. This is achieved by connecting an external PNP transistor at the output of the device, as shown above. The VCE
break-down voltage of this PNP becomes the operating common-mode range of the device. The device features an integrated
5 V series regulator. This regulator ensures that at all times COM, which is the most negative of all the terminals, is always 5 V
less than the supply voltage (+V ). Assuming a battery voltage (+V) of 100 V, it follows that the voltage at COM is
S
(+V) – 5 V = 95 V. The base emitter junction of transistor Q2, in addition to the Vbe of one internal transistor, makes the
collector of transistor Q1 approximately equal to 95 V + 2(Vbe(Q2)) = 95 V + 1.2 V = 96.2 V. This voltage appears across
external transistor Q2. The voltage across transistor Q1 is 100 V – 96.2 V = 3.8 V. In this manner, transistor Q2 withstands
95.6 V and the internal transistor Q1 is only subjected to voltages well below its breakdown capability.
In this mode of operation, the supply current (I
BIAS
) of the device circuit increases based on the supply range and the R
BIAS
resistor chosen. For example if V+ = 500 V and R
BIAS
= 500 kΩ, then, I
= (500 – 5) / 500 kΩ = 990 μA. In high voltage
BIAS
operation, it is recommended that I
BIAS
remain within 200 μA to 1 mA. This ensures that the bias circuit is turned on, allowing
the device to function as expected. At the same time, the current through the bias circuit / regulator is limited to 1 mA.
Transistor Q2 can be a field effect transistor (FET) or a bipolar PNP transistor. The latter is much less expensive, however the
magnitude of I
conducted to the output resistor (R ) is reduced by the amount of current lost through the base of the
OUT
OUT
PNP. This leads to an error in the output voltage reading. The device includes a circuit at the ALPHA pin which compensates
for the output current that is lost through the base of the external PNP transistor. This ensures that the correct
transconductance gain of the amplifier is maintained.
FIGURE 4. High voltage external PNP configuration circuit.
SIZE
STANDARD
5962-09244
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
B
SHEET
COLUMBUS, OHIO 43218-3990
17
DSCC FORM 2234
APR 97
6.7.3 Dynamic response considerations. External input filtering should be considered to trade off desired dynamic response
versus undesired responses to system transients and electromagnetic interference (EMI). External input filtering is achieved by
adding the R / C filter circuit shown in figure 5. With the lower 2 kΩ input differential impedance, the R is recommended to
F
F
F
be in the 5 Ω to 15 Ω range to prevent gain and CMR errors. With a R chosen, the C should be selected to achieve the
F
F
desired low pass filter using the formula: Low pass filter cutoff frequency = 1 / (2 x π x R x C ).
F
F
As an example, with R = 6 Ω and a C = 2.7 µF, the low pass filter (LPF) cutoff frequency will be 10 kHz. The chosen input
F
F
filter cutoff frequency should suppress transients while allowing proper response to expected changes in the sensed current.
EMI suppression can also be achieved by using 1% tolerance capacitors on the +V and +V
inputs to ground.
The capacitors must be matched and values selected based on suppression achieved with the 2 kΩ input differential
S
SENSE
impedance. Use the same low pass filter cutoff frequency equation replacing R with 2 kΩ. The chosen cutoff frequency should
F
implement the EMI suppression while allowing proper response to expected changes in the sensed current.
6.8 Additional information. When applicable a copy of the following additional data shall be maintained and available from the
device manufacturer:
a. RHA test conditions (SEP).
b. Occurrence of latchup (SEL).
FIGURE 5. Input filter circuit.
SIZE
STANDARD
5962-09244
A
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
REVISION LEVEL
B
SHEET
COLUMBUS, OHIO 43218-3990
18
DSCC FORM 2234
APR 97
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 13-06-13
Approved sources of supply for SMD 5962-09244 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DLA Land and Maritime-VA. This information
bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime
maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
Vendor
similar
PIN 2/
number
5962R0924401VHA
5962L0924402VHA
24355
24355
AD8212AL/QMLR
AD8212AL/QMLL
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
Vendor CAGE
number
Vendor name
and address
24355
Analog Devices (4)
Route 1 Industrial Park
P.O. Box 9106
Norwood, MA 02062
Point of contact: 7910 Triad Center Drive
Greensboro, NC 27409-9605
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
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