5962L1121204V9A [RENESAS]
Adjustable Positive LDO Regulator;
| 型号： | 5962L1121204V9A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Adjustable Positive LDO Regulator 输出元件 调节器 |
| 文件： | 总22页 (文件大小：1211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL75051ASEH, ISL73051ASEH
3A, Radiation Hardened, Positive, Ultra-Low Dropout Regulator
FN8964
Rev.3.00
May 16, 2019
The ISL75051ASEH and ISL73051ASEH are radiation
hardened low-voltage, high-current, single-output LDOs
Features
• DLA SMD 5962-11212
specified for up to 3.0A of continuous output current.
These devices operate across an input voltage range of
2.2V to 6.0V and can provide output voltages of 0.8V to
5.0V adjustable, based on the resistor divider setting.
Dropout voltages as low as 65mV can be achieved using
the device.
• Output current up to 3.0A at T = +150°C
J
• Output accuracy ±1.5% over MIL temperature range
• Ultra low dropout:
• 65mV (typical) dropout at 1.0A
The OCP pin allows the short-circuit output current limit
threshold to be programmed by a resistor from the OCP
pin to GND. The OCP setting range is 0.5A minimum to
8.5A maximum. The resistor sets the constant current
threshold for the output under fault conditions. The
thermal shutdown disables the output if the device
temperature exceeds the specified value. It subsequently
enters an ON/OFF cycle until the fault is removed. The
ENABLE feature allows the part to be placed into a low
current shutdown mode that typically draws about 10µA.
• 225mV (typical) dropout at 3.0A
• SET mitigation with no added filtering/diodes
• Input supply range: 2.2V to 6.0V
• Fast load transient response
• Shutdown current of 10µA (typical)
• Output adjustable using external resistors
• PSRR 66dB (typical) at 1kHz
• Enable and PGood features
These devices are optimized for fast transient response and
Single Event Effects (SEE). This reduces the magnitude of
Single Event Transients (SET) seen on the output.
Additional protection diodes and filters are not needed.
These devices are stable with tantalum capacitors as low as
47µF and provide excellent regulation all the way from no
load to full load. Programmable soft-start allows the user
to program the inrush current by using the decoupling
capacitor value on the BYP pin.
• Programmable soft-start/inrush current limiting
• Over-temp shutdown and programmable OCP limits
• Stable with 47µF min tantalum capacitor
• Radiation hardness (ISL75051ASEH only)
• High dose rate (50-300rad(Si)/s): 100krad(Si)
• Low dose rate (≤0.01rad(Si)/s): 50krad(Si)
• Radiation hardness (ISL73051ASEH only)
• Low dose rate (≤0.01rad(Si)/s): 50krad(Si)
Applications
• LDO regulator for space applications
• DSP, FPGA, and µP core power supplies
• Post-regulation of switched mode power supplies
• Down-hole drilling
Related Literature
• For a full list of related documents, visit our website:
• ISL75051ASEH, ISL73051ASEH device pages
0.30
EN
+150°C
EN
BYP
ADJ
ROCP
0.25
0.1µF
OCP
+125°C
ISL75051ASEH
VIN
VOUT
220µF
0.20
VIN
PG
VOUT
GND
R
1
0.15
0.1µF
0.1µF
220µF
+25°C
2.67k
VIN
0.10
0.05
0.00
4.7nF
100pF
R
PG
2
0.00
0.50
1.00
1.50
2.00
(A)
2.50
3.00
3.50
I
OUT
Figure 2. Dropout vs I
Figure 1. Typical Application
OUT
FN8964 Rev.3.00
May 16, 2019
Page 1 of 22
ISL75051ASEH, ISL73051ASEH
Contents
1.
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
1.2
1.3
1.4
1.5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Typical Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
2.2
2.3
2.4
2.5
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Radiation Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.
4.
Typical Operating Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Input Voltage Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Adjustable Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input and Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power-Good. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Current Limit Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Thermal Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.
6.
7.
8.
Die and Layout Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Metallization Mask Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FN8964 Rev.3.00
May 16, 2019
Page 2 of 22
ISL75051ASEH, ISL73051ASEH
1. Overview
1. Overview
1.1
Block Diagram
VIN
Current
Limit ADJ
OCP
520mV
Power
PMOS
Reference
Bias
BYPASS
VOUT
Current
Limit
Thermal
Shutdown
Level
Shift
ENABLE
VADJ
PGOOD
Delay
450mV
GND
Figure 3. Block Diagram
1.2
Typical Application
EN
EN
10
11
BYP
9
8
511
OCP
ADJ
0.2µF
VIN
VIN
VIN
12
13
14
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
GND
7
6
5
4
3
VIN
VIN
VIN
PG
15
16
17
VIN
VOUT
220µF
2
1
18
0.1µF
0.1µF
220µF
2.67k
4.7n
4.32k
2.26k
VIN
100pF
5.49k
PG
Figure 4. Typical Application
FN8964 Rev.3.00
May 16, 2019
Page 3 of 22
ISL75051ASEH, ISL73051ASEH
1. Overview
1.3
Ordering Information
Ordering SMD Number
Temp Range
(°C)
Package
(RoHS Compliant)
Pkg
Dwg. #
(Notes 1, 2)
Part Number
ISL75051ASEHVF
5962R1121203VXC
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
Evaluation Board
18 Ld CDFP
K18.D
K18.D
N/A
ISL75051ASEHF/PROTO (Note 3)
ISL75051ASEHVX
18 Ld CDFP
Die
5962R1121203V9A
5962R1121203VYC
ISL75051ASEHVFE
18 Ld CDFP with Bottom METAL K18.E
N/A
ISL75051ASEHFE/PROTO (Note 3)
ISL75051ASEHX/SAMPLE (Note 3)
ISL73051ASEHVF
18 Ld CDFP with Bottom Metal
Die Sample
K18.E
N/A
5962L1121204VXC
18 Ld CDFP
K18.D
K18.D
N/A
ISL73051ASEHF/PROTO (Note 3)
ISL73051ASEHVX
18 Ld CDFP
5962L1121204V9A
Die
5962L1121204VYC
ISL73051ASEHVFE
18 Ld CDFP with Bottom Metal
18 Ld CDFP with Bottom Metal
Die Sample
K18.E
K18.E
N/A
ISL73051ASEHFE/PROTO (Note 3)
ISL73051ASEHX/SAMPLE (Note 3)
ISL75051ASEHEV1Z (Note 4)
N/A
N/A
Notes:
1. These Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible
with both SnPb and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed must be used when ordering.
3. The /PROTO and /SAMPLE are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity. These
parts are intended for engineering evaluation purposes only. The /PROTO parts meet the electrical limits and conditions across the
temperature range specified in the DLA SMD and are in the same form and fit as the qualified device. The /SAMPLE die is capable
of meeting the electrical limits and conditions specified in the DLA SMD at +25°C only. The /SAMPLE is a die and does not receive
100% screening across the temperature range to the DLA SMD electrical limits. These part types do not come with a certificate of
conformance because there is no radiation assurance testing and they are not DLA qualified devices.
4. Evaluation board uses the /PROTO parts. The /PROTO parts are not rated or certified for Total Ionizing Dose (TID) or Single Event
Effect (SEE) immunity.
Table 1. Key Differences Between Family of Parts
Part Numbers
TID Ratings
ISL75051ASEH
HDR to 100krad(Si) RHA Tested
LDR to 50krad(Si) RHA Tested
ISL73051ASEH
LDR to 50krad(Si) RHA Tested
FN8964 Rev.3.00
May 16, 2019
Page 4 of 22
ISL75051ASEH, ISL73051ASEH
1. Overview
1.4
Pin Configuration
18 Ld CDFP
Top View
GND
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VADJ
BYP
1
18
17
16
15
14
13
12
11
10
PG
2
3
4
5
6
7
8
9
VIN
VIN
VIN
VIN
VIN
VIN
OCP
EN
GND
Note: The ESD triangular mark indicates Pin #1. It is a part of the device
marking and is placed on the lid in the quadrant where Pin #1 is located.
1.5
Pin Descriptions
Pin Number
Pin Name
GND
VOUT
VADJ
BYP
Description
1
GND pin.
2, 3, 4, 5, 6, 7
Output voltage pins.
8
The VADJ pin allows V
to be programmed with an external resistor divider.
OUT
To filter the internal reference, connect a 0.1µF capacitor from the BYP pin to GND.
independent chip enable. TTL and CMOS compatible.
9
10
EN
V
IN
11
12, 13, 14, 15, 16, 17
18
OCP
VIN
Allows the current limit to be programmed with an external resistor.
Input supply pins.
PG
V
in regulation signal. Logic low defines when V
is not in regulation. Must be
OUT
OUT
grounded if not used.
Top Lid
GND
-
The top lid is connected to the GND pin of the package.
The bottom E-pad is only available on the K18.E package and is not electrically connected.
Bottom Metal
FN8964 Rev.3.00
May 16, 2019
Page 5 of 22
ISL75051ASEH, ISL73051ASEH
2. Specifications
2. Specifications
2.1
Absolute Maximum Ratings
Parameter
Minimum
-0.3
Maximum
Unit
V
V
V
Relative to GND (Note 5)
6.7
6.7
IN
Relative to GND (Note 5)
-0.3
V
OUT
PG, EN, OCP/ADJ Relative to GND (Note 5)
-0.3
6.7
V
V
V
Relative to GND (Notes 5, 6)
-0.3
6.2
V
IN
Relative to GND (Notes 5, 6)
-0.3
6.2
V
OUT
PG, EN, OCP/ADJ Relative to GND (Notes 5, 6)
Junction Temperature (T ) (Note 5)
-0.3
6.2
V
+175
°C
Unit
kV
V
J
ESD Rating
Value
2.5
Human Body Model (Tested per MIL-PRF-883 3015.7)
Machine Model (Tested per JESD22-A115C)
Charged Device Model (Tested per JS-002-2014)
Notes:
250
1
kV
5. Extended operation at these conditions can compromise reliability. Exceeding these limits results in damage. Recommended
operating conditions define limits where specifications are established.
2
6. Tested in a heavy ion environment at LET = 86.3MeV•cm /mg at +125°C (T ).
C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can
adversely impact product reliability and result in failures not covered by warranty.
2.2
Thermal Information
Thermal Resistance (Typical)
(°C/W)
28
(°C/W)
4
JA
JC
18 Ld CDFP Package (Notes 7, 8)
18 Ld CDFP Package with Bottom Metal and Solder Mount (Notes 7, 8)
Notes:
24
3.3
7. is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach”
JA
features. See TB379.
8. For , the “case temp” location is the center of the package underside.
JC
Parameter
Storage Temperature Range
Minimum
Maximum
Unit
-65
+150
°C
2.3
Recommended Operating Conditions
Parameter (Note 9)
Ambient Temperature Range (T )
Minimum
Maximum
+125
+150
6.0
Unit
°C
°C
V
-55
A
Junction Temperature (T )
J
V
V
Relative to GND
2.2
0.8
0
IN
Range
5
V
OUT
PG, EN, OCP/ADJ Relative to GND
+6.0
V
Note:
9. Refer to “Thermal Guidelines” on page 16.
FN8964 Rev.3.00
May 16, 2019
Page 6 of 22
ISL75051ASEH, ISL73051ASEH
2. Specifications
2.4
Radiation Information
Parameter
Minimum
Maximum
Unit
Maximum Total Dose
Dose Rate = 50-300rad(Si)/s (ISL75051ASEH only)
Dose Rate = 0.01rad(Si)/s
100
50
krad(Si)
krad(Si)
SEE Performance
2
SET (V
<±5% During Events) (Note 10)
86.3
86.3
MeV•cm /mg
OUT
2
SEL/SEB (No Latch-Up/Burnout)
MeV•cm /mg
Note:
10. Refer to this device’s Radiation report for more details.
2.5
Electrical Specifications
Unless otherwise noted, all parameters are established over the following specified conditions: V = V
IN
+ 0.4V, V
= 1.8V,
OUT
OUT
= 220µF, 25mΩ, and 0.1µF X7R, T = +25°C, I = 0A. Applications must follow thermal guidelines of the package to
C
= C
IN
determine worst-case junction temperature (see Note 14). Boldface limits apply across the operating temperature range, -55°C to
+125°C. Pulse load techniques are used by ATE to ensure T = T defines established limits.
OUT
J
L
J
A
Min
Max
Parameter
Symbol
Test Conditions
(Note 11)
Typ
(Note 11)
Unit
DC Characteristics
DC Output Voltage Accuracy
V
V
resistor adjust to 0.52V, 1.5V, and 1.8V
OUT
-1.5
-1.5
0.2
0.2
1.5
1.5
%
%
OUT
2.2V < V < 3.6V; 0A < I
< 3.0A
IN LOAD
V
V
resistor adjust to 5.0V
+ 0.4V < V < 6.0V; 0A < I
IN
OUT
OUT
<3.0A
LOAD
VADJ Pin Voltage
BYP Pin
V
2.2V < V < 6.0V; I
IN
= 0A
= 0A
514.8
520.0
520
525.2
mV
mV
mV
ADJ
LOAD
LOAD
V
2.2V < V < 6.0V; I
IN
BYP
DC Input Line Regulation
2.2V < V < 3.6V, V
IN
(Note 12)
= 1.5V, +25°C and -55°C
1.13
3.50
8.00
OUT
2.2V < V < 3.6V, V
IN
(Note 12)
= 1.5V, +125°C
1.13
1.62
1.62
mV
mV
mV
OUT
OUT
2.2V < V < 3.6V, V
IN
(Note 12)
= 1.8V, +25°C and -55°C
= 1.8V, +125°C
3.50
2.2V < V < 3.6V, V
IN
10.50
OUT
(Note 12)
V
+ 0.4V < V < 6.0V, V
= 5.0V (Note 12)
12.50
-0.8
20.00
-0.1
mV
mV
OUT
OUT
IN
OUT
< 3.0A,
+ 0.4V (Note 12)
OUT
DC Output Load Regulation
V
V
= 1.5V; 0A < I
LOAD
= V
-4.00
-4.80
IN
V
V
= 1.8V; 0A < I
= V
< 3.0A,
-1.20
-6.00
-0.05
-0.05
mV
mV
OUT
LOAD
+ 0.4V (Note 12)
OUT
IN
V
V
= 5.0V; 0A < I
< 3.0A,
-15.00
OUT
LOAD
+ 0.4V (Note 12)
= V
IN
OUT
VADJ Input Current
Ground Pin Current
V
= 0.5V
1
µA
mA
mA
mA
mA
µA
ADJ
I
V
= 1.5V; I
= 5.0V; I
= 1.5V; I
= 5.0V; I
= 0A, V = 2.2V
IN
11
16
11
16
10
13
19
14
20
30
Q
OUT
OUT
OUT
OUT
LOAD
LOAD
LOAD
LOAD
V
V
V
= 0A, V = 6.0V
IN
= 3.0A, V = 2.2V
IN
= 3.0A, V = 6.0V
IN
Ground Pin Current in
Shutdown
I
ENABLE Pin = 0V, V = 6.0V
IN
SHDN
FN8964 Rev.3.00
May 16, 2019
Page 7 of 22
ISL75051ASEH, ISL73051ASEH
2. Specifications
Unless otherwise noted, all parameters are established over the following specified conditions: V = V
IN
+ 0.4V, V
= 1.8V,
OUT
OUT
= 220µF, 25mΩ, and 0.1µF X7R, T = +25°C, I = 0A. Applications must follow thermal guidelines of the package to
C
= C
IN
determine worst-case junction temperature (see Note 14). Boldface limits apply across the operating temperature range, -55°C to
+125°C. Pulse load techniques are used by ATE to ensure T = T defines established limits. (Continued)
OUT
J
L
J
A
Min
Max
Parameter
Dropout Voltage
Symbol
Test Conditions
(Note 11)
Typ
65
(Note 11)
Unit
mV
mV
mV
A
V
I
I
I
= 1.0A, V
= 2.0A, V
= 3.0A, V
= 2.5V (Note 13)
= 2.5V (Note 13)
= 2.5V (Note 13)
100
200
300
DO
LOAD
LOAD
LOAD
OUT
OUT
OUT
140
225
1.1
1.2
5.7
6.2
175
Output Short-Circuit Current
Output Short-Circuit Current
I
V
V
V
V
V
= 0V, V = 2.2V, R
IN
= 5.11k
= 5.11k
= 511Ω
= 511Ω
SCL
OUT
OUT
OUT
OUT
OUT
SET
SET
SET
SET
= 0V, V = 6.0V, R
IN
A
I
= 0V, V = 2.2V, R
IN
A
SCH
= 0V, V = 6.0V, R
IN
A
Thermal Shutdown
Temperature
TSD
+ 0.4V < V < 6.0V
IN
°C
Thermal Shutdown Hysteresis
(Rising Threshold)
TSDn
V
+ 0.4V < V < 6.0V
IN
25
°C
OUT
AC Characteristics
Input Supply Ripple Rejection
PSRR
V
V
= 300mV, f = 1kHz, I
LOAD
= 3A; V = 2.5V,
IN
42
66
30
dB
dB
P-P
= 1.8V
OUT
V
V
= 300mV, f = 100kHz, I = 3A;
LOAD
P-P
IN
= 2.5V, V
= 1.8V
OUT
Phase Margin
PM
GM
V
= 1.8V, C = 220µF Tantalum
70
16
dB
dB
OUT
OUT
L
Gain Margin
V
= 1.8V, C = 220µF Tantalum
L
Output Noise Voltage
I
= 10mA, BW = 300Hz < f < 300kHz,
100
µV
RMS
LOAD
BYPASS to GND capacitor = 0.2µF
Device Start-Up Characteristics: Enable Pin
Rising Threshold
2.2V < V < 6.0V
IN
0.6
0.9
1.2
0.90
1
V
V
Falling Threshold
2.2V < V < 6.0V
IN
0.47
0.70
Enable Pin Leakage Current
Enable Pin Propagation Delay
Hysteresis
V
V
= 6.0V, EN = 6.0V
= 2.2V, EN rise to I
µA
µs
mV
IN
IN
rise
225
90
300
200
450
318
OUT
Must be independent of V ; 2.2V < V < 6.0V
IN IN
Device Start-Up Characteristics: PG Pin
PG Rising Threshold
PG Falling Threshold
PG Hysteresis
2.2V < V < 6.0V
IN
85
82
90
88
97
93
%
%
2.2V < V < 6.0V
IN
2.2V < V < 6.0V
IN
2.5
3.2
35
5.0
%V
OUT
PG Low Voltage
I
I
= 1mA
100
400
1.00
mV
mV
µA
SINK
SINK
= 6mA
185
0.01
PG Leakage Current
Notes:
V
= 6.0V, PG = 6.0V
IN
11. Parameters with MIN and/or MAX limits are 100% tested at -55°C, +25°C, and +125°C, unless otherwise specified. Temperature
limits established by characterization and are not production tested.
12. Line and Load Regulation done under pulsed condition for T <10ms.
13. Dropout is defined as the difference between the supply V and V
IN
when the supply produces a 2% drop in V
from its
OUT
OUT,
nominal value. Data measured within a 3ms period.
14. See“Applications Information” on page 12 and TB379.
FN8964 Rev.3.00
May 16, 2019
Page 8 of 22
ISL75051ASEH, ISL73051ASEH
3. Typical Operating Performance
3. Typical Operating Performance
1.528
0.522
0.521
0.520
0.519
0.518
0.517
0.516
0.515
+25°C, V
OUT
+25°C, V
ADJ
1.526
1.524
1.522
1.520
1.518
1.516
1.514
1.512
1.510
-58°C, V
OUT
-58°C, V
ADJ
+128°C, V
OUT
+128°C, V
ADJ
V
V
= 2.5V
V
V
= 2.5V
= 1.5V
IN
OUT
IN
OUT
0.5
= 1.5V
0.0
0.5
1.0
1.5
I
2.0
(A)
2.5
3.0
3.5
0.0
1.0
1.5
I
2.0
(A)
2.5
3.0
3.5
3.5
3.5
OUT
OUT
Figure 6. Load Regulation, V
ADJ
vs I
OUT
Figure 5. Load Regulation, V
vs I
OUT
OUT
0.5215
2.525
0.5210
0.5205
0.5200
0.5195
0.5190
0.5185
0.5180
0.5175
0.5170
0.5165
0.5160
+25°C, V
ADJ
2.520
2.515
2.510
2.505
2.500
2.495
2.490
2.485
-58°C, V
OUT
-58°C, V
ADJ
+25°C, V
OUT
+128°C, V
+128°C, V
ADJ
OUT
V
V
= 3.3V
V
V
= 3.3V
= 2.5V
IN
OUT
0.5
IN
OUT
= 2.5V
0.0
0.5
1.0
1.5
2.0
(A)
2.5
3.0
0.0
1.0
1.5
2.0
(A)
2.5
3.0
3.5
I
I
OUT
OUT
Figure 7. Load Regulation, V
vs I
Figure 8. Load Regulation, V vs I
ADJ OUT
OUT
OUT
0.5215
4.090
+25°C, V
-58°C, V
ADJ
0.5210
0.5205
0.5200
0.5195
0.5190
0.5185
0.5180
0.5175
0.5170
0.5165
0.5160
4.085
4.080
4.075
4.070
4.065
4.060
+128°C, V
OUT
ADJ
+25°C, V
+128°C, V
ADJ
OUT
-58°C, V
1.5
OUT
2.0
V
V
= 5V
= 4V
V
V
= 5V
IN
OUT
0.5
IN
OUT
= 4V
0.0
1.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
(A)
2.5
3.0
3.5
I
(A)
I
OUT
OUT
Figure 9. Load Regulation, V
vs I
Figure 10. Load Regulation, V vs I
ADJ OUT
OUT
OUT
FN8964 Rev.3.00
May 16, 2019
Page 9 of 22
ISL75051ASEH, ISL73051ASEH
3. Typical Operating Performance
0.525
0.523
8
7
6
5
4
3
2
1
0
R
R
= 0.511k
OCP
R
+25°C, V
ADJ
= 0.681k
= 0.75k
OCP
0.521
0.519
R
OCP
R
= 1.00k
= 2.00k
OCP
R
= 1.47k
OCP
OCP
-58°C, V
ADJ
+128°C, V
ADJ
0.517
R
= 3.83
R
= 5.11k
OCP
R
= 2.61k
OCP
OCP
0.515
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
(V)
V
(V)
V
IN
IN
Figure 11. V vs V
IN
Over-Temperature
Figure 12. R
vs OCP at +25°C, V
= 1.5V
ADJ
OCP OUT
8
7
6
5
4
3
2
1
0
8
R
= 0.511k
OCP
R
= 0.511k
OCP
7
6
5
4
3
2
1
0
R
= 0.681k
OCP
OCP
R
= 0.681k
= 0.75k
= 1.47k
OCP
R
R
R
R
= 1.00k
OCP
R
= 1.00k
= 2.00k
R
= 0.75k
= 1.47k
OCP
OCP
OCP
= 2.00k
OCP
R
OCP
R
OCP
R
= 5.11k
R
= 3.83
R
= 3.83
R
= 2.61k
OCP
R
= 2.61k
R
= 5.11k
OCP
OCP
OCP
OCP
OCP
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
V
(V)
V
IN
(V)
IN
Figure 13. R
vs OCP at +128°C, V
= 1.5V
Figure 14. R
vs OCP at -58°C, V
= 1.5V
OCP
OUT
OCP
OUT
100mV/Div
100mV/Div
1A/Div
1A/Div
500µs/Div
500µs/Div
Figure 15. Transient Load Response, V = 3.3V,
IN
Figure 16. Transient Load Response, V = 3.3V,
IN
V
= 2.5V, C
= 47µF, 35mΩ
V
= 2.5V, C = 220µF, 25mΩ
OUT
OUT
OUT
OUT
FN8964 Rev.3.00
May 16, 2019
Page 10 of 22
ISL75051ASEH, ISL73051ASEH
3. Typical Operating Performance
1V/Div
500mV/Div
2V/Div
500mV/Div
1V/Div
2V/Div
1V/Div
1V/Div
2ms/Div
5ms/Div
Figure 17. Power-On and Power-Off, EN = 0 to 1, +25°C,
Figure 18. Power-On and Power-Off, EN = 0 to 1, +25°C,
V
= 3.3V, V
= 0.8V, I
= 0.5A, PGOOD Turn-On
V
= 2.2V, V = 0.8V, I
= 0.5A, PGOOD Turn-On
IN
OUT
OUT
IN
OUT OUT
2V/Div
500mV/Div
2V/Div
500mV/Div
1V/Div
2V/Div
1V/Div
2V/Div
2ms/Div
2ms/Div
Figure 19. Power-On and Power-Off, EN = 1 to 0, +25°C,
Figure 20. Power-On and Power-Off, EN = 1 to 0, +25°C,
V
= 6V, V
= 0.8V, I
= 0.5A, PGOOD Turn-Off
V
= 2.2V, V = 0.8V, I
= 0.5A, PGOOD Turn-Off
IN
OUT
OUT
IN
OUT OUT
80
70
60
50
40
30
100
64.96dB
PSRR dB at -58°C
10
1
PSRR dB at +25°C
PSRR dB at +128°C
27.61dB
V
V
= 4V
IN
= 3V
OUT
I
= 3A
OUT
Temperature = +25oC
V
I
C
= 2.5V, V
= 1.8V,
IN
OUT
= 3A, Signal = 300mV
0.1
0.01
20
10
0
OUT
P-P
= 220µF TANT,
IN
e = 365.90nV/√Hz at 1kHz
n
C
= 220µF TANT, C
= 0.2µF
OUT
BYP
10
100
1k
10k
100k
0.01
1
100
10k
Frequency (Hz)
Frequency (Hz)
Figure 21. Noise (µV/√Hz)
Figure 22. PSRR
FN8964 Rev.3.00
May 16, 2019
Page 11 of 22
ISL75051ASEH, ISL73051ASEH
4. Applications Information
4. Applications Information
4.1
Input Voltage Requirements
These radiation hardened LDOs work from a V in the range of 2.2V to 6.0V. The input supply can have a
IN
tolerance of as much as ±10% for conditions noted in the “Electrical Specifications” on page 7. The minimum input
voltage is 2.2V. However, due to the nature of an LDO, V must be some margin higher than the output voltage,
IN
and dropout at the maximum rated current of the application, if active filtering (PSRR) is expected from V to
IN
V
. The dropout specification of this family of LDOs has been generously specified to allow applications to
OUT
design for efficient operation.
4.2
Adjustable Output Voltage
The output voltage of the radiation hardened LDOs can be set to any user-programmable level between 0.8V and
5.0V. This is achieved with a resistor divider connected between the OUT, ADJ, and GND pins. With the internal
reference at 0.52V, the divider ratio should be fixed so that when the desired V
level is reached, the voltage
OUT
presented to the ADJ pin is 0.52V. Resistor values for typical voltages are shown in Table 2.
Table 2. Resistor Values for Typical Voltages
V
(V)
R
(Ω)
R
(kΩ)
OUT
BOTTOM
TOP
0.8
7.87k
4.32
1.5
1.8
2.5
4.0
5.0
2.26k
1.74k
1.13k
634
4.32
4.32
4.32
4.32
4.32
499
R
TOP
R
= ------------------------------
BOTTOM
(EQ. 1)
V
OUT
---------------
– 1
V
ADJ
4.3
Input and Output Capacitor Selection
The radiation hardened operation requires the use of a combination of tantalum and ceramic capacitors to achieve a
good volume-to-capacitance ratio. The recommended combination is a 220µF, 10V, 25mΩ rated DSSC 04051-032
series tantalum capacitor in parallel with a 0.1µF MIL-PRF-49470 CDR04 ceramic capacitor that is connected
between the VIN to GND pins and the VOUT to GND pins of the LDO, with PCB traces no longer than 0.5cm.
While using the same capacitor for both VIN and VOUT simplifies the design and reduces the BOM count, it is not
required to do so. The VIN capacitance provides transient current during start-up and load steps while ensuring that
VIN does not drop below the UVLO threshold. The VIN capacitance can be sized appropriately for a given
application as long as those two criteria are met.
The stability of the device depends on the capacitance and ESR of the output capacitor. The usable ESR range for
the device is 6mΩ to 100mΩ. At the lower limit of ESR = 6mΩ, the phase margin is about 51°. On the high side, an
ESR of 100mΩ is found to limit the gain margin at around 10dB. The typical GM/PM seen with capacitors is
shown in Table 3.
Table 3. Typical GM/PM with Various Capacitors
Capacitance (µF)
ESR (mΩ)
Gain Margin (dB)
Phase Margin (°)
47
35
25
14
16
55
57
100
FN8964 Rev.3.00
May 16, 2019
Page 12 of 22
ISL75051ASEH, ISL73051ASEH
4. Applications Information
Table 3. Typical GM/PM with Various Capacitors (Continued)
Capacitance (µF)
ESR (mΩ)
Gain Margin (dB)
Phase Margin (°)
220
220
100
6
19
16
10
51
69
62
25
100
The type numbers of the KEMET capacitors used in the device are shown in Table 4.
Table 4. KEMET Capacitors Used in Device
KEMET Type Number
T525D476M016ATE035
T525D107M010ATE025
T530D227M010ATE006
T525D227M010ATE025
T495X107K016ATE100
Capacitor Details
47µF, 10V, 35mΩ
100µF, 10V, 25mΩ
220µF, 10V, 6mΩ
220µF, 10V, 25mΩ
100µF, 16V, 100mΩ
A typical gain phase plot measured on the ISL75051ASEHEV1Z evaluation board for V = 3.3V, V
IN
= 1.8V,
OUT
= 3A with a 220µF, 10V, 25mΩ capacitor is shown in Figure 23 and is measured at GM = 16.3dB and
and I
OUT
PM = 69.16°.
60
50
40
180
150
120
90
30
PHASE
20
60
10
0
30
0
GAIN
-10
-20
-30
-40
-50
-60
3.3V
-30
-60
-90
-120
-150
-180
1.8V
3.0A
1x220µF
T525D
500
5k
50k
Frequency (Hz)
500k
5M
Figure 23. Typical Gain Phase Plot
4.4
Enable
These devices can be enabled by applying a logic high on the EN pin. The enable threshold is typically 0.9V. A
soft-start cycle is initiated when the devices are enabled using this pin. Taking this pin to logic low disables the
devices.
The EN can be driven from either an open drain or a totem pole logic drive between the EN pin and GND.
Assuming an open-drain configuration, M1 actively pulls down the EN line, as shown in Figure 24 on page 14, and
thereby discharges the input capacitance, shutting off the devices immediately.
FN8964 Rev.3.00
May 16, 2019
Page 13 of 22
ISL75051ASEH, ISL73051ASEH
4. Applications Information
V
IN
R
1
10k
INT EN Gate
EN PIN
INT EN Bus
M
1
EN
0
Figure 24. Enable
4.5
Power-Good
The power-good pin is asserted high when the voltage on the ADJ pin crosses the rising threshold of 0.9 x V
ADJ
(typical). On the falling threshold, power-good is asserted low when the voltage on the ADJ pin crosses the falling
threshold of 0.88 x V . The power-good output is an open-drain output rated for a continuous sink current of
ADJ
1mA.
4.6
Soft-Start
Soft-start is achieved by the BYP pin charging time constant. The capacitor value on the pin determines the time
constant and can be calculated using Equations 2 through 4 based on the V range:
IN
If the V range is 2.2V ≤ V < 2.7V:
IN
IN
(EQ. 2)
t
= –4.8376 V + 0.0254 T + 0.0522 C
+ 11.8526
SS
IN
A
BYP
If the V range is 2.7V ≤ V < 4.0V:
IN IN
(EQ. 3)
t
= –1.4711 V + 0.0179 T + 0.0377 C
+ 4.7430
+ 1.8527
SS
IN
A
BYP
If the V range is 4.0V ≤ V < 6.0V:
IN IN
(EQ. 4)
t
= –0.4458 V + 0.0130 T + 0.0295 C
IN A
SS
BYP
where t = soft-start time (ms), V = input supply (V), T = ambient temperature, and C
SS IN BYP
= BYPASS capacitor
A
(nF).
The BYPASS capacitor, C , charges with a current source and provides an EA reference, -IN, with an SS ramp.
1
V
follows this ramp in turn. The ramp rate can be calculated based on the C value. For conditions in which C
OUT
is opened, or for small values of C , the ramp is provided by C = 50pF, with a source of 0.5µA. Connecting
1
1
1
2
C min = 0.1µF to the BYPASS pin is recommended for normal operation.
1
FN8964 Rev.3.00
May 16, 2019
Page 14 of 22
ISL75051ASEH, ISL73051ASEH
4. Applications Information
ADJ Pin
V
V
IN
IN
I1
90µA DC
I2
U1
0.5µA DC
V
IN
+IN
-IN
-IN
BYPASS
EXT Pin
INT SS Node
75051_PMOS
M1
OUT
V
ISL75051ASEH EA
OUT
C
C
2
1
0.1µF
50pF
0
0
Figure 25. Soft-Start
4.7
Current Limit Protection
The radiation hardened LDOs incorporate protection against overcurrent due to any short or overload condition
applied to the output pin. The current limit circuit becomes a constant current source when the output current
exceeds the current limit threshold, which can be adjusted by means of a resistor connected between the OCP pin
and GND. If the short or overload condition is removed from V
regulation. The OCP can be calculated with Equation 5:
, the output returns to normal voltage mode
OUT
(EQ. 5)
2.2V V 3.0V:
IN
2.8691
-----------------
I
= V 1.2688 +
+ T –0.002 – 2.1851
OCP
IN
A
R
OCP
3.0V V 6.6V:
IN
3.3161
-----------------
I
= V 6.168E – 02 +
+ T 1.5312E – 04 – 0.3176
OCP
IN
A
R
OCP
where OCP = Overcurrent Threshold in amps and ROCP = OCP resistor in kΩ. Visit our website for an Excel tool
to help calculate the ROCP value needed for a given OCP level.
In the event of an overload condition based on the set OCP limit, the die temperature can exceed the internal
over-temperature limit, and the LDOs begin to cycle on and off due to the fault condition (Figure 26). However,
thermal cycling may never occur if the heatsink used for the package can keep the die temperature below the limits
specified for thermal shutdown.
8
7
6
5
4
3
2
1
0
OCP = +25°C
0
1
2
3
4
5
6
R
(kΩ)
OCP
Figure 26. OCP vs R
OCP
FN8964 Rev.3.00
May 16, 2019
Page 15 of 22
ISL75051ASEH, ISL73051ASEH
4. Applications Information
4.8
Thermal Guidelines
If the die temperature exceeds approximately +175°C, the LDO output shuts down to zero until the die temperature
cools to approximately +155°C. The level of power combined with the thermal impedance of the package ( of
JC
4°C/W for the 18 Ld CDFP package) determines whether the junction temperature exceeds the thermal shutdown
temperature specified in the Electrical Specifications table on page 8.
Mount these devices on a high-effective thermal conductivity PCB with thermal vias, per JESD51-7 and
JESD51-5. Place a silpad between the package base and the PCB copper plane. The V and V
ratios should
IN
OUT
be selected to ensure that dissipation for the selected V range keeps T within the recommended operating level
IN
J
of +150°C for normal operation.
FN8964 Rev.3.00
May 16, 2019
Page 16 of 22
ISL75051ASEH, ISL73051ASEH
5. Die and Layout Characteristics
5. Die and Layout Characteristics
Table 5. Die and Assembly Related Information
Die Information
Dimensions
4555µm x 4555µm (179.3 mils x 179.3 mils)
Thickness: 304.8µm ±25.4µm (12.0 mils ±1 mil)
Interface Materials
Glassivation
Type: Silicon Oxide and Silicon Nitride
Thickness: 0.3µm ±0.03µm to 1.2µm ±0.12µm
Top Metallization
Type: AlCu (99.5%/0.5%)
Thickness: 2.7µm ±0.4µm
Backside Metallization
Substrate
None
Type: Silicon
Backside Finish
Silicon
Process
0.6µM BiCMOS Junction Isolated
Assembly Information
Substrate Potential
Additional Information
Worst Case Current Density
Transistor Count
Unbiased
5
2
<2 x 10 A/cm
2932
Weight of Packaged Device
K18.D: 1.07g typical with leads clipped
K18.E: 1.07g typical with leads clipped
Layout Characteristics
Step and Repeat
4555µmx4555µm
FN8964 Rev.3.00
May 16, 2019
Page 17 of 22
ISL75051ASEH, ISL73051ASEH
6. Metallization Mask Layout
6. Metallization Mask Layout
Pad X Y Coordinates
X
Y
DX
DY
Pad Name (µm) (µm) (µm) (µm)
1
2
GND
0
0
0
254 254
254 254
GND -393
3
VOUT -711 -710 254 422
VOUT -711 -1858 254 422
VOUT -711 -2964 254 422
ADJ -1680 -3070 254 254
BYP -1621 -3879 254 254
4
5
6
7
8
EN
2164 -3879 254 254
9
OCP 2222 -3131 254 246
10
11
12
13
VIN
VIN
VIN
PG
1078 -2965 254 422
1078 -1853 254 422
1078 -711 254 422
420
-25
254 254
FN8964 Rev.3.00
May 16, 2019
Page 18 of 22
ISL75051ASEH, ISL73051ASEH
7. Revision History
7. Revision History
Rev.
Date
Description
3.00
May 16, 2019
Updated links throughout document.
Added second paragraph in “Input and Output Capacitor Selection” on page 12.
Updated disclaimer.
2.00
1.00
Mar 2, 2018
Updated Figure 3 on page 3.
Changed Maximum Total Dose Rate at 0.01rad(Si)/s from 100krad(Si) to 50krad(Si) on page 7.
Changed Maximum SEE Performance from 86MeV•cm /mg to 86.3MeV•cm /mg on page 7.
Updated Note 10 to link to the device’s test report for SET and SEL/SEB on page 7.
Removed Radiation Characteristics section (multiple pages).
Updated Renesas disclaimer.
2
2
Removed About Intersil section.
Nov 14, 2017
Added ISL75051ASEHF/PROTO and ISL73051ASEHF/PROTO to the Ordering Information table on
page 4.
Updated Pin descriptions adding bottom metal information.
Updated Absolute Maximum Ratings table and added Note 6.
Updated Radiation Information table and removed Note 10 on page 7.
Updated DC Output Regulation (V
= 1.8V) minimum spec from “”-4.0” to “-4.80”.
OUT
Updated PG Rising Threshold maximum spec from “96” to “97”.
Updated PG Hysteresis maximum spec from “4.0” to “5.0”.
Updated heading for the tables in sections 3.1, 3.2, and 3.3.
0.00
Sept 25, 2017
Initial release
FN8964 Rev.3.00
May 16, 2019
Page 19 of 22
ISL75051ASEH, ISL73051ASEH
8. Package Outline Drawings
For the most recent package outline drawing, see K18.D.
8. Package Outline Drawings
K18.D 18 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Rev 5, 3/13
PIN NO. 1
ID OPTIONAL
0.015(0.381)
1
2
0.005(0.127)
A
A
0.040(1.016 BSC)
0.476(12.09)
0.456(11.58)
PIN NO. 1
ID AREA
0.005(0.127)
MIN.
4
0.020(0.508)
0.013(0.330)
TOP VIEW
0.122(3.10)
0.100(2.54)
0.036(0.92)
0.026(0.66)
0.397(10.084)
0.377(9.576)
6
-D-
0.010(0.254)
0.004(0.102)
-H-
0.295(7.49)
-C-
0.250(6.35)
0.303(7.70)
0.283(7.19)
SEATING AND
BASE PLANE
0.03(0.76) MIN.
SIDE VIEW
BOTTOM VIEW
NOTES:
Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark. Alternately, a tab may be used to identify pin one.
1.
0.007(0.178)
0.004(0.102)
LEAD FINISH
2. If a pin one identification mark is used in addition to a tab, the limits
of the tab dimension do not apply.
~
0.010(0.254)
0.004(0.102)
BASE
METAL
3. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
0.017(0.432)
0.013(0.330)
4. Measure dimension at all four corners.
0.0015(0.04)
MAX
5. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
0.020(0.508)
0.013(0.330)
6. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
3
SECTION A-A
7. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
8. Dimensions = INCH (mm). Controlling dimension: INCH.
FN8964 Rev.3.00
May 16, 2019
Page 20 of 22
ISL75051ASEH, ISL73051ASEH
8. Package Outline Drawings
For the most recent package outline drawing, see K18.E.
K18.E
18 Lead Ceramic Metal Seal Flatpack Package with Bottom Metal
Rev 1, 3/13
PIN NO. 1
ID OPTIONAL
0.015(0.381)
1
2
0.005(0.127)
A
A
0.040(1.016 BSC)
0.476(12.09)
0.456(11.58)
PIN NO. 1
ID AREA
0.005(0.127)
MIN.
4
0.020(0.508)
0.013(0.330)
TOP VIEW
0.122(3.10)
0.100(2.54)
0.036(0.92)
0.026(0.66)
0.397(10.084)
6
-D-
0.377(9.576)
0.010(0.254)
0.004(0.102)
-H-
0.295(7.49)
-C-
0.250(6.35)
BOTTOM METAL
7
0.303(7.70)
0.283(7.19)
SEATING AND
BASE PLANE
0.03(0.76) MIN.
SIDE VIEW
BOTTOM METAL
0.005(0.127) REF
OFFSET FROM
CERAMIC EDGE
BOTTOM VIEW
NOTES:
Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark. Alternately, a tab may be used to identify pin one.
1.
0.007(0.178)
0.004(0.102)
LEAD FINISH
2. If a pin one identification mark is used in addition to a tab, the limits
of the tab dimension do not apply.
~
3. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
0.010(0.254)
0.004(0.102)
BASE
METAL
4. Measure dimension at all four corners.
0.017(0.432)
0.013(0.330)
5. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
0.0015(0.04)
MAX
6. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
0.020(0.508)
0.013(0.330)
3
SECTION A-A
7.
The bottom of the package is a solderable metal surface.
8. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
9. Dimensions = INCH (mm). Controlling dimension: INCH.
FN8964 Rev.3.00
May 16, 2019
Page 21 of 22
1RWLFH
ꢃꢅ 'HVFULSWLRQVꢀRIꢀFLUFXLWVꢆꢀVRIWZDUHꢀDQGꢀRWKHUꢀUHODWHGꢀLQIRUPDWLRQꢀLQꢀWKLVꢀGRFXPHQWꢀDUHꢀSURYLGHGꢀRQO\ꢀWRꢀLOOXVWUDWHꢀWKHꢀRSHUDWLRQꢀRIꢀVHPLFRQGXFWRUꢀSURGXFWVꢀ
DQGꢀDSSOLFDWLRQꢀH[DPSOHVꢅꢀ<RXꢀDUHꢀIXOO\ꢀUHVSRQVLEOHꢀIRUꢀWKHꢀLQFRUSRUDWLRQꢀRUꢀDQ\ꢀRWKHUꢀXVHꢀRIꢀWKHꢀFLUFXLWVꢆꢀVRIWZDUHꢆꢀDQGꢀLQIRUPDWLRQꢀLQꢀWKHꢀGHVLJQꢀRIꢀ\RXUꢀ
SURGXFWꢀRUꢀV\VWHPꢅꢀ5HQHVDVꢀ(OHFWURQLFVꢀGLVFODLPVꢀDQ\ꢀDQGꢀDOOꢀOLDELOLW\ꢀIRUꢀDQ\ꢀORVVHVꢀDQGꢀGDPDJHVꢀLQFXUUHGꢀE\ꢀ\RXꢀRUꢀWKLUGꢀSDUWLHVꢀDULVLQJꢀIURPꢀWKHꢀXVHꢀRIꢀ
WKHVHꢀFLUFXLWVꢆꢀVRIWZDUHꢆꢀRUꢀLQIRUPDWLRQꢅ
ꢁꢅ 5HQHVDVꢀ(OHFWURQLFVꢀKHUHE\ꢀH[SUHVVO\ꢀGLVFODLPVꢀDQ\ꢀZDUUDQWLHVꢀDJDLQVWꢀDQGꢀOLDELOLW\ꢀIRUꢀLQIULQJHPHQWꢀRUꢀDQ\ꢀRWKHUꢀFODLPVꢀLQYROYLQJꢀSDWHQWVꢆꢀFRS\ULJKWVꢆꢀRUꢀ
RWKHUꢀLQWHOOHFWXDOꢀSURSHUW\ꢀULJKWVꢀRIꢀWKLUGꢀSDUWLHVꢆꢀE\ꢀRUꢀDULVLQJꢀIURPꢀWKHꢀXVHꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀRUꢀWHFKQLFDOꢀLQIRUPDWLRQꢀGHVFULEHGꢀLQꢀWKLVꢀ
GRFXPHQWꢆꢀLQFOXGLQJꢀEXWꢀQRWꢀOLPLWHGꢀWRꢆꢀWKHꢀSURGXFWꢀGDWDꢆꢀGUDZLQJVꢆꢀFKDUWVꢆꢀSURJUDPVꢆꢀDOJRULWKPVꢆꢀDQGꢀDSSOLFDWLRQꢀH[DPSOHVꢅꢀ
ꢇꢅ 1RꢀOLFHQVHꢆꢀH[SUHVVꢆꢀLPSOLHGꢀRUꢀRWKHUZLVHꢆꢀLVꢀJUDQWHGꢀKHUHE\ꢀXQGHUꢀDQ\ꢀSDWHQWVꢆꢀFRS\ULJKWVꢀRUꢀRWKHUꢀLQWHOOHFWXDOꢀSURSHUW\ꢀULJKWVꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀRUꢀ
RWKHUVꢅ
ꢈꢅ <RXꢀVKDOOꢀQRWꢀDOWHUꢆꢀPRGLI\ꢆꢀFRS\ꢆꢀRUꢀUHYHUVHꢀHQJLQHHUꢀDQ\ꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWꢆꢀZKHWKHUꢀLQꢀZKROHꢀRUꢀLQꢀSDUWꢅꢀ5HQHVDVꢀ(OHFWURQLFVꢀGLVFODLPVꢀDQ\ꢀ
DQGꢀDOOꢀOLDELOLW\ꢀIRUꢀDQ\ꢀORVVHVꢀRUꢀGDPDJHVꢀLQFXUUHGꢀE\ꢀ\RXꢀRUꢀWKLUGꢀSDUWLHVꢀDULVLQJꢀIURPꢀVXFKꢀDOWHUDWLRQꢆꢀPRGLILFDWLRQꢆꢀFRS\LQJꢀRUꢀUHYHUVHꢀHQJLQHHULQJꢅ
ꢉꢅ 5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀDUHꢀFODVVLILHGꢀDFFRUGLQJꢀWRꢀWKHꢀIROORZLQJꢀWZRꢀTXDOLW\ꢀJUDGHVꢊꢀꢋ6WDQGDUGꢋꢀDQGꢀꢋ+LJKꢀ4XDOLW\ꢋꢅꢀ7KHꢀLQWHQGHGꢀDSSOLFDWLRQVꢀIRUꢀ
HDFKꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWꢀGHSHQGVꢀRQꢀWKHꢀSURGXFWꢌVꢀTXDOLW\ꢀJUDGHꢆꢀDVꢀLQGLFDWHGꢀEHORZꢅ
ꢋ6WDQGDUGꢋꢊ
&RPSXWHUVꢍꢀRIILFHꢀHTXLSPHQWꢍꢀFRPPXQLFDWLRQVꢀHTXLSPHQWꢍꢀWHVWꢀDQGꢀPHDVXUHPHQWꢀHTXLSPHQWꢍꢀDXGLRꢀDQGꢀYLVXDOꢀHTXLSPHQWꢍꢀKRPHꢀ
HOHFWURQLFꢀDSSOLDQFHVꢍꢀPDFKLQHꢀWRROVꢍꢀSHUVRQDOꢀHOHFWURQLFꢀHTXLSPHQWꢍꢀLQGXVWULDOꢀURERWVꢍꢀHWFꢅ
ꢋ+LJKꢀ4XDOLW\ꢋꢊ 7UDQVSRUWDWLRQꢀHTXLSPHQWꢀꢎDXWRPRELOHVꢆꢀWUDLQVꢆꢀVKLSVꢆꢀHWFꢅꢏꢍꢀWUDIILFꢀFRQWUROꢀꢎWUDIILFꢀOLJKWVꢏꢍꢀODUJHꢐVFDOHꢀFRPPXQLFDWLRQꢀHTXLSPHQWꢍꢀNH\ꢀ
ILQDQFLDOꢀWHUPLQDOꢀV\VWHPVꢍꢀVDIHW\ꢀFRQWUROꢀHTXLSPHQWꢍꢀHWFꢅ
8QOHVVꢀH[SUHVVO\ꢀGHVLJQDWHGꢀDVꢀDꢀKLJKꢀUHOLDELOLW\ꢀSURGXFWꢀRUꢀDꢀSURGXFWꢀIRUꢀKDUVKꢀHQYLURQPHQWVꢀLQꢀDꢀ5HQHVDVꢀ(OHFWURQLFVꢀGDWDꢀVKHHWꢀRUꢀRWKHUꢀ5HQHVDVꢀ
(OHFWURQLFVꢀGRFXPHQWꢆꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀDUHꢀQRWꢀLQWHQGHGꢀRUꢀDXWKRUL]HGꢀIRUꢀXVHꢀLQꢀSURGXFWVꢀRUꢀV\VWHPVꢀWKDWꢀPD\ꢀSRVHꢀDꢀGLUHFWꢀWKUHDWꢀWRꢀ
KXPDQꢀOLIHꢀRUꢀERGLO\ꢀLQMXU\ꢀꢎDUWLILFLDOꢀOLIHꢀVXSSRUWꢀGHYLFHVꢀRUꢀV\VWHPVꢍꢀVXUJLFDOꢀLPSODQWDWLRQVꢍꢀHWFꢅꢏꢆꢀRUꢀPD\ꢀFDXVHꢀVHULRXVꢀSURSHUW\ꢀGDPDJHꢀꢎVSDFHꢀV\VWHPꢍꢀ
XQGHUVHDꢀUHSHDWHUVꢍꢀQXFOHDUꢀSRZHUꢀFRQWUROꢀV\VWHPVꢍꢀDLUFUDIWꢀFRQWUROꢀV\VWHPVꢍꢀNH\ꢀSODQWꢀV\VWHPVꢍꢀPLOLWDU\ꢀHTXLSPHQWꢍꢀHWFꢅꢏꢅꢀ5HQHVDVꢀ(OHFWURQLFVꢀGLVFODLPVꢀ
DQ\ꢀDQGꢀDOOꢀOLDELOLW\ꢀIRUꢀDQ\ꢀGDPDJHVꢀRUꢀORVVHVꢀLQFXUUHGꢀE\ꢀ\RXꢀRUꢀDQ\ꢀWKLUGꢀSDUWLHVꢀDULVLQJꢀIURPꢀWKHꢀXVHꢀRIꢀDQ\ꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWꢀWKDWꢀLVꢀ
LQFRQVLVWHQWꢀZLWKꢀDQ\ꢀ5HQHVDVꢀ(OHFWURQLFVꢀGDWDꢀVKHHWꢆꢀXVHUꢌVꢀPDQXDOꢀRUꢀRWKHUꢀ5HQHVDVꢀ(OHFWURQLFVꢀGRFXPHQWꢅ
ꢑꢅ :KHQꢀXVLQJꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢆꢀUHIHUꢀWRꢀWKHꢀODWHVWꢀSURGXFWꢀLQIRUPDWLRQꢀꢎGDWDꢀVKHHWVꢆꢀXVHUꢌVꢀPDQXDOVꢆꢀDSSOLFDWLRQꢀQRWHVꢆꢀꢋ*HQHUDOꢀ1RWHVꢀIRUꢀ
+DQGOLQJꢀDQGꢀ8VLQJꢀ6HPLFRQGXFWRUꢀ'HYLFHVꢋꢀLQꢀWKHꢀUHOLDELOLW\ꢀKDQGERRNꢆꢀHWFꢅꢏꢆꢀDQGꢀHQVXUHꢀWKDWꢀXVDJHꢀFRQGLWLRQVꢀDUHꢀZLWKLQꢀWKHꢀUDQJHVꢀVSHFLILHGꢀE\ꢀ
5HQHVDVꢀ(OHFWURQLFVꢀZLWKꢀUHVSHFWꢀWRꢀPD[LPXPꢀUDWLQJVꢆꢀRSHUDWLQJꢀSRZHUꢀVXSSO\ꢀYROWDJHꢀUDQJHꢆꢀKHDWꢀGLVVLSDWLRQꢀFKDUDFWHULVWLFVꢆꢀLQVWDOODWLRQꢆꢀHWFꢅꢀ5HQHVDVꢀ
(OHFWURQLFVꢀGLVFODLPVꢀDQ\ꢀDQGꢀDOOꢀOLDELOLW\ꢀIRUꢀDQ\ꢀPDOIXQFWLRQVꢆꢀIDLOXUHꢀRUꢀDFFLGHQWꢀDULVLQJꢀRXWꢀRIꢀWKHꢀXVHꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀRXWVLGHꢀRIꢀVXFKꢀ
VSHFLILHGꢀUDQJHVꢅ
ꢒꢅ $OWKRXJKꢀ5HQHVDVꢀ(OHFWURQLFVꢀHQGHDYRUVꢀWRꢀLPSURYHꢀWKHꢀTXDOLW\ꢀDQGꢀUHOLDELOLW\ꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢆꢀVHPLFRQGXFWRUꢀSURGXFWVꢀKDYHꢀVSHFLILFꢀ
FKDUDFWHULVWLFVꢆꢀVXFKꢀDVꢀWKHꢀRFFXUUHQFHꢀRIꢀIDLOXUHꢀDWꢀDꢀFHUWDLQꢀUDWHꢀDQGꢀPDOIXQFWLRQVꢀXQGHUꢀFHUWDLQꢀXVHꢀFRQGLWLRQVꢅꢀ8QOHVVꢀGHVLJQDWHGꢀDVꢀDꢀKLJKꢀUHOLDELOLW\ꢀ
SURGXFWꢀRUꢀDꢀSURGXFWꢀIRUꢀKDUVKꢀHQYLURQPHQWVꢀLQꢀDꢀ5HQHVDVꢀ(OHFWURQLFVꢀGDWDꢀVKHHWꢀRUꢀRWKHUꢀ5HQHVDVꢀ(OHFWURQLFVꢀGRFXPHQWꢆꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀ
DUHꢀQRWꢀVXEMHFWꢀWRꢀUDGLDWLRQꢀUHVLVWDQFHꢀGHVLJQꢅꢀ<RXꢀDUHꢀUHVSRQVLEOHꢀIRUꢀLPSOHPHQWLQJꢀVDIHW\ꢀPHDVXUHVꢀWRꢀJXDUGꢀDJDLQVWꢀWKHꢀSRVVLELOLW\ꢀRIꢀERGLO\ꢀLQMXU\ꢆꢀ
LQMXU\ꢀRUꢀGDPDJHꢀFDXVHGꢀE\ꢀILUHꢆꢀDQGꢓRUꢀGDQJHUꢀWRꢀWKHꢀSXEOLFꢀLQꢀWKHꢀHYHQWꢀRIꢀDꢀIDLOXUHꢀRUꢀPDOIXQFWLRQꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢆꢀVXFKꢀDVꢀVDIHW\ꢀ
GHVLJQꢀIRUꢀKDUGZDUHꢀDQGꢀVRIWZDUHꢆꢀLQFOXGLQJꢀEXWꢀQRWꢀOLPLWHGꢀWRꢀUHGXQGDQF\ꢆꢀILUHꢀFRQWUROꢀDQGꢀPDOIXQFWLRQꢀSUHYHQWLRQꢆꢀDSSURSULDWHꢀWUHDWPHQWꢀIRUꢀDJLQJꢀ
GHJUDGDWLRQꢀRUꢀDQ\ꢀRWKHUꢀDSSURSULDWHꢀPHDVXUHVꢅꢀ%HFDXVHꢀWKHꢀHYDOXDWLRQꢀRIꢀPLFURFRPSXWHUꢀVRIWZDUHꢀDORQHꢀLVꢀYHU\ꢀGLIILFXOWꢀDQGꢀLPSUDFWLFDOꢆꢀ\RXꢀDUHꢀ
UHVSRQVLEOHꢀIRUꢀHYDOXDWLQJꢀWKHꢀVDIHW\ꢀRIꢀWKHꢀILQDOꢀSURGXFWVꢀRUꢀV\VWHPVꢀPDQXIDFWXUHGꢀE\ꢀ\RXꢅ
ꢔꢅ 3OHDVHꢀFRQWDFWꢀDꢀ5HQHVDVꢀ(OHFWURQLFVꢀVDOHVꢀRIILFHꢀIRUꢀGHWDLOVꢀDVꢀWRꢀHQYLURQPHQWDOꢀPDWWHUVꢀVXFKꢀDVꢀWKHꢀHQYLURQPHQWDOꢀFRPSDWLELOLW\ꢀRIꢀHDFKꢀ5HQHVDVꢀ
(OHFWURQLFVꢀSURGXFWꢅꢀ<RXꢀDUHꢀUHVSRQVLEOHꢀIRUꢀFDUHIXOO\ꢀDQGꢀVXIILFLHQWO\ꢀLQYHVWLJDWLQJꢀDSSOLFDEOHꢀODZVꢀDQGꢀUHJXODWLRQVꢀWKDWꢀUHJXODWHꢀWKHꢀLQFOXVLRQꢀRUꢀXVHꢀRIꢀ
FRQWUROOHGꢀVXEVWDQFHVꢆꢀLQFOXGLQJꢀZLWKRXWꢀOLPLWDWLRQꢆꢀWKHꢀ(8ꢀ5R+6ꢀ'LUHFWLYHꢆꢀDQGꢀXVLQJꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀLQꢀFRPSOLDQFHꢀZLWKꢀDOOꢀWKHVHꢀ
DSSOLFDEOHꢀODZVꢀDQGꢀUHJXODWLRQVꢅꢀ5HQHVDVꢀ(OHFWURQLFVꢀGLVFODLPVꢀDQ\ꢀDQGꢀDOOꢀOLDELOLW\ꢀIRUꢀGDPDJHVꢀRUꢀORVVHVꢀRFFXUULQJꢀDVꢀDꢀUHVXOWꢀRIꢀ\RXUꢀQRQFRPSOLDQFHꢀ
ZLWKꢀDSSOLFDEOHꢀODZVꢀDQGꢀUHJXODWLRQVꢅ
ꢄꢅ 5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀDQGꢀWHFKQRORJLHVꢀVKDOOꢀQRWꢀEHꢀXVHGꢀIRUꢀRUꢀLQFRUSRUDWHGꢀLQWRꢀDQ\ꢀSURGXFWVꢀRUꢀV\VWHPVꢀZKRVHꢀPDQXIDFWXUHꢆꢀXVHꢆꢀRUꢀVDOHꢀLVꢀ
SURKLELWHGꢀXQGHUꢀDQ\ꢀDSSOLFDEOHꢀGRPHVWLFꢀRUꢀIRUHLJQꢀODZVꢀRUꢀUHJXODWLRQVꢅꢀ<RXꢀVKDOOꢀFRPSO\ꢀZLWKꢀDQ\ꢀDSSOLFDEOHꢀH[SRUWꢀFRQWUROꢀODZVꢀDQGꢀUHJXODWLRQVꢀ
SURPXOJDWHGꢀDQGꢀDGPLQLVWHUHGꢀE\ꢀWKHꢀJRYHUQPHQWVꢀRIꢀDQ\ꢀFRXQWULHVꢀDVVHUWLQJꢀMXULVGLFWLRQꢀRYHUꢀWKHꢀSDUWLHVꢀRUꢀWUDQVDFWLRQVꢅ
ꢃꢂꢅ ,WꢀLVꢀWKHꢀUHVSRQVLELOLW\ꢀRIꢀWKHꢀEX\HUꢀRUꢀGLVWULEXWRUꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢆꢀRUꢀDQ\ꢀRWKHUꢀSDUW\ꢀZKRꢀGLVWULEXWHVꢆꢀGLVSRVHVꢀRIꢆꢀRUꢀRWKHUZLVHꢀVHOOVꢀRUꢀ
WUDQVIHUVꢀWKHꢀSURGXFWꢀWRꢀDꢀWKLUGꢀSDUW\ꢆꢀWRꢀQRWLI\ꢀVXFKꢀWKLUGꢀSDUW\ꢀLQꢀDGYDQFHꢀRIꢀWKHꢀFRQWHQWVꢀDQGꢀFRQGLWLRQVꢀVHWꢀIRUWKꢀLQꢀWKLVꢀGRFXPHQWꢅ
ꢃꢃꢅ 7KLVꢀGRFXPHQWꢀVKDOOꢀQRWꢀEHꢀUHSULQWHGꢆꢀUHSURGXFHGꢀRUꢀGXSOLFDWHGꢀLQꢀDQ\ꢀIRUPꢆꢀLQꢀZKROHꢀRUꢀLQꢀSDUWꢆꢀZLWKRXWꢀSULRUꢀZULWWHQꢀFRQVHQWꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢅ
ꢃꢁꢅ 3OHDVHꢀFRQWDFWꢀDꢀ5HQHVDVꢀ(OHFWURQLFVꢀVDOHVꢀRIILFHꢀLIꢀ\RXꢀKDYHꢀDQ\ꢀTXHVWLRQVꢀUHJDUGLQJꢀWKHꢀLQIRUPDWLRQꢀFRQWDLQHGꢀLQꢀWKLVꢀGRFXPHQWꢀRUꢀ5HQHVDVꢀ
(OHFWURQLFVꢀSURGXFWVꢅ
ꢎ1RWHꢃꢏ ꢋ5HQHVDVꢀ(OHFWURQLFVꢋꢀDVꢀXVHGꢀLQꢀWKLVꢀGRFXPHQWꢀPHDQVꢀ5HQHVDVꢀ(OHFWURQLFVꢀ&RUSRUDWLRQꢀDQGꢀDOVRꢀLQFOXGHVꢀLWVꢀGLUHFWO\ꢀRUꢀLQGLUHFWO\ꢀFRQWUROOHGꢀ
VXEVLGLDULHVꢅ
ꢎ1RWHꢁꢏ ꢋ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWꢎVꢏꢋꢀPHDQVꢀDQ\ꢀSURGXFWꢀGHYHORSHGꢀRUꢀPDQXIDFWXUHGꢀE\ꢀRUꢀIRUꢀ5HQHVDVꢀ(OHFWURQLFVꢅ
ꢎ5HYꢅꢈꢅꢂꢐꢃꢀꢀ1RYHPEHUꢀꢁꢂꢃꢒꢏ
Corporate Headquarters
ContactInformation
TOYOSU FORESIA, 3-2-24 Toyosu,
For further information on a product, technology, the most up-to-date
Koto-ku, Tokyo 135-0061, Japan
www.renesas.com
version of a document, or your nearest sales office, please visit:
www.renesas.com/contact/
Trademarks
Renesas and the Renesas logo are trademarks of Renesas Electronics
Corporation. All trademarks and registered trademarks are the property
of their respective owners.
ꢀꢁꢂꢃꢄꢀ5HQHVDVꢀ(OHFWURQLFVꢀ&RUSRUDWLRQꢅꢀ$OOꢀULJKWVꢀUHVHUYHGꢅ
相关型号：
5962L1522802V9A
3.3V Radiation Tolerant CAN Transceiver, 1Mbps, Listen Mode, Split Termination Output
INTERSIL
©2020 ICPDF网 联系我们和版权申明