HI-5700_技术文档

®

HI-5700

8-Bit, 20 MSPS Flash A/D Converter

May 1997

Features

Description

• 20 MSPS with No Missing Codes

• 18MHz Full Power Input Bandwidth

• No Missing Codes Over Temperature

• Sample and Hold Not Required

• Single +5V Supply Voltage

• CMOS/TTL

The HI-5700 is a monolithic, 8-bit, CMOS Flash Analog-to-

Digital Converter. It is designed for high speed applications

where wide bandwidth and low power consumption are

essential. Its 20 MSPS speed is made possible by a parallel

architecture which also eliminates the need for an external

sample and hold circuit. The HI-5700 delivers ±0.5 LSB

differential nonlinearity while consuming only 725mW

(typical) at 20 MSPS. Microprocessor compatible data

output latches are provided which present valid data to the

output bus 1.5 clock cycles after the convert command is

received. An overflow bit is provided to allow the series

connection of two converters to achieve 9-bit resolution.

• Overflow Bit

• Improved Replacement for MP7684

• Evaluation Board Available

• /883 Version Available

Ordering Information

Applications

PART

TEMPERATURE

RANGE

NUMBER

PACKAGE

• Video Digitizing

HI3-5700J-5

HI9P5700J-5

HI3-5700A-9

HI9P5700A-9

0^oC to +70^oC

-40^oC to +85^oC

28 Lead Plastic DIP

28 Lead Plastic SOIC (W)

28 Lead Plastic DIP

28 Lead Plastic SOIC (W)

• Radar Systems

• Medical Imaging

• Communication Systems

• High Speed Data Acquisition Systems

Pinout

HI-5700

(PDIP, SOIC)

TOP VIEW

V_IN

CLK

1

2

28

27

26

25

24

23

22

V_REF

-

(MSB) D7

D6

AV_DD

AGND

AV_DD

¹/₂R

3

4

D5

5

D4

¹/₄R

V_DD

6

7

21 AV_DD

8

GND

³/₄R

AGND

9

20

19

18

17

16

15

D3

D2

10

11

12

13

14

AGND

AV_DD

V_REF

+

(LSB) D1

D0

CE1

CE2

OVF

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

File Number 3174.4

HI-5700

Functional Block Diagram

ýφ1 ýφ2

φý1

ýφ1

ýφ2

V_IN

28

D

R/2

OVERFLOW

(OVF)

Q

14

2

V_REF

+

17

CL

R

COMP

256

D

D7 (MSB)

D6

CL

R

³/₄R

9

D

3

CL

COMP

193

R

COMPARATOR

LATCHES

AND

ENCODER

LOGIC

D

4

D5

¹/₂R

CL

22

6

COMP

129

D

5

D4

D3

CL

¹/₄R

D

10

R

CL

COMP

65

D

D2

D1

Q

11

12

CL

COMP

2

D

R

CL

V_REF

-

27

D

13

D0 (LSB)

Q

R/2

CL

COMP

1

CE1

CE2

16

15

φý1

18

20

AV_DD

AGND

V_DD

GND

23

24

21 26

19

7

8

1

CLK

25

φý2

4-1492

Specifications HI-5700

Absolute Maximum Ratings

Thermal Information

Supply Voltage, V_DDto GND . . . . . . . . . (GND - 0.5) < V_DD< +7.0V

Analog and Reference Input Pins. . . .(V_SS- 0.5) < V_INA< (V_DD+0.5V)

Digital I/O Pins . . . . . . . . . . . . . . . (GND - 0.5) < V_I/O< (V_DD+0.5V)

Thermal Resistance

θ_JA

HI3-5700J-5, HI3-5700A-9 . . . . . . . . . . . . . . . . . . . . . 55^oC/W

HI9P5700J-5, HI9P5700A-9 . . . . . . . . . . . . . . . . . . . . 75^oC/W

Storage Temperature Range . . . . . . . . . . . . . . . -65^oC to +150^oC Maximum Power Dissipation +70^oC . . . . . . . . . . . . . . . . . . . . 1.05W

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . 300^oC

(SOIC - Lead Tips Only)

Operating Temperature Range

HI3-5700J-5, HI9P5700J-5 . . . . . . . . . . . . . . . . . . . 0^oC to +70^oC

HI3-5700A-9, HI9P5700A-9 . . . . . . . . . . . . . . . -40^oC to +85^oC

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150^oC

CAUTION: Stresses above those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and opera-

tion of the device at these or any other conditions above those indicated in the operation section of this specification is not implied.

Electrical Specifications AV_DD= V_DD= +5.0V; V_REF+= +4.0V; V_REF-= GND = AGND = 0V; F_S= Specified Clock Frequency at

50% Duty Cycle; C_L= 30pF; Unless Otherwise Specified

(NOTE 2)

0^oC TO +70^oC

+25^oC

TYP

-40^oC TO +85^oC

PARAMETER

TEST CONDITION

MIN

MAX

MIN

MAX

UNITS

SYSTEM PERFORMANCE

Resolution

8

-

8

-

Bits

Integral Linearity Error (INL)

(Best Fit Method)

F

_S= 15MHz, f_IN= DC

_S= 20MHz, f_IN= DC

-

±0.9

±1.0

±2.0

±2.25

-

±2.25

±3.25

LSB

Differential Linearity Error (DNL)

(Guaranteed No Missing Codes)

F

_S= 15MHz, f_IN= DC

-

±0.4

±0.5

±0.9

-

±1.0

LSB

F_S= 20MHz, f_IN= DC

Offset Error (VOS)

F

_S= 15MHz, f_IN= DC

_S= 20MHz, f_IN= DC

-

±5.0

±8.0

-

±9.5

LSB

Full Scale Error (FSE)

F_S= 15MHz, f_IN= DC

_S= 20MHz, f_IN= DC

-

±0.5

±0.6

±4.5

-

±8.0

LSB

F

DYNAMIC CHARACTERISTICS

Maximum Conversion Rate

Minimum Conversion Rate

Full Power Input Bandwidth

Signal to Noise Ratio (SNR)

No Missing Codes

20

-

25

-

0.125

-

20

-

0.125

-

MSPS

MHz

No Missing Codes (Note 2)

F_S= 20MHz

-

18

-

F_S= 15MHz, f_IN= 100kHz

F_S= 15MHz, f_IN= 3.58MHz

F_S= 15MHz, f_IN= 4.43MHz

F_S= 20MHz, f_IN= 100kHz

F_S= 20MHz, f_IN= 3.58MHz

F_S= 20MHz, f_IN= 4.43MHz

-

46.5

44.0

43.4

45.9

42.0

41.6

-

dB

RMS Signal

= --------------------------------

RMS Noise

Signal to Noise and Distortion Ratio

(SINAD)

F_S= 15MHz, f_IN= 100kHz

F_S= 15MHz, f_IN= 3.58MHz

F_S= 15MHz, f_IN= 4.43MHz

F_S= 20MHz, f_IN= 100kHz

F_S= 20MHz, f_IN= 3.58MHz

F_S= 20MHz, f_IN= 4.43MHz

-

43.4

34.3

32.3

42.3

35.2

32.8

-

dB

RMS Signal

= -------------------------------------------------------------

RMS Noise + Distortion

Total Harmonic Distortion (THD)

F_S= 15MHz, f_IN= 100kHz

F_S= 15MHz, f_IN= 3.58MHz

F_S= 15MHz, f_IN= 4.43MHz

F_S= 20MHz, f_IN= 100kHz

F_S= 20MHz, f_IN= 3.58MHz

F_S= 20MHz, f_IN= 4.43MHz

-

-46.9

-34.8

-32.8

-46.6

-36.6

-33.5

-

dBc

Differential Gain

F

_S= 14MHz, f_IN= 3.58MHz

-

3.5

0.9

-

%

Differential Phase Error

F

Degree

4-1493

Specifications HI-5700

Electrical Specifications AV_DD= V_DD= +5.0V; V_REF+= +4.0V; V_REF-= GND = AGND = 0V; F_S= Specified Clock Frequency at

50% Duty Cycle; C_L= 30pF; Unless Otherwise Specified (Continued)

(NOTE 2)

0^oC TO +70^oC

+25^oC

TYP

-40^oC TO +85^oC

PARAMETER

ANALOG INPUTS

TEST CONDITION

MIN

MAX

MIN

MAX

UNITS

Analog Input Resistance, R_IN

Analog Input Capacitance, C_IN

Analog Input Bias Current, IB

V_IN= 4V

V_IN= 0V

V_IN= 0V, 4V

4

-

10

60

±0.01

-

MΩ

pF

µA

-

±1.0

REFERENCE INPUTS

Total Reference Resistance, R_L

Reference Resistance Tempco, T_C

DIGITAL INPUTS

250

-

330

-

235

-

Ω

+0.31

Ω/°C

Input Logic High Voltage, V_IH

Input Logic Low Voltage, V_IL

Input Logic High Current, I_IH

Input Logic Low Current, I_IL

Input Capacitance, C_IN

2.0

-

7

-

2.0

V

µA

pF

-

0.8

1.0

-

0.8

1.0

-

V_IN= 5V

V_IN= 0V

DIGITAL OUTPUTS

Output Logic Sink Current, I_OL

Output Logic Source Current, I_OH

Output Leakage, I_OZ

V_O= 0.4V

3.2

-3.2

-

3.2

-3.2

-

mA

µA

pF

V_O= 4.5V

-

±1.0

-

±1.0

-

CE2 = 0V, V_O= 0V, 5V

CE2 = 0V

Output Capacitance, C_OUT

5.0

TIMING CHARACTERISTICS

Aperture Delay, t_AP

Aperture Jitter, t_AJ

Data Output Enable Time, t_EN

Data Output Disable Time, t_DIS

Data Output Delay, t_OD

Data Output Hold, t_H

-

6

-

25

20

25

-

30

25

30

-

ns

ps

ns

30

18

15

20

10

5

POWER SUPPLY REJECTION

Offset Error PSRR, ∆VOS

Gain Error PSRR, ∆FSE

V

_DD= 5V ±10%

-

±0.1

±2.75

-

±5.0

LSB

POWER SUPPLY CURRENT

Supply Current, I_DD

NOTES:

F_S= 20MHz

-

145

180

-

190

mA

9. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.

10. Parameter guaranteed by design or characterization and not production tested.

4-1494

HI-5700

Timing Waveforms

ENCODER DATA IS

LATCHED INTO THE

OUTPUT REGISTERS

COMPARATOR DATA

IS LATCHED

SAMPLE

N-1

SAMPLE

N

SAMPLE

N+1

SAMPLE

N+2

CLOCK

N-2

AUTO

BALANCE

t_AB

AUTO

BALANCE

AUTO

BALANCE

AUTO

BALANCE

INPUT

ANALOG

INPUT

t_AP

t_H

t_AJ

t_OD

DATA

OUTPUT

DATA N-4

DATA N-3

DATA N-2

DATA N-1

DATA N

FIGURE 1. INPUT-TO-OUTPUT TIMING

CE1

CE2

t_EN

t_DIS

HIGH

D0 - D7

DATA

IMPEDANCE

HIGH

IMPEDANCE

OVF

DATA

FIGURE 2. OUTPUT ENABLE TIMING

4-1495

HI-5700

Typical Performance Curves

8

7

6

5

4

V_DD= 5V, V_REF+ = 4V

T_A= 25^oC

7

6

F_S= 15MHz, f_IN= 100kHz

F_S= 20MHz, f_IN= 100kHz

F_S= 15MHz

F_S= 20MHz, f_IN= 3.85MHz

F_S= 20MHz

F_S= 15MHz, f_IN= 3.85MHz

5

4

-60 -40 -20

0

+20 +40 +60 +80 +100 +120 +140

TEMPERATURE (^oC)

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

INPUT FREQUENCY - f_IN(MHz)

FIGURE 4. EFFECTIVE NUMBER OF BITS vs TEMPERATURE

FIGURE 3. EFFECTIVE NUMBER OF BITS vs f_IN

-30

50

48

46

44

42

40

38

36

34

32

30

28

26

B.

D.

V_DD= 5V, V_REF+ = 4V

A.

-32

-34

-36

-38

-40

-42

-44

-46

-48

-50

B.

A. F_S= 15MHz, f_IN= 100kHz

B. F_S= 15MHz, f_IN= 4.43MHz

C. F_S= 20MHz, f_IN= 100kHz

D. F_S= 20MHz, f_IN= 4.43MHz

C.

A. F_S= 15MHz, f_IN= 100kHz

B. F_S= 15MHz, f_IN= 4.43MHz

C. F_S= 20MHz, f_IN= 100kHz

D. F_S= 20MHz, f_IN= 4.43MHz

A.

D.

-60 -40 -20

0

+20 +40 +60 +80 +100 +120 +140

TEMPERATURE (^oC)

-60 -40

-20

0

+20 +40 +60 +80 +100 +120 +140

TEMPERATURE (^oC)

FIGURE 5. SNR vs TEMPERATURE

FIGURE 6. TOTAL HARMONIC DISTORTION vs TEMPERATURE

1.0

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

V_DD= 5V, V_REF+ = 4V

f_IN= 100kHz

f

_IN= 100kHz

0.75

0.5

0.25

0

F_S= 20MHz

F_S= 15MHz

F_S= 20MHz

F_S= 15MHz

-60 -40 -20

0

+20 +40 +60 +80 +100 +120 +140

TEMPERATURE (^oC)

-60 -40 -20

0

+20 +40 +60 +80 +100 +120 +140

TEMPERATURE (^oC)

FIGURE 7. INL vs TEMPERATURE

FIGURE 8. DNL vs TEMPERATURE

4-1496

HI-5700

Typical Performance Curves (Continued)

8

2.0

1.5

1.0

0.5

0

V_DD= 5V, V_REF+ = 4V

7

F_S= 20MHz

6

F_S= 15MHz

5

4

3

2

F_S= 20MHz

F_S= 15MHz

-60 -40 -20

0

+20 +40 +60 +80 +100 +120 +140

TEMPERATURE (^oC)

-60 -40 -20

0

+20 +40 +60 +80 +100 +120 +140

TEMPERATURE (^oC)

FIGURE 9. OFFSET VOLTAGE vs TEMPERATURE

FIGURE 10. FULL SCALE ERROR vs TEMPERATURE

35

30

25

20

15

10

1.0

V_DD= 5V, V_REF+ = 4V

0.5

0

C

_LOAD= 30pF

PSRR VOS

t_OD

t_HOLD

PSRR FSE

-0.5

-1.0

-60 -40 -20

0

+20 +40 +60 +80 +100 +120 +140

TEMPERATURE (^oC)

-60 -40 -20

0

+20 +40 +60 +80 +100 +120 +140

TEMPERATURE (^oC)

FIGURE 11. OUTPUT DELAY vs TEMPERATURE

V_DD= 5V, V_REF+ = 4V

FIGURE 12. POWER SUPPLY REJECTION vs TEMPERATURE

180

200

190

180

170

160

150

140

130

120

110

100

90

170

V_DD= 5V, V_REF+ = 4V

160

T_A= 25^oC

150

D = 50%

140

130

120

110

100

90

t_AB

F_S= 20MHz

F_S= 1MHz

D =

t_AB+ t_S

D = 25%

80

70

60

50

40

30

D = 10%

10

80

-60 -40 -20

0

+20 +40 +60 +80 +100 +120 +140

TEMPERATURE (^oC)

0.1

1

100

CLOCK FREQUENCY (MHz)

FIGURE 13. SUPPLY CURRENT vs TEMPERATURE

FIGURE 14. SUPPLY CURRENT vs CLOCK DUTY CYCLE

4-1497

HI-5700

TABLE 1. PIN DESCRIPTION

DESCRIPTION

output word, plus an additional comparator to detect an

overflow condition.

PIN #

NAME

The CMOS HI-5700 works by alternately switching between

a “Sample” mode and an “Auto Balance” mode. Splitting up

the comparison process in this CMOS technique offers a

number of significant advantages. The offset voltage of each

CMOS comparator is dynamically canceled with each

conversion cycle such that offset voltage drift is virtually

eliminated during operation. The block diagram and timing

diagram illustrate how the HI-5700 CMOS flash converter

operates.

1

2

CLK

D7

Clock Input

Bit 7, Output (MSB)

Bit 6, Output

3

D6

4

D5

Bit 5, Output

5

D4

Bit 4, Output

6

¹/₄R

V_DD

GND

³/₄R

D3

¹/₄th Point of Reference Ladder

Digital Power Supply

Digital Ground

7

The input clock which controls the operation of the HI-5700

is first split into a non-inverting φ1 clock and an inverting φ2

clock. These two clocks, in turn, synchronize all internal

timing of analog switches and control logic within the

converter.

8

9

³/₄th Point of Reference Ladder

10

11

12

13

14

15

Bit 3, Output

D2

Bit 2, Output

In the “Auto Balance” mode (φ1), all φ1 switches close and

φ2 switches open. The output of each comparator is

momentarily tied to its own input, self-biasing the comparator

D1

Bit 1, Output

D0

Bit 0, Output (LSB)

Overflow, Output

midway between GND and V

and presenting a low

DD

OVF

CE2

impedance to a small input capacitor. Each capacitor, in

turn, is connected to a reference voltage tap from the

resistor ladder. The Auto Balance mode quickly precharges

all 256 input capacitors between the self-bias voltage and

each respective tap voltage.

Three-State Output Enable Input, Active High.

(See Table 2)

16

CE1

Three-State Output Enable Input, Active Low.

(See Table 2)

In the “Sample” mode (φ2), all φ1 switches open and φ2

switches close. This places each comparator in a sensitive

high gain amplifier configuration. In this open loop state, the

input impedance is very high and any small voltage shift at

the input will drive the output either high or low. The φ2 state

also switches each input capacitor from its reference tap to

the input signal. This instantly transfers any voltage

difference between the reference tap and input voltage to

the comparator input. All 256 comparators are thus driven

simultaneously to a defined logic state. For example, if the

input voltage is at mid-scale, capacitors precharged near

zero during φ1 will push comparator inputs higher than the

self bias voltage at φ2; capacitors precharged near the

reference voltage push the respective comparator inputs

lower than the bias point. In general, all capacitors

precharged by taps above the input voltage force a “low”

voltage at comparator inputs; those precharged below the

input voltage force “high” inputs at the comparators.

17

18

19

20

21

22

23

24

25

26

27

28

V_REF

+

Reference Voltage Positive Input

Analog Power Supply, +5V

Analog Ground

AV_DD

AGND

AV_DD

¹/₂R

Analog Ground

Analog Power Supply, +5V

¹/₂Point of Reference Ladder

Analog Power Supply, +5V

Analog Ground

AV_DD

AGND

AV_DD

Analog Ground

Analog Power Supply, +5V

Reference Voltage Negative Input

Analog Input

V_REF

V_IN

-

TABLE 2. CHIP ENABLE TRUTH TABLE

During the next φ1 Auto-Balancing state, comparator output

data is latched into the encoder logic block and the first

stage of encoding takes place. The following φ2 state

completes the encoding process. The 8 data bits (plus

overflow bit) are latched into the output flip-flops at the next

falling clock edge. The Overflow bit is set if the input voltage

CE1

CE2

D0 - D7

Valid

OVF

0

1

0

Valid

1

Three-State

X

Three-State

exceeds V

+ - 0.5 LSB. The output bus may be either

REF

X’s = Don’t Care.

enabled or disabled according to the state of CE1 and CE2

(See Table 2). When disabled, output bits assume a high

impedance state.

Theory of Operation

The HI-5700 is an 8-bit analog-to-digital converter based on

a parallel CMOS “flash” architecture. This flash technique is

an extremely fast method of A/D conversion because all bit

decisions are made simultaneously. In all, 256 comparators

As shown in the timing diagram, the digital output word

becomes valid after the second φ1 state. There is thus a one

and a half cycle pipeline delay between input sample and

digital output. “Data Output Delay” time indicates the slight

time delay for data to become valid at the end of the φ1

8

are used in the HI-5700: (2 -1) comparators to encode the

4-1498

HI-5700

HA-5033

+9V TO +12V

100Ω

0.01µF

ANALOG

SIGNAL

INPUT

10µF

CLOCK INPUT

V_IN

CLK

D7

1

2

28

27

V_REF

-

50Ω

+9V TO +12V

0.01µF

10µF

D6

3

AV_DD26

AGND 25

AGND 24

OUTPUT

PINS

D5

4

DIGITAL

V_DD

5

D4

ANALOG

V_DD(+5V)

TO ANALOG +5V

10µF

6

1/4R

V_DD

23

22

AV_DD

¹/₂R

7

ANALOG

GROUND

0.01µF

8

AV_DD21

GND

3/4R

AGND

20

19

18

17

16

15

9

TO ANALOG GND

D3

10

11

12

13

14

AGND

AV_DD

DIGITAL

GROUND

0.01µF

10µF

D2

OUTPUT

PINS

D1

V_REF

+

PRECISION

DC

REFERENCE

D0

CE1

CE2

OVF

+5V

FIGURE 15. TEST CIRCUIT

Applications Information

Voltage Reference

Digital Control and Interface

The reference voltage is applied across the resistor ladder

between V + and V -. In most applications, V - is

simply tied to analog ground such that the reference source

The HI-5700 provides a standard high speed interface to

external CMOS and TTL logic families. Two chip enable

inputs control the three-state outputs of output bits D0

through D7 and the Overflow (OVF) bit. As indicated in the

Truth Table, all output bits are high impedance when CE2 is

low, and output bits D0 through D7 are independently

controlled by CE1.

REF

drives V +. The reference must be capable of supplying

REF

enough current to drive the minimum ladder resistance of

235Ω over temperature.

The HI-5700 is specified for a reference voltage of 4.0V, but

will operate with voltages as high as the V

case of 4.0V reference operation, the converter encodes the

analog input into a binary output in LSB increments of

supply. In the

DD

Although the Digital Outputs are capable of handling typical

data bus loading, the bus capacitance charge/discharge

currents will produce supply and local group disturbances.

Therefore, an external bus driver is recommended.

(V

+ - V

-)/256, or 15.6mV. Reducing the reference

REF

voltage reduces the LSB size proportionately and thus

increases linearity errors. The minimum practical reference

voltage is about 2.5V. Because the reference voltage

terminals are subjected to internal transient currents during

conversion, it is important to drive the reference pins from a

low impedance source and to decouple thoroughly. Again,

ceramic and tantalum (0.01µF and 10µF) capacitors near

the package pin are recommended. It is not necessary to

Clock

The clock should be properly terminated to digital ground

near the clock input pin. Clock frequency defines the

conversion frequency and controls the converter as

described in the “Theory of Operation” section. The Auto

Balance φ1 half cycle of the clock may be reduced to

approximately 20ns; the Sample φ2 half cycle may be varied

from a minimum of 25ns to a maximum of 5µs.

1

3

decouple the / R, / R, and / R tap point pins for most

4

2

4

applications.

Signal Source

It is possible to elevate V

- from ground if necessary. In

REF

A current pulse is present at the analog input (V ) at the

this case, the V

- pin must be driven from a low

IN

REF

beginning of every sample and auto balance period. The

transient current is due to comparator charging and switch

feedthrough in the capacitor array. It varies with the

amplitude of the analog input and the converter’s sampling

impedance reference capable of sinking the current through

the resistor ladder. Careful decoupling is again

recommended.

4-1499

HI-5700

rate.

reference voltage is the ideal location.

The signal source must absorb these transients prior to the Quarter Point Adjustment

end of the sample period to ensure a valid signal for

The reference tap points are brought out for linearity

adjustment or creating a nonlinear transfer function if

conversion. Suitable broad band amplifiers or buffers which

exhibit low output impedance and high output drive include

the HA-5004, HA-5002, and HA-5003.

1

3

desired. It is not necessary to decouple the / R, / R, and /

4

2

R tap points in most applications.

4

The signal source may drive above or below the power supply

rails, but should not exceed 0.5V beyond the rails or damage

may occur. Input voltages of -0.5V to +0.5 LSB are converted

Power Supplies

The HI-5700 operates nominally from 5V supplies but will

work from 3V to 6V. Power to the device is split such that

analog and digital circuits within the HI-5700 are powered

separately. The analog supply should be well regulated and

“clean” from significant noise, especially high frequency

to all zeroes; input voltages of V

+ -0.5 LSB to V +0.5V

REF

DD

are converted to all ones with the Overflow bit set.

Full Scale Offset Error Adjustment

In applications where accuracy is of utmost importance, noise. The digital supply should match the analog supply

three adjustments can be made; i.e., offset, gain, and within about 0.5V and should be referenced externally to the

reference tap point trims. In general, offset and gain analog supply at a single point. Analog and digital grounds

correction can be done in the preamp circuitry.

should not be separated by more that 0.5V. It is

recommended that power supply decoupling capacitors be

Offset Adjustment

placed as close to the supply pins as possible.

A

combination of 0.01µF ceramic and 10µF tantalum

capacitors is recommended for this purpose as shown in the

test circuit.

Offset correction can be done in the preamp driving the

converter by introducing a DC component to the input signal.

An alternate method is to adjust V

- to produce the

REF

desired offset. It is adjusted such that the 0 to 1 code

transition occurs at 0.5 LSB.

Reducing Power Consumption

Power dissipation in the HI-5700 is related to clock

frequency and clock duty cycle. For a fixed 50% clock duty

cycle, power may be reduced by lowering the clock

frequency. For a given conversion frequency, power may be

reduced by decreasing the Auto-Balance (φ1) portion of the

clock duty cycle. This relationship is illustrated in the

Gain Adjustment

In general, full scale error correction can be done in the

preamp circuitry by adjusting the gain of the op amp. An

alternate method is to adjust the V

+ voltage. The

REF

TABLE 3. CODE TABLE

BINARY OUTPUT CODE

INPUT VOLTAGE †

V

_REF+ = 4.0V

_REF- = 0.0V

MSB

D7

1

LSB

D0

1

CODE

DESCRIPTION

DECIMAL

COUNT

(V)

OVF

D6

1

D5

1

D4

1

D3

1

D2

1

D1

1

Overflow (OVF)

Full Scale (FS)

FS - 1 LSB

4.000

3.9766

3.961

511

255

254

1

0

1

0

3/4 FS

1/2 FS

1/4 FS

2.992

1.992

0.992

192

128

64

0

1

0

1

0

1

0

1 LSB

Zero

0.0078

0

1

0

1

0

† The voltages listed above represent the ideal transition of each output code shown as a function of the reference voltage.

4-1500

HI-5700

Glossary of Terms

LSB: Least Significant Bit = (V

5700 specifications are given for a 15.6mV LSB size V

+ - V

-)/256. All HI-

REF

Aperture Delay: Aperture delay is the time delay between

the external sample command (the rising edge of the clock)

and the time at which the signal is actually sampled. This

delay is due to internal clock path propagation delays.

REF

+

REF

= 4.0V, V

- = 0.0V.

REF

Offset Error (VOS): Offset error is the difference between the

actual input voltage of the 0 to 1 code transition and the ideal

Aperture Jitter: This is the RMS variation in the aperture delay

due to variation of internal φ1 and φ2 clock path delays and

variation between the individual comparator switching times.

value of V

- + 0.5 LSB, V Error is expressed in LSBs.

REF

OS

Power Supply Rejection Ratio (PSRR): PSRR is

expressed in LSBs and is the maximum shift in code

transition points due to a power supply voltage shift. This is

measured at the 0 to 1 code transition point and the 254 to

255 code transition point with a power supply voltage shift

from the nominal value of 5.0V.

Differential Linearity Error (DNL): The differential linearity

error is the difference in LSBs between the spacing of the

measured midpoint of adjacent codes and the spacing of ideal

midpoints of adjacent codes. The ideal spacing of each

midpoint is 1.0 LSB. The range of values possible is from -1.0

LSB (which implies a missing code) to greater than +1.0 LSB.

Signal to Noise Ratio (SNR): SNR is the ratio in dB of the

RMS signal to RMS noise at specified input and sampling

frequencies.

Full Power Input Bandwidth: Full power input bandwidth is

the frequency at which the amplitude of the fundamental of

the digital output word has decreased 3dB below the

amplitude of an input sine wave. The input sine wave has a

peak-to-peak amplitude equal to the reference voltage. The

bandwidth given is measured at the specified sampling

frequency.

Signal to Noise and Distortion Ratio (SINAD): SINAD is

the ratio in dB of the RMS signal to the RMS sum of the

noise and harmonic distortion at specified input and

sampling frequencies.

Total Harmonic Distortion (THD): THD is the ratio in dBc of

the RMS sum of the first five harmonic components to the

RMS signal for a specified input and sampling frequency.

Full Scale Error (FSE): Full Scale Error is the difference

between the actual input voltage of the 254 to 255 code

transition and the ideal value of V

is expressed in LSBs.

+ - 1.5 LSB. This error

REF

Integral Linearity Error (INL): The integral linearity error is the

difference in LSBs between the measured code centers and

the ideal code centers. The ideal code centers are calculated

using a best fit line through the converter’s transfer function.

4-1501

HI-5700

Die Characteristics

DIE DIMENSIONS:

154.3 x 173.2 x 19 ± 1mils

METALLIZATION:

Type: Si - Al

Thickness: 11kÅ ± 1kÅ

GLASSIVATION:

Type: SiO

2

Thickness: 8kÅ ± 1kÅ

TRANSISTOR COUNT: 8000

SUBSTRATE POTENTIAL (Powered Up): V+

Metallization Mask Layout

HI-5700

26

25

4

3

2

1

28

27

D4

5

AGND

1/4R

V_DD

6

7

AGND

AV_DD

24

23

V_DD

GND

7

8

¹/₂R

22

21

AV_DD

AGND

8

20

3/4R

D3

9

AGND

AV_DD

19

10

11

12

13

14

15

16

17

18

4-1502


型号：	HI-5700
厂家：	Intersil
描述：	8-Bit, 20 MSPS Flash A/D Converter 8位， 20 MSPS的Flash A / D转换器转换器
文件：	总12页 (文件大小：733K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HI-5700 [INTERSIL]

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HI-5701/883

HI-5701883

HI-5701_05

HI-574

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HI-574A_01

HI-574A_08

HI-6010

HI-6010C