HI-5701 [INTERSIL]
6-Bit, 30MSPS, Flash A/D Converter; 6位， 30MSPS时，Flash A / D转换器
| 型号： | HI-5701 |
| 厂家： | 
Intersil |
| 描述： | 6-Bit, 30MSPS, Flash A/D Converter |
| 文件： | 总14页 (文件大小：154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-5701
Data Sheet
June 1999
File Number 2937.8
6-Bit, 30MSPS, Flash A/D Converter
Features
The HI-5701 is a monolithic, 6-bit, CMOS flash Analog-to-
Digital Converter. It is designed for high speed applications
where wide bandwidth and low power consumption are
essential. Its 30MSPS speed is made possible by a parallel
architecture which also eliminates the need for an external
sample and hold circuit. The HI-5701 delivers ±0.7 LSB
differential nonlinearity while consuming only 250mW (Typ)
at 30MSPS. Microprocessor compatible data output latches
are provided which present valid data to the output bus 1.5
clock cycles after the convert command is received. An
overflow bit is provided to allow the series connection of two
converters to achieve 7-bit resolution.
• 30MSPS with No Missing Codes
• Full Power Input Bandwidth . . . . . . . . . . . . . . . . . . 20MHz
• No Missing Codes Over Temperature
• Sample and Hold Not Required
• Single Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . +5V
• Power Dissipation (Max). . . . . . . . . . . . . . . . . . . . .300mW
• CMOS/TTL Compatible
• Overflow Bit
• /883 Version Available
The HI-5701 is available in Commercial and Industrial
temperature ranges and is supplied in 18 lead Plastic DIP
and SOIC packages
Applications
• Video Digitizing
• Radar Systems
Ordering Information
• Communication Systems
• High Speed Data Acquisition Systems
TEMP.
PKG.
NO.
o
PART NUMBER RANGE ( C)
PACKAGE
18 Ld PDIP
HI3-5701K-5
HI9P5701K-5
HI3-5701B-9
HI9P5701B-9
HI5701-EV
0 to 70
0 to 70
-40 to 85
-40 to 85
25
E18.3
Pinout
18 Ld SOIC
M18.3
E18.3
M18.3
HI-5701
(PDIP, SOIC)
TOP VIEW
18 Ld PDIP
18 Ld SOIC
Evaluation Board
D5 (MSB)
OVF
1
2
3
4
5
6
7
8
9
18
17
16
15
14
D4
D3
1
/ R
V
2
SS
NC
CE2
D2
D1
13 D0 (LSB)
12
CE1
CLK
V
V
V
DD
11
10
PHASE
IN
V
+
-
REF
REF
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
HI-5701
Functional Block Diagram
φ1
φ2
φ1
φ1
φ2
V
IN
D
R/2
OVERFLOW
(OVF)
Q
Q
Q
Q
Q
Q
Q
V
+
REF
CL
COMP 64
D
R
R
D5 (MSB)
D4
CL
D
CL
COMP 63
COMP 32
COMP 2
COMPARATOR
LATCHES
AND
63 TO 6
ENCODER
LOGIC
R
R
R
D
D3
1
CL
/ R
2
D
D2
CL
D
D1
CL
R
D
D0 (LSB)
CL
V
-
REF
R/2
COMP 1
CE1
CE2
CLOCK
PHASE
V
φ2 (SAMPLE)
DD
V
SS
φ1 (AUTO BALANCE)
2
HI-5701
Absolute Maximum Ratings
Thermal Information
o
Supply Voltage, V
DD
Analog and Reference Input Pins (VSS - 0.5) < V
Digital I/O Pins . . . . . . . . . . . . . . . .(VSS - 0.5) < V < (V
I/O
to V
SS
. . . . . . . . . . . (VSS - 0.5) < V
< +7V
+0.5V)
+0.5V)
Thermal Resistance (Typical, Note 1)
θJA ( C/W)
DD
DD
DD
< (V
INA
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
105
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
o
Maximum Power Dissipation at 70 C (Note 2) . . . . . . . . . . .635mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
o
Operating Conditions
o
o
Temperature Range
HI3-5701-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C
HI9P5701-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
o
o
o
(SOIC - Lead Tips Only)
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
Electrical Specifications
V
C
= +5.0V; V
= 30pF; Unless Otherwise Specified
+ = +4.0V; V
REF-
= V = GND; f = Specified Clock Frequency at 50% Duty Cycle;
SS
DD
REF
S
L
(NOTE 3)
o
o
0 C TO 70 C
o
o
o
25 C
-40 C TO 85 C
PARAMETER
SYSTEM PERFORMANCE
Resolution
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
6
-
-
-
-
-
-
-
-
-
-
6
-
-
-
-
-
-
-
-
-
±2.0
-
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Integral Linearity Error, INL
(Best Fit Line)
f
f
f
f
f
f
f
f
= 20MHz
±0.5
±1.5
±0.3
±0.7
±0.5
±0.5
±0.25
±0.25
±1.25
S
S
S
S
S
S
S
S
= 30MHz
-
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
= 20MHz
±0.6
±0.75
= 30MHz
-
±2.0
-
Offset Error, V
OS
(Adjustable to Zero)
= 20MHz (Note 3)
= 30MHz
±2.5
-
±2.5
-
Full Scale Error, FSE
(Adjustable to Zero)
= 20MHz (Note 3)
= 30MHz
±2.0
-
DYNAMIC CHARACTERISTICS
Maximum Conversion Rate
Minimum Conversion Rate
Full Power Input Bandwidth
Signal to Noise Ratio, SNR
No Missing Codes
30
-
40
-
-
30
-
-
MSPS
MSPS
MHz
dB
No Missing Codes (Note 3)
0.125
0.125
f
f
f
= 30MHz
-
20
36
31
-
-
-
-
-
-
-
S
S
S
= 1MHz, f = 100kHz
IN
-
-
RMS Signal
= --------------------------------
RMS Noise
= 30MHz, f = 4MHz
IN
-
-
dB
Signal to Noise Ratio, SINAD
f
f
= 1MHz, f = 100kHz
IN
-
-
35
30
-
-
-
-
-
-
dB
dB
S
S
RMS Signal
= 30MHz, f = 4MHz
IN
= -------------------------------------------------------------
RMS Noise + Distortion
Total Harmonic Distortion
f
f
f
f
= 1MHz, f = 100kHz
IN
-
-
-
-
-44
-38
2
-
-
-
-
-
-
-
-
-
-
-
-
dBc
dBc
S
S
S
S
= 30MHz, f = 4MHz
IN
Differential Gain
= 14.32MHz, f = 3.58MHz
IN
%
Differential Phase
= 14.32MHz, f = 3.58MHz
IN
2
Degree
3
HI-5701
Electrical Specifications
V
C
= +5.0V; V
+ = +4.0V; V
REF-
= V = GND; f = Specified Clock Frequency at 50% Duty Cycle;
SS
DD
REF
S
= 30pF; Unless Otherwise Specified (Continued)
L
(NOTE 3)
o
o
0 C TO 70 C
o
o
o
25 C
-40 C TO 85 C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
ANALOG INPUTS
Analog Input Resistance, R
V
V
V
= 4V
-
-
-
30
20
-
-
-
-
-
-
-
MΩ
pF
IN
IN
IN
IN
Analog Input Capacitance, C
= 0V
IN
Analog Input Bias Current, IB
REFERENCE INPUTS
= 0V, 4V
0.01
±1.0
±1.0
µA
Total Reference Resistance, R
250
-
370
-
-
235
-
-
-
Ω
L
o
Reference Resistance Tempco, T
+0.266
Ω/ C
C
DIGITAL INPUTS
Input Logic High Voltage, V
IH
2.0
-
-
-
2.0
-
V
Input Logic Low Voltage, V
-
-
-
-
0.8
1.0
1.0
-
-
-
-
-
0.8
1.0
1.0
-
V
IL
Input Logic High Current, I
V
V
= 5V
= 0V
-
µA
µA
pF
IH
IN
IN
Input Logic Low Current, I
-
IL
Input Capacitance, C
7
IN
DIGITAL OUTPUTS
Output Logic Sink Current, I
OL
V
= 0.4V
= 4.5V
3.2
-
-
-
3.2
-
mA
mA
µA
pF
O
Output Logic Source Current, I
V
-3.2
-
±1.0
-
-3.2
-
±1.0
-
OH
O
Output Leakage, I
CE2 = 0V
CE2 = 0V
-
-
-
-
-
OFF
Output Capacitance, C
5.0
OUT
TIMING CHARACTERISTICS
Aperture Delay, t
-
-
6
-
-
-
-
-
-
ns
ps
ns
ns
ns
ns
AP
Aperture Jitter, t
AJ
30
12
11
14
10
Data Output Enable Time, t
(Note 3)
(Note 3)
(Note 3)
(Note 3)
-
20
20
20
-
-
20
20
20
-
EN
Data Output Disable Time, t
-
-
DIS
Data Output Delay, t
-
-
OD
Data Output Hold, t
5
5
H
POWER SUPPLY REJECTION
Offset Error PSRR, ∆V
V
V
= 5V ±10%
= 5V ±10%
-
-
±0.1
±0.1
±1.0
±1.0
-
-
±1.5
±1.5
LSB
LSB
OS
DD
DD
Gain Error PSRR, ∆FSE
POWER SUPPLY CURRENT
Supply Current, I
NOTE:
f
= 20MHz
S
-
50
60
-
75
mA
DD
3. Parameter guaranteed by design or characterization and not production tested.
4
HI-5701
Timing Waveforms
COMPARATOR DATA
IS LATCHED
ENCODED DATA IS
LATCHED INTO THE
OUTPUT REGISTERS
CLOCK
INPUT
PHASE - HIGH
φ1
φ1
φ1
φ1
φ2
φ2
φ2
φ2
φ2
SAMPLE
N - 2
SAMPLE
N - 1
SAMPLE
N
SAMPLE
N + 1
SAMPLE
N + 2
CLOCK
INPUT
PHASE - LOW
AUTO
AUTO
BALANCE
AUTO
BALANCE
AUTO
BALANCE
BALANCE
t
S
t
AB
ANALOG
INPUT
t
AP
t
t
H
AJ
t
OD
DATA
OUTPUT
DATA N - 4
DATA N - 3
DATA N - 2
DATA N - 1
DATA N
FIGURE 1. INPUT-TO-OUTPUT TIMING
CE1
CE2
t
t
t
t
DIS
EN
EN
DIS
HIGH
HIGH
D0 - D5
DATA
DATA
DATA
DATA
IMPEDANCE
DATA
IMPEDANCE
HIGH
OVF
IMPEDANCE
FIGURE 2. OUTPUT ENABLE TIMING
5
HI-5701
Typical Performance Curves
6
6
5
4
3
f
= 20MHz
S
f
= 1MHz, f = 100kHz
IN
S
5
4
f
= 30MHz
= 40MHz
S
f
= 30MHz, f = 4MHz
IN
S
f
S
V
= 5V, V
o
+ = 4V
REF
DD
T
= 25 C
A
V
= 5V, V + = 4V
REF
DD
3
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
10 20 30 40 50 60 70 80 90
-40 -30 -20 -10
o
INPUT FREQUENCY (f ) - MHz
TEMPERATURE ( C)
IN
FIGURE 3. EFFECTIVE NUMBER OF BITS vs f
IN
FIGURE 4. ENOB vs TEMPERATURE
38
36
34
32
30
28
26
24
-34
-36
-38
-40
-42
-44
-46
V
= 5V, V
REF
+ = 4V
f
= 1MHz, f = 100kHz
DD
S IN
f
= 30MHz, f = 4MHz
IN
S
f
= 30MHz, f = 4MHz
IN
S
V
= 5V, V + = 4V
REF
DD
f
= 1MHz, f = 100kHz
IN
S
0
10 20 30 40 50 60 70 80 90
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
-40 -30 -20 -10
o
o
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 5. SNR vs TEMPERATURE
FIGURE 6. TOTAL HARMONIC DISTORTION vs TEMPERATURE
1
2
f
= 100kHz
f
= 100kHz
IN
IN
V
= 5V, V + = 4V
REF
DD
V
= 5V, V + = 4V
REF
DD
1.5
0.75
0.5
0.25
0
f
= 30MHz
= 1MHz
f
= 30MHz
S
S
1
0.5
f
f
= 1MHz
S
S
0
0
10 20 30 40 50 60 70 80 90
0
10 20 30 40 50 60 70 80 90
-40 -30 -20 -10
-40 -30 -20 -10
o
(o
TEMPERATURE ( C)
TEMPERATURE C)
FIGURE 7. INL vs TEMPERATURE
FIGURE 8. DNL vs TEMPERATURE
6
HI-5701
Typical Performance Curves (Continued)
1
60
55
V
= 5V, V + = 4V
REF
DD
V
= 5V ±10%, V
+ = 4V
REF
DD
50
45
40
0.5
0
f
= 20MHz
S
PSRR V
OS
35
30
25
20
15
10
PSRR FSE
-0.5
-1
f
= 1MHz
60
S
0
10 20 30 40 50 60 70 80 90
-40
-20
0
20
40
80
100
-40 -30 -20 -10
o
o
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 9. POWER SUPPLY REJECTION vs TEMPERATURE
FIGURE 10. SUPPLY CURRENT vs TEMPERATURE
6.0
60
f = 1MHz
V
= 5V, V
o
+ = 4V
REF
I
DD
55
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
T
= 25 C
D = 50%
A
50
45
40
D = 25%
t
AB
D = -----------------------
+ t
t
35
30
25
20
15
10
AB
S
D = 10%
30
40
50
60
0.1
1
10
100
CLOCK FREQUENCY (MHz)
CLOCK FREQUENCY (MHz)
FIGURE 11. SUPPLY CURRENT vs CLOCK AND DUTY CYCLE
FIGURE 12. EFFECTIVE NUMBER OF BITS vs CLOCK
FREQUENCY
7
HI-5701
eliminated during operation. The block diagram and timing
diagram illustrate how the HI-5701 CMOS flash converter
operates.
TABLE 1. PIN DESCRIPTIONS
NAME DESCRIPTION
Bit 6, Output (MSB).
PIN #
1
2
3
4
5
D5
The input clock which controls the operation of the HI-5701
is first split into a non-inverting φ1 clock and an inverting φ2
clock. These two clocks, in turn, synchronize all internal
timing of analog switches and control logic within the
converter.
OVF
Overflow, Output.
Digital Ground.
No Connection.
V
SS
NC
CE2
Three-State Output Enable Input, Active
High (See Table 2).
In the “Auto Balance” mode (φ1), all φ1 switches close and
φ2 switches open. The output of each comparator is
momentarily tied to its own input, self-biasing the comparator
6
CE1
Three-State Output Enable Input, Active
Low (See Table 2).
midway between V and V
and presenting a low
SS
DD
7
8
CLK
Clock Input.
impedance to a small input capacitor. Each capacitor, in
turn, is connected to a reference voltage tap from the
resistor ladder. The Auto Balance mode quickly precharges
all 64 input capacitors between the self-bias voltage and
each respective tap voltage.
PHASE
Sample Clock Phase Control Input. When
Phase is Low, Sample Unknown (φ1) Oc-
curs When the Clock is Low and Auto Bal-
ance (φ2) Occurs When the Clock is High
(See Text).
9
V
V
V
V
+
-
Reference Voltage Positive Input.
Reference Voltage Negative Input.
Analog Signal Input.
Power Supply, +5V.
Bit 1, Output (LSB).
Bit 2, Output.
In the “Sample” mode (φ2), all φ1 switches open and φ2
switches close. This places each comparator in a sensitive
high gain amplifier configuration. In this open loop state, the
input impedance is very high and any small voltage shift at
the input will drive the output either high or low. The φ2 state
also switches each input capacitor from its reference tap to
the input signal. This instantly transfers any voltage
difference between the reference tap and input voltage to the
comparator input. All 64 comparators are thus driven
simultaneously to a defined logic state. For example, if the
input voltage is at mid-scale, capacitors precharged near
zero during φ1 will push comparator inputs higher than the
self bias voltage at φ2; capacitors precharged near the
reference voltage push the respective comparator inputs
lower than the bias point. In general, all capacitors
REF
REF
IN
10
11
12
13
14
15
16
17
18
DD
D0
D1
D2
1
Bit 3, Output.
/
R2
Reference Ladder Midpoint.
Bit 4, Output.
2
D3
D4
Bit 5, Output.
TABLE 2. CHIP ENABLE TRUTH TABLE
precharged by taps above the input voltage force a “low”
voltage at comparator inputs; those precharged below the
input voltage force “high” inputs at the comparators.
CE1
CE2
D0 - D5
OVF
0
1
1
0
Valid
Valid
Valid
1
Three-State
Three-State
During the next φ1 state, comparator output data is latched
into the encoder logic block and the first stage of encoding
takes place. The following φ2 state completes the encoding
process. The 6 data bits (plus overflow bit) are latched into
X
Three-State
X = Don’t Care
Theory of Operation
the output flip-flops at the next falling clock edge. The
1
Overflow bit is set if the input voltage exceeds V
+ - /
2
REF
The HI-5701 is a 6-bit analog-to-digital converter based on a
parallel CMOS “flash” architecture. This flash technique is an
extremely fast method of A/D conversion because all bit
decisions are made simultaneously. In all, 64 comparators
are used in the HI-5701; 63 comparators to encode the
output word, plus an additional comparator to detect an
overflow condition.
LSB. The output bus may be either enabled or disabled
according to the state of CE1 and CE2 (See Table 2). When
disabled, output bits assume a high impedance state.
As shown in the timing diagram, the digital output word
becomes valid after the second φ1 state. There is thus a one
and a half cycle pipeline delay between input sample and
digital output. “Data Output Delay” time indicates the slight
time delay for data to become valid at the end of the φ1 state.
Refer to the Glossary of Terms for other definitions.
The CMOS HI-5701 works by alternately switching between
a “Sample” mode and an “Auto Balance” mode. Splitting up
the comparison process in this CMOS technique offers a
number of significant advantages. The offset voltage of each
CMOS comparator is dynamically canceled with each
conversion cycle such that offset voltage drift is virtually
8
HI-5701
D5
D4
DATA
OVF
D3
OUPUT
V
1/2R
NC
SS
D2
D1
D0
+5V
CE2
CE1
V
+5V
10µF
10µF
DD
10µF
0.01µF
CLOCK
INPUT
CLK
+9V to +12V
50Ω
0.01µF
ANALOG
SIGNAL
INPUT
V
PHASE
IN
100Ω
HA-5033
50Ω
V
V
REF-
+4V
REF+
10µF
0.01µF
0.01µF
-9V to -12V
FIGURE 13. TEST CIRCUIT
clock and phase inputs control the sample and auto balance
modes. The digital outputs change state on the clock phase
which begins the sample mode. Two chip enable inputs
control the three-state outputs of output bits D0 through D5
and the Overflow OVF bit. As indicated in Table 2, all output
bits are high impedance when CE2 is low, and output bits D0
through D5 are independently controlled by CE1.
Application Information
Voltage Reference
The reference voltage is applied across the resistor ladder at
the input of the converter, between V + and V -. In
REF REF
most applications, V
- is simply tied to analog ground
REF
such that the reference source drives V
+. The reference
REF
must be capable of supplying enough current to drive the
minimum ladder resistance of 235Ω over temperature.
Although the Digital Outputs are capable of handling typical
data bus loading, the bus capacitance charge/discharge
currents will produce supply and local ground disturbances.
Therefore, an external bus driver is recommended.
The HI-5701 is specified for a reference voltage of 4.0V, but
will operate with voltages as high as the V
supply. In the
DD
case of 4.0V reference operation, the converter encodes the
analog input into a binary output in LSB increments of
Clock
The clock should be properly terminated to digital ground
near the clock input pin. Clock frequency defines the
conversion frequency and controls the converter as
described in the “Theory of Operation” section. The Auto
Balance φ1 half cycle of the clock may be reduced to 16ns;
the Sample φ2 half cycle may be varied from a minimum of
16ns to a maximum of 8µs.
(V
+ -V
)/64, or 62.5mV. Reducing the reference
REF
REF
voltage reduces the LSB size proportionately and thus
increases linearity errors. The minimum practical reference
voltage is about 2V. Because the reference voltage terminals
are subjected to internal transient currents during
conversion, it is important to drive the reference pins from a
low impedance source and to decouple thoroughly. Again,
ceramic and tantalum (0.01µF and 10µF) capacitors near
TABLE 3. PHASE CONTROL
the package pin are recommended. It is not necessary to
1
CLOCK
PHASE
INTERNAL GENERATION
Sample Unknown (φ2)
Auto Balance (φ1)
decouple the / R tap point pin for most applications.
2
0
0
1
1
0
1
0
1
It is possible to elevate V
this case, the V
REF
- from ground if necessary. In
- pin must be driven from a low
REF
impedance reference capable of sinking the current through
the resistor ladder. Careful decoupling is again
recommended.
Auto Balance (φ1)
Sample Unknown (φ2)
Gain and Offset Adjustment
Digital Control and Interface
In applications where accuracy is of utmost importance,
three adjustments can be made; i.e., offset, gain, and
The HI-5701 provides a standard high speed interface to
external CMOS and TTL logic families. Four digital inputs
are provided to control the function of the converter. The
9
HI-5701
midpoint trim. In general, offset and gain correction can be
done in the preamp circuitry.
Signal Source
A current pulse is present at the analog input (V ) at the
IN
beginning of every sample and auto balance period. The
transient current is due to comparator charging and switch
feed through in the capacitor array. It varies with the
amplitude of the analog input and the sampling rate.
Offset Adjustment
The preferred offset correction method is to introduce a DC
component to V of the converter. An alternate method is to
IN
adjust the V
- input to produce the desired offset
REF
adjustment. The theoretical input voltage to produce the first
The signal source must be capable of recovering from the
transient prior to the end of the sample period to ensure a
valid signal for conversion. Suitable broad band amplifiers or
buffers which exhibit low output impedance and high output
drive include the HFA-0005, HA-5004, HA-5002, and HA-
5033.
1
transition is / LSB.
2
1
1
V
(0 to 1 transition) = / LSB = / (V
/64) = V
/128.
REF
IN
2
2
REF
Gain Adjustment
In general, full scale error correction can be done in the
preamp circuitry by adjusting the gain of the op amp. An
alternate method is to adjust the V + input voltage. This
The signal source may drive above or below the power
REF
supply rails, but should not exceed 0.5V beyond the rails or
1
adjustment is performed by setting V to the 63 to overflow
IN
damage may occur. Input voltages of -0.5V to + / LSB are
2
1
transition. The theoretical input voltage to produce the
1
converted to all zeros; input voltages of V
+ - / LSB to
REF
2
transition is / LSB less than V
2
+ and is calculated as
REF
V
+ 0.5 are converted to all ones with the Overflow bit set.
DD
follows:
Power Supply
V
(63 to 64 transition) = V
REF
- (V
/128)
REF
IN
= V
The HI-5701 operates nominally from a 5V supply, but will
function from 3V to 6V. The supply should be well regulated
and “clean” of significant noise, especially high frequency
noise. It is recommended that power supply decoupling
capacitors be placed as close to the supply pin as possible.
A combination of 0.01µF ceramic and 10µF tantalum
capacitors is recommended for this purpose as shown in the
test circuit Figure 13.
(127/128).
REF
To perform the gain trim, first do the offset trim and then
apply the required V for the 63 to overflow transition. Now
IN
+ until that transition occurs on the outputs.
adjust V
REF
Midpoint Trim
1
The reference center ( / R) is available to the user as the
2
midpoint of the resistor ladder. The / R point can be used
to improve linearity or create unique transfer functions. The
offset and gain trims should be done prior to adjusting the
midpoint. The theoretical transition from count 31 to 32
occurs at 31.5 LSBs. That voltage is calculated as follows:
1
2
Reducing Power Consumption
Power dissipation in the HI-5701 is related to clock frequency
and clock duty cycle. For a fixed 50% clock duty cycle, power
may be reduced by lowering the clock frequency. For a given
conversion frequency, power may be reduced by shortening
the Auto Balance φ1 portion of the clock duty cycle.
V
(31 to 32 transition) = 31.5(V
REF
/64) = V
(63/128).
1
IN
REF
An adjustable voltage follower can be used to drive the / R
2
pin. Set V to the 31 to 32 transition voltage, then adjust the
IN
voltage follower until the transition occurs on the output bits.
TABLE 4. OUTPUT CODE TABLE
BINARY OUTPUT CODE
INPUT VOLTAGE†
V
+ = 4V
- = 0V
REF
MSB
D5
1
LSB
D0
1
CODE
DESCRIPTION
V
DECIMAL
COUNT
REF
(V)
OVF
D4
1
D3
1
D2
1
D1
1
Overflow (OVF)
Full Scale (FS)
FS - 1 LSB
4.000
127
63
1
0
0
3.9063
1
1
1
1
1
1
3.8438
62
1
1
1
•
1
1
0
•
•
•
•
3
/
FS
2.9688
48
0
1
1
0
•
•
0
0
0
4
•
•
•
•
10
HI-5701
TABLE 4. OUTPUT CODE TABLE (Continued)
BINARY OUTPUT CODE
INPUT VOLTAGE†
V
+ = 4V
- = 0V
REF
MSB
D5
1
LSB
D0
0
CODE
DESCRIPTION
V
DECIMAL
COUNT
REF
(V)
OVF
D4
D3
D2
D1
1
/
FS
1.9688
32
0
0
0
•
0
0
2
•
•
•
•
•
1
/
FS
0.9688
16
0
0
1
0
•
•
0
0
0
4
•
•
•
•
1 LSB
Zero
0.0313
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
† The voltages listed above represent the ideal transition of each output code shown as a function of the reference voltage.
Offset Error, V
- Offset error is the difference between
the actual input voltage of the 0 to 1 code transition and the
Glossary of Terms
OS
Aperture Delay - is The time delay between the external
sample command (the rising edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
ideal value of V
LSBs.
- + 0.5 LSB. V error is expressed in
OS
REF
Power Supply Rejection Ratio, PSRR - Is expressed in
LSBs and is the maximum shift in code transition points due
to a power supply voltage shift. This is measured at the 0 to
1 code transition point and the 62 to 63 code transition point
with a power supply voltage shift from the nominal value of
5.0V.
Aperture Jitter, t
AJ
- This is the RMS variation in the
aperture delay due to variation of internal φ1 and φ2 clock
path delays and variation between the individual comparator
switching times.
Differential Linearity Error, DNL - The differential linearity
error is the difference in LSBs between the spacing of the
measured midpoint of adjacent codes and the spacing of
ideal midpoints of adjacent codes. The ideal spacing of each
midpoint is 1 LSB. The range of values possible is from
-1 LSB (which implies a missing code) to greater than
+1 LSB.
Signal to Noise Ratio, SNR - SNR is the ratio in dB of the
RMS signal to RMS noise at specified input and sampling
frequencies.
Signal to Noise and Distortion Ratio, SINAD - Is the ratio
in dB of the RMS signal to the RMS sum of the noise and
harmonic distortion at specified input and sampling
frequencies.
Full Power Input Bandwidth - Full power bandwidth is the
frequency at which the amplitude of the fundamental of the
digital output word has decreased 3dB below the amplitude
of an input sine wave. The input sine wave has a peak-to-
peak amplitude equal to the reference voltage. The
bandwidth given is measured at the specified sampling
frequency.
Total Harmonic Distortion, THD - Is the ratio in dBc of the
RMS sum of the first five harmonic components to the RMS
signal for a specified input and sampling frequency
Full Scale Error, FSE - is The difference between the actual
input voltage of the 63 to 64 code transition and the ideal
value of V
REF
+ - 1.5 LSB. This error is expressed in LSBs.
Integral Linearity Error, INL - The integral linearity error is
the difference in LSBs between the measured code centers
and the ideal code centers. The ideal code centers are
calculated using a best fit line through the converter’s
transfer function.
LSB - Least Significant Bit = (V
+ - V
-)/64. All
REF
REF
HI-5701 specifications are given for a 62.5mV LSB size
+ = 4V, V - = 0V.
V
REF
REF
11
HI-5701
Die Characteristics
DIE DIMENSIONS:
WORST CASE CURRENT DENSITY:
5
2
86.6 mils x 130.7 mils x 19 mils ±1 mil
<2.0 x 10 A/cm
METALLIZATION:
TRANSISTOR COUNT:
Type: SiAl
4000
Thickness: 11kÅ ±1kÅ
SUBSTRATE POTENTIAL (POWERED UP):
PASSIVATION:
V+
Type: SiO
2
Thickness: 8kÅ ±1kÅ
Metallization Mask Layout
HI-5701
V
(3)
SS
1
(16)
/
R
2
(15) D2
CE2 (5)
(14) D1
(13) D0
(12) V
DD
CE1 (6)
12
HI-5701
Dual-In-Line Plastic Packages (PDIP)
N
E18.3 (JEDEC MS-001-BC ISSUE D)
E1
18 LEAD DUAL-IN-LINE PLASTIC PACKAGE
INDEX
AREA
1 2
3
N/2
INCHES
MILLIMETERS
-B-
-C-
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-A-
A
A1
A2
B
-
4
D
E
0.015
0.115
0.014
0.045
0.008
0.845
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
21.47
0.13
7.62
6.10
4
BASE
PLANE
A2
A
0.195
0.022
0.070
0.014
0.880
-
4.95
0.558
1.77
0.355
22.35
-
-
SEATING
PLANE
-
L
C
L
B1
C
8, 10
D1
B1
eA
A1
A
D1
-
e
eC
C
B
D
5
eB
0.010 (0.25) M
C
B S
D1
E
5
NOTES:
0.325
0.280
8.25
7.11
6
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
E1
e
5
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
e
e
6
A
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
-
0.430
0.150
-
10.92
3.81
7
B
4. Dimensions A, A1 and L are measured with the package seated in
L
0.115
2.93
4
9
JEDEC seating plane gauge GS-3.
N
18
18
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
Rev. 0 12/93
e
6. E and
are measured with the leads constrained to be
A
-C-
perpendicular to datum
.
7. e and e are measured at the lead tips with the leads unconstrained.
B
C
e
must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
13
HI-5701
Small Outline Plastic Packages (SOIC)
N
M18.3 (JEDEC MS-013-AB ISSUE C)
INDEX
AREA
0.25(0.010)
M
B M
H
18 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
11.35
7.40
MAX
2.65
0.30
0.51
0.32
11.75
7.60
NOTES
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
0.4625
0.2992
-
1
2
3
L
-
9
SEATING PLANE
A
0.0091
0.4469
0.2914
-
-A-
o
h x 45
D
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
C
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
α
18
18
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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14
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