HI-6010 [HOLTIC]
ARINC 429 TRANSMITTER/RECEIVER FOR 8 BIT BUS; ARINC 429发射器/接收器， 8位总线
| 型号： | HI-6010 |
| 厂家： | 
HOLT INTEGRATED CIRCUITS |
| 描述： | ARINC 429 TRANSMITTER/RECEIVER FOR 8 BIT BUS |
| 文件： | 总12页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-6010
GENERAL DESCRIPTION
FEATURES
The HI-6010 is a CMOS integrated circuit designed to
interface the avionics data bus standard ARINC 429 to an
8 bit port. It contains one receiver and one transmitter.
They operate independently except for the self test option
and the parity option. The receiver demands that the
incoming data meet the standard protocol and the
transmitteroutputs a standard protocolstream.
!
ARINC 429 protocol controller with interface to
an 8 bit bus
!
!
!
!
!
Automatic label recognition option
8 bit or 32 bit buffering option
Self test and parity options
CMOS / TTL logic pins
The HI-6010 provides flexible options for interfacing to the
user system. The controlling processor can operate both
the receiver and transmitter either by using hard wired
flags and gates at the pins or by using softwa re reads and
writes of the Status Register and Control Register or a
combination thereof.
Plastic and ceramic package options - surface
mount or DIP
!
Military processing available
The chip is programmable to operate with single 8 bit
bytes requiring "on the fly transmitter loading and receiver
downloading" or to operate in 32 bit "extended buffer"
mode. In addition there is an option to use automatic label
recognition after loading 8 possible labels for comparison.
Parity and self test are also software programmable.
Master Reset isactivated onlybytaking theMRpinhigh.
PIN CONFIGURATION (Top View)
VSS
WEF
1
2
3
4
5
6
7
8
9
28 RE
27 C/D
26 CS
25 WE
24 D7
23 D6
22 D5
21 D4
20 D3
19 D2
18 D1
17 D0
16 RXD1
15 VDD
CTS
TXC
HFS
Two clock inputs allow independent selection of the data
rates of the transmitter and receiver. Each must b e 4X the
desired ARINC 429 frequency.
MR
TXE
RXRDY
TXRDY
Error flags are generated for transmitter underwrites and
for receiver data framing miscues, parity errors, and buffer
overwrites.
TXD0 10
TXD1 11
RXC 12
FCR 13
RXD0 14
The HI-6010 is a 5 volt chip that will require data transla-
tion from and to the ARINC bus. The HI-8482 and HI-8588
line receivers are available for the receiver side and the
HI-318X, HI-838X and HI-858X line drivers are available
for the transmitter side. The HI-8590 is also available with
a line driver and a line receiver in a single 16-pin thermally
enhanced ESOIC package.
Pin numbers apply for plastic and ceramic DIP and
for plastic PLCC. Consult factory for pin out of 48
leadceramicleadlesschipcarrier.
! Avionics Data Communication
! Serial to Parallel Conversion
! Parallel to Serial Conversion
! VDD = 5.0 VOLTS ±5%
! VSS = 0.0 VOLTS
HOLT INTEGRATED CIRCUITS
4-3
(DS6010 Rev. A)
01/01
HI-6010
PIN
SYMBOL FUNCTION
DESCRIPTION
1
VSS
WEF
CTS
TXC
HFS
MR
POWER
OUTPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
OUTPUT
INPUT
POWER
INPUT
I / O
0.0 Volts
2
Error indication if high. Status register must be read to determine specific error.
Enables data transmission when low.
Source clock for data transmission. 4 times bit rate.
Hardware feature select.
3
4
5
6
Master reset, active high.
7
TXE
RXRDY
TXRDY
TXD0
TXD1
RXC
FCR
RXD0
VDD
RXD1
D0
Low when transmission in progress.
High when data of received word is available.
High when data of a transmitted word may be input.
"Zeroes" data output of transmitter.
"Ones" data output of transmitter.
Source clock for data reception. 4 times bit rate.
First character received flag.
"Zeroes" data input to receiver.
5 Volts ±5%
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
"Ones" data input to receiver.
Data bus
D1
I / O
Data bus
D2
I / O
Data bus
D3
I / O
Data bus
D4
I / O
Data bus
D5
I / O
Data bus
D6
I / O
Data bus
D7
I / O
Data bus
WE
INPUT
INPUT
INPUT
INPUT
8 bit data bus input control active low.
Chip select, active low.
CS
C/D
High for control or status register operations, low for data
8 bit data bus output control, active low.
RE
goes high for any one of three receiver errors. The status
register will showwhich ofthethreeerrors occurred:
Status Register Bit
Error
The receiver logic is independent of the transmitter except in
the followingways:
SR3
SR4
SR5
Received a parity error
Data Overwritten
Receiving sequence error
1. SelfTest
2. Parity Option
The possible Receiver sequence errors are:
1. RXD0 and RXD1 simultaneously a one.
2. Less than 32 bits before 3 nulls.
3. More than 32 bits.
In self test, the transmitter outputs route to the receiver inputs
internally ignoring the external inputs. Also in self test, the
external receiver clock is replaced with thetransmitter clock.
The parity option affects both the receiver and transmitter.
Eitherboth areoperational or neither.
There are no errors flagged for labels received that don't
match stored labels when in the label recognition mode.
Errorsareclearedby MRor byreading theStatus Register.
HARDWARE CONTROL OF THE RECEIVER
PIN 2 - WEF
PIN 5 - HFS and the CONTROL REGISTER
This pin, along with the control register, sets up the
functioning (e.g. modes) of the chip. If H FS is low, the
WEF is an error indicator. It goes high for a transmitter
"underwrite" (failure to keep up with byte loading) and pin 2
HOLT INTEGRATED CIRCUITS
4-4
HI-6010
PIN 14 - RXD0 and PIN 16 - RXD1
These pins must be 5 volt logic levels. There must be a
translator between the ARINC bus and these inputs.
Typically a receiver chip, such as the HI-8482 or HI-8588
is inserted between the ARINC bus and the logic chips.
RXD0 is looking for a high level for zero inputs and RXD1 is
looking for a high level for one inputs. When both inputs are
low this isreferred toas theNull state.
receiver is not programmable to the 32 bit "extended buffer"
mode nor to the label recognition mode. Affecting the
receiver:
CONTROL PROGRAM PIN 5
BIT NAME
VALUE VALUE
OPERATION
CR1
X
0
1
0
1
1
No action
No action
SOFTWARE CONTROL OF THE RECEIVER
Next 8 data read cycles will read
stored labels. One time only sequence
on each transiton of CR1 to a 1.
By writing to the Control Register and reading the Status
Register the controlling processor can operate the receiver
without hardware interrupts.
The Control Register in
CR2
CR3*
CR4
CR5
0
1
X
X
Receiver is disabled
Receiver is enabled
combination with the wiring of pin 5 was explained above.
The Status Register bits pertaining to the receiver are
explained below:
0
1
X
X
RXRDY goes high normally
Blocks RXRDY for one ARINC word
STATUS BIT VALUE
MEANING
0
1
X
X
Self test disabled
Self test enabled
SR1
SR3
SR4
SR5
0
1
No receiver data
Receiver data ready
0
0
No parity errors enabled and 32nd
bit is data
Parity error flag enabled
32 bit "extended mode" enabled and
parity enabled.
0
1
No parity error
Parity error - Parity was even
1
0
0
1
0
1
Receiver data not overwritten
Receiver data was overwritten
1
1
8 bit "one byte at a time" mode and
parity enabled.
0
1
Receiver data received without framing error
Framing error - Did not receive exactly 32
good bits
CR7
X
0
1
0
1
1
Label recognition not programmable
Label recognition disabled
Label recognition enabled
SR6
0
1
Did not receive first byte
Received first byte - Same flag as pin 13
* CR3 will be automatically reset to 0 after being programmed
to a 1 at the completion of an ARINC word reception. This
allows a software label recognition different from the automatic
optionavailable.
COMMUNICATING WITH THE CONTROL AND
STATUS REGISTERS
Pin 27, C/D , must be high to read the status register or write
the control register. Reading the status register resets
errors. Thereisno provision toread thecontrol register.
PIN 6 - MR
When MR is a 1, the control word is set to 0X10 0101 (CR7 -
CR0). For the receiver this sets up 8 bit mode with the
receiver and parity enabled. MR also initializes the registers
and logic. The first ARINC reception will only occur after a
wordgap.
LABELRECOGNITIONOPTION
Pin 5 must be high if label recognition is selected in either the
8 or 32 bit modes and all eight label buffers must be written
using redundantlabels, ifnecessary.
PIN 8 - RXRDY
The chip compares the incoming label to the stored labels. If
a match is found, the data is processed. If a match is not
found, noindicators ofreceivingARINCdata arepresented.
In 8 bit mode, this pin goes high whenever 8 bits are received
without error. In 32 bit mode this pin goes high after all 32 bits
are received with no error. This flag may be inhibited for one
ARINC word if CR3 is programmed to 1. This flag is also
inhibited in label recognition if the incoming ARINC label does
notmatch oneofthestored 8 labels.
LOADING LABELS
After thewritethat changes CR7from 0 to1, thenext 8 writes
of data (C/D is a zero for data) will load the label registers.
Labels must be loaded whenever pin 5 goes from low to
high.
PIN 12 - RXC
This pin must have a clock a pplied that is 4X the desired
receivefrequency.
READING LABELS
PIN 13 - FCR
After the write that changes CR1 from 0 to 1, the next 8 data
readsarelabels.
In 8 bit mode, this pin flags the first character (byte) received.
In 32 bit mode, this pin goes high for a valid 32 bit word. The
pinis notaffectedby CR3programming.
HOLT INTEGRATED CIRCUITS
4-5
HI-6010
PIN 6 - MR
The chip is initialized whenever this pin goes high. The
Control Register is set to 0X10 0101 (CR7 - CR0). For the
transmitter this sets up 8 bit mode with the transmitter
enabled.
The transmitter logic is independent of the receiver except in
the followingways:
1. Self Test
2. Parity Option
PIN 7 - TXE
In self test the transmitter outputs route to the receiver inputs
internallyand theTXD0andTXD1outputs areinhibited.
Whenever a transmission begins, this pin goes low and
returnshighafter thetransmission is complete.
When parity is enabled, both the receiver and transmitter are
affected. Odd parity is automatically generated in the 32nd
bitifthisoptionis selected.
PIN 9 - TXRDY
Whenever TXRDY is a one, data may be written into the
transmitter buffer. In 8 bit "one byte at a time" mode, this pin
may bemonitoredtoindicatewhen towritethenext 8 bits.
HARDWARE CONTROL OF THE TRANSMITTER
PIN 2 - WEF
PIN 10 - TXD0 and PIN 11 - TXD1
This output goes high for 1 transmitter error and 3 receiver
errors. To determine which error is being flagged, read the
Status Register. Reading the Status Register also clears the
error flag. The transmitte r will not function until the error is
cleared. Itcanalso becleared by MR going high.
TXD0 will go high during a transmission if the data is zero.
TXD1 goes high if data is a one. When both pins are low this
is referred to as the Null state . Typically an ARINC
transmitter chip, such as the HI-8382, HI-8383, HI-8585 or
HI-8586 is connected to these pins to translate the 5 volt
levelsto theproper ARINCbus levels.
Theonly possible transmitter error is generated whenrunning
in 8 bit mode. Forthe transmitter this means loadingthe last3
bytes while the transmission is in progress. Failure to load a
byte before the previous byte's 8th bit is transmitted will
generatetheerror, indicatedby status bitSR7 set to a 1.
SOFTWARE CONTROLOF THETRANSMITTER
By writing into the Control Register and reading the Status
Register, the controlling processor can operate the
transmitter independent of the flags at the pins.
Transmissioncan beinitiatedby changing CR0from a 0 toa1
after the transmitter buffer has been loaded. Then the Status
Register may bemonitoredas follows:
PIN 3 - CTS
This pin is a hardware gate for transmissions. If the
transmitter buffer is loaded and Control Register bit CR0 is a
one, the only inhibitof the transmitter would be for CTS to bea
one. When taken low, transmission of an ARINC word is
enabled. It may be pulsedtoreleaseeachtransmitted word.
STATUS BIT VALUE
MEANING
SR0
SR2
SR7
0
1
Do not load the transmitter buffer
Ready to load the transmitter buffer
PIN 4 - TXC
0
1
Transmission in progress
Transmitter is idle
The data rate of transmission is controlled by this pin. This
clock must be4X thedesireddaterate.
0
1
No transmission error
8 bit mode only error for underwriting data
PIN 5 - HFS and the CONTROL REGISTER
This pinalong with theControl Register sets thefunctioningof
the chip. For thetransmitter:
Cabling Noise -The HI-6010 has TTL compatible inputs and
therefore they are susceptible to noise near ground. If the data
bus is passed by ribbon cable or the equivalent to the device
under test, it is possible to get significant glitches on the Master
Reset line. The problem will appear to be a pattern sensitive
failure. One cure is simply to adequately bypass Master Reset.
AnotheristobuffertheHI-6010inputsnearthechip.
CONTROL PROGRAM
PIN 5
VALUE
BIT NAME
VALUE
OPERATION
CR0
0
1
X
X
Transmitter is disabled
Transmitter is enabled
CR4
CR5
0
1
X
X
Not in self test
Self test enabled
Receiver Seems Dead - After Master Reset the HI-6010
receivermustseeawordgapbeforethefirstARINCdatabit.
0
1
0
1
0
0
1
1
8 bit mode + data in 32nd bit
8 bit mode + parity enabled
32 bit mode with parity enabled
8 bit mode with parity enabled
Error flags must be cleared by either a Status Register Read or
by a Master Reset. The operati on of either the transmitter or the
receiverisinhibiteduponerror.
HOLT INTEGRATED CIRCUITS
4-6
HI-6010
8 BIT "ONE BYTE AT A TIME" TRANSMIT USING TXRDY, PIN 9, TO TRIGGER NEXT BYTE LOAD
REC/D CSWE D7
28 27 26 25 24
D6
23
D5
22
D4
21
D3
20
D2
19
D1
18
D0
17
6
0
0
0
0
0
5
0
0
0
0
0
0
0
0
0
3
X
0
0
0
0
0
0
0
0
7
1
0
0
0
0
0
0
0
1
8
X
X
X
X
X
X
X
X
X
9 13
COMMENTS
Load Control Word
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
P
P
1
0
0
0*
0
0
0
0
1
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
TD8 TD7 TD6 TD5 TD4 TD3 TD2 TD1
TXRDY & TXE Go Low After Load Data
Monitor Pin 9 to Go High
After Pin 9 High Then Load Next Byte
Monitor Pin 9 to Go High
Load
X
X
X
X
X
X
X
X
P TD16 TD15 TD14 TD13 TD12 TD11 TD10 TD9
1
X
X
X
X
X
X
X
X
P TD24 TD23 TD22 TD21 TD20 TD19 TD18 TD17 0
1
X
X
X
X
X
X
X
X
0
Monitor Pin 9 to Go High
Load
P TD32 TD31 TD30 TD29 TD28 TD27 TD26 TD25 0
1
X
X
X
X
X
X
X
X
0
Transmission Complete
8 BIT "ONE BYTE AT A TIME" TRANSMIT MONITORING STATUS REGISTER BIT 0
REC/D CSWE D7
28 27 26 25 24
D6
23
D5
22
D4
21
D3
20
D2
19
D1
18
D0
17
6
0
0
0
0
0
0
0
5
0
0
0
0
0
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
0
0
0
7
1
0
0
0
0
0
0
0
0
0
0
8
X
X
X
X
X
X
X
X
X
X
X
9 13
COMMENTS
Load Control Word D0 = 1
Load Data to Transmit - Byte 1
Status Bits 0, 2 & 7 ( TXRDY, TXE & ERROR)
Status Bit 0 Goes High
Load the Next Byte to Transmit
Monitor Status Bit 0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
1
0
0
0*
0
0
0
0
1
1
0
0
1
0
0
1
0
0
1
0
X
X
X
X
X
X
X
X
X
X
X
TD8 TD7 TD6 TD5 TD4 TD3 TD2 TD1
P
P
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
P TD16 TD15 TD14 TD13 TD12 TD11 TD10 TD9
P
P
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Detect a Transition
P TD24 TD23 TD22 TD21 TD20 TD19 TD18 TD17 0
Load 3rd Byte
P
P
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Monitor Status Bit 0
Detect a Transition
P TD32 TD31 TD30 TD29 TD28 TD27 TD26 TD25 0
Load 4th Byte
HOLT INTEGRATED CIRCUITS
4-7
HI-6010
RECEIVING 32 BIT WORDS HARDWARE INTERRUPT
REC/D CSWE D7
28 27 26 25 24
D6
23
D5
22
D4
21
D3
20
D2
19
D1
18
D0
17
6
0
0
0
0
5
1
1
1
1
1
1
1
3
X
X
X
X
X
X
X
7
X
X
X
X
X
X
X
8
0
1
1
1
1
1
0
9 13
COMMENTS
Write CR: 32 Bit Recieve & No Label Recogn.
Await Pin 8 or Pin 13 to Go High
Read 1st Byte
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
P
1
1
0
0
0
0
0
1
0
0
X
X
X
X
X
X
X
0
1
1
1
1
1
0
X
X
X
X
X
X
X
X
P
P
P
P
1
RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1
1 RD16 RD15 RD14 RD13 RD12 RD11 RD10 RD9
Read 2nd Byte
1 RD24 RD23 RD22 RD21 RD20 RD19 RD18 RD17 0
Read 3rd Byte
1
1
PAR RD31 RD30 RD29 RD28 RD27 RD26 RD25 0
Read 4th Byte
X
X
X
X
X
X
X
X
0
RECEIVING 8 BIT MODE SOFTWARE INTERRUPT
REC/D CSWE D7
28 27 26 25 24
D6
23
D5
22
D4
21
D3
20
D2
19
D1
18
D0
17
6
0
0
0
0
0
0
0
0
0
5
1
1
1
1
1
1
1
1
1
1
1
1
1
3
X
X
X
X
X
X
X
X
X
X
X
X
X
7
X
X
X
X
X
X
X
X
X
X
X
X
X
8
0
0
1
0
0
1
0
0
1
0
0
1
0
9 13
COMMENTS
1
P
P
P
P
P
P
P
P
P
P
P
P
1
1
1
0
1
1
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
1
1
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
X
X
0
0
1
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
0
0
0
0
0
0
0
0
0
0
Write CR: 8 Bit Receive & Not Label Recong.
Monitor the Status Register
SR 1 & SR 6 Go High - First Character
Read 1st Byte
RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1
0
0
0
0
0
0
0
0
0
0
X
X
0
1
0
0
Look for SR 1 to Go High Again
1 RD16 RD15 RD14 RD13 RD12 RD11 RD10 RD9
Read 2nd Byte
1
1
0
0
0
0
0
0
0
0
0
0
X
X
0
1
0
0
Look for SR 1 to Go High Again
1 RD24 RD23 RD22 RD21 RD20 RD19 RD18 RD17 0
Read 3rd Byte
1
1
1
0
0
0
0
0
0
0
0
0
0
X
X
0
1
0
0
0
0
Look for SR 1 to Go High Again
PAR RD31 RD30 RD29 RD28 RD27 RD26 RD25 0
Read 4th Byte
HOLT INTEGRATED CIRCUITS
4-8
HI-6010
TRANSMIT IN 32 BIT MODE (EXTENDED BUFFER) USING CTS TO INITIATE
REC/D CSWE D7
28 27 26 25 24
D6
23
D5
22
D4
21
D3
20
D2
19
D1
18
D0
17
6
0
0
0
5
1
1
1
1
1
1
3
1
1
1
1
1
0
7
1
1
1
1
1
1
8
X
X
X
X
X
X
9 13
COMMENTS
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
1
P
P
0
0
0
0
0
0
0
1
1
0
0
0
1
1
X
X
X
X
X
X
Load Control Word D5 = 0 & D0 = 1
Load Data to Transmit - Byte 1
Load Data to Transmit - Byte 2
Load Data to Transmit - Byte 3
Load Data to Transmit - Byte 4
TD8 TD7 TD6 TD5 TD4 TD3 TD2 TD1
P TD16 TD15 TD14 TD13 TD12 TD11 TD10 TD9
P TD24 TD23 TD22 TD21 TD20 TD19 TD18 TD17 0
P
1
X
X
TD31 TD30 TD29 TD28 TD27 TD26 TD25 0
X
X
X
X
X
X
X
0
Take CTS Low to Start Transmitting
32nd Bit Will Be Parity
TRANSMIT IN 32 BIT MODE (EXTENDED BUFFER)
USING SOFTWARE WRITE TO CONTROL REGISTER
REC/D CSWE D7
28 27 26 25 24
D6
23
D5
22
D4
21
D3
20
D2
19
D1
18
D0
17
6
0
0
0
5
1
1
1
1
1
1
3
0
0
0
0
0
0
7
1
1
1
1
1
0
8
X
X
X
X
X
X
9 13
COMMENTS
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
P
P
0
0
0
0
0
0
0
0
1
0
0
0
1
1
X
X
X
X
X
X
Load Control Word D5 = 0 & D0 = 0
Load Data to Transmit - Byte 1
Load Data to Transmit - Byte 2
Load Data to Transmit - Byte 3
Load Data to Transmit - Byte 4
TD8 TD7 TD6 TD5 TD4 TD3 TD2 TD1
P TD16 TD15 TD14 TD13 TD12 TD11 TD10 TD9
P TD24 TD23 TD22 TD21 TD20 TD19 TD18 TD17 0
P
P
X
0
TD31 TD30 TD29 TD28 TD27 TD26 TD25 0
0
0
0
0
0
0
1
0
Write Control Word D0 = 1
32nd Bit Will Be Parity
HOLT INTEGRATED CIRCUITS
4-9
HI-6010
LOADING LABELS
REC/D CSWE D7
28 27 26 25 24
D6
23
D5
22
D4
21
D3
20
D2
19
D1
18
D0
17
6
0
0
0
0
0
0
0
0
0
0
5
1
1
1
1
1
1
1
1
1
1
3
X
X
X
X
X
X
X
X
X
X
7
X
X
X
X
X
X
X
X
X
X
8
X
X
X
X
X
X
X
X
X
X
9 13
COMMENTS
Control Bit 7 Must Be 0 First
Write 1 into Control Bit 7
Load the 1st Label
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
P
P
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1L7 1L6 1L5 1L4 1L3 1L2 1L1 1L0
2L7 2L6 2L5 2L4 2L3 2L2 2L1 2L0
3L7 3L6 3L5 3L4 3L3 3L2 3L1 3L0
4L7 4L6 4L5 4L4 4L3 4L2 4L1 4L0
5L7 5L6 5L5 5L4 5L3 5L2 5L1 5L0
6L7 6L6 6L5 6L4 6L3 6L2 6L1 6L0
7L7 7L6 7L5 7L4 7L3 7L2 7L1 7L0
8L7 8L6 8L5 8L4 8L3 8L2 8L1 8L0
Load the 2nd Label
Load the 3rd Label
Load the 4th Label
Load the 5th Label
Load the 6th Label
Load the 7th Label
Load the 8th Label
READING LABELS
REC/D CSWE D7
28 27 26 25 24
D6
23
D5
22
D4
21
D3
20
D2
19
D1
18
D0
17
6
0
0
0
0
0
0
0
0
0
0
5
1
1
1
1
1
1
1
1
1
1
3
X
X
X
X
X
X
X
X
X
X
7
X
X
X
X
X
X
X
X
X
X
8
X
X
X
X
X
X
X
X
X
X
9 13
COMMENTS
Make Sure Bit 1 of Control Word is 0
Write 1 into Control Bit 1
Read the 1st Label
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
P
P
P
P
P
P
P
P
1L7 1L6 1L5 1L4 1L3 1L2 1L1 1L0
2L7 2L6 2L5 2L4 2L3 2L2 2L1 2L0
3L7 3L6 3L5 3L4 3L3 3L2 3L1 3L0
4L7 4L6 4L5 4L4 4L3 4L2 4L1 4L0
5L7 5L6 5L5 5L4 5L3 5L2 5L1 5L0
6L7 6L6 6L5 6L4 6L3 6L2 6L1 6L0
7L7 7L6 7L5 7L4 7L3 7L2 7L1 7L0
8L7 8L6 8L5 8L4 8L3 8L2 8L1 8L0
Read the 2nd Label
Read the 3rd Label
Read the 4th Label
Read the 5th Label
Read the 6th Label
Read the 7th Label
Read the 8th Label
HOLT INTEGRATED CIRCUITS
4-10
HI-6010
TIMING DIAGRAMS
DATA BUS TIMING - READ
DATA BUS TIMING - WRITE
VALID
VALID
C/D
RD
C/D
WE
tCDH
tCDH
tCDS
tCDS
tWP
tDWS
tRD
tDR
tDWH
DATA
BUS
DATA
BUS
VALID
VALID
tCSSR
tCSSW
tCSHR
tCSHW
CS
CS
Figure 1.
Figure 2.
TRANSMTTER OPERATION
RECEIVER OPERATION
CTS
TXE
tCTL
tCPW
tENDAT
tDTX
tTXRY
TXD0/
TXD1
RXD0/
RXD1
FIRST
BIT
LAST
BIT
LAST
BIT
tDR
RXRDY/
FCR
TXRDY
Figure 3.
Figure 4.
HOLT INTEGRATED CIRCUITS
4-11
HI-6010
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to VSS = 0V)
Supply Voltage:
Input Voltage Range
Input Current
VDD
VIN
IIN
-0.5V to +7.0V
-0.5V to VDD +0.5V
+10mA
Power Dissipation
PD
500mW
Operating Temperature Range: TA (Industrial)
-40°C to +85°C
TA (Hi temp & Military) -55°C to +125°C
Storage Temperature Range:
Lead Temperature
TSTG
-65°C to +150°C
Output Current
IOUT
+25mA
TLEAD
300°C for 60 Seconds
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These a re stress ratings
only. Functional operation of the device at these or any other conditions above those indicated in the operational se ctions of the specifications is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
VDD = 5.0V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
SYMBOL
CONDITION
MIN
4.5
TYP
5
MAX
UNITS
Operating Voltage
Min. Input Voltage
Max. Input Voltage
Min. Input Current
Max. Input Current
Min. Output Voltage
VDD
VIH
VIL
IIH
5.5
V
V
(HI)
(LO)
(HI)
2.1
1.4
1.4
0.7
1.5
V
VIH = 4.9V
VIL = 0.1V
-1.5
2.7
µA
µA
V
(LO)
(HI)
IIL
VOH
VIH
IDD
CIN
IOUT = -1.5mA
IOUT = 1.8mA
f = 400KHz
Not tested
Max. Output Voltage (LO)
Operating Current Drain
Input Capacitance
0.7
2.8
20
V
0.8
mA
pF
AC ELECTRICAL CHARACTERISTICS
VDD = 5.0V, VSS = 0V, TA =Operating Temperature Range (unless otherwise specified).
PARAMETER SYMBOL
MIN
TYP
MAX
UNITS
DATA BUS TIMING - READ
(See Figure 1.)
Setup C/D to RD
tCDS
tCDH
tRC
50
0
ns
ns
ns
ns
ns
ns
Hold C/D to RD
Delay RD to Data
200
150
Delay Data Bus Hi-Z from RD
Setup CS to RD
tRD
tCSSR
tCSHR
0
0
Hold RD to CS
DATA BUS TIMING - WRITE
Set C/D to WE
(See Figure 2.)
tCDS
tCDH
0
0
ns
ns
ns
ns
ns
ns
ns
Hold C/D to WE
Setup Data Bus to WE
Hold Data Bus to WE
Setup CS to WE
tWDS
tDWH
tCSSW
tCSHW
tWP
200
100
0
Hold CS to WE
0
Pulse Width WE
200
TRANSMITTER TIMING
Delay TXE from CTS
Delay TXRDn from CTS
Delay TXRDY from last TXDn
Delay TXE from last TXDn
CTS pulse width
(See Figure 3.)
tCTL
tENDAT
tTXRDY
tTDTX
1.5
1
2.0
CLKS
CLK
16
CLKS
4
DATA BITS
CLK
tCPW
1
RECEIVER TIMING
Delay Last RXDn to RXRDY
(See Figure 4.)
tDR
3
CLKS
HOLT INTEGRATED CIRCUITS
4-12
HI-6010
ORDERING INFORMATION
PART
NUMBER
PACKAGE
DESCRIPTION
TEMPERATURE
RANGE
BURN
IN
LEAD
FINISH
FLOW
HI-6010C
28 PIN CERAMIC SIDE BRAZED DIP
28 PIN CERAMIC SIDE BRAZED DIP
-40°C TO +85°C
-55°C TO +125°C
-55°C TO +125°C
-40°C TO +85°C
-55°C TO +125°C
I
T
M
I
NO
NO
YES
NO
NO
GOLD
GOLD
HI-6010CT
HI-6010CM-01 28 PIN CERAMIC SIDE BRAZED DIP
SOLDER
SOLDER
SOLDER
HI-6010J
28 PIN PLASTIC J -LEAD PLCC
28 PIN PLASTIC J -LEAD PLCC
HI-6010JT
T
HOLT INTEGRATED CIRCUITS
4-13
HI-6010 PACKAGE DIMENSIONS
inches (millimeters)
28-PIN CERAMIC SIDE-BRAZED DIP
Package Type: 28C
1.400 ± .014
(35.560 ± .356)
.610 ± .010
.595 ± .010
(15.494 ± .254)
(15.113 ± .254)
.050 TYP.
(1.270 TYP.)
.600 ± .010
.085 ± .009
(2.159 ± .229)
.200 MAX.
(5.080 MAX.)
(15.240 ± .254)
.125 MIN.
(3.175 MIN.)
010 + .002/- .001
(.254 +.051/- .025)
.018 ± .002
(.457 ± .051)
.100 ± .005
(2.540 ± .127)
28-PIN PLASTIC PLCC
Package Type: 28J
PIN NO. 1 IDENT
PIN NO. 1
.045 x 45°
.045 x 45°
.050 ± .005
(1.27 ± .127)
.453 ± .003
(11.506 ± .076)
.490 ± .005
(12.446 ± .127)
.031 ± .005
(.787 ± .127)
SQ.
SQ.
.017 ± .004
(.432 ± .102)
SEE DETAIL
A
.009
.011
.015 ± .002
(.381 ± .051)
.173 ± .008
(4.394 ± .203)
.020 MIN
(.508 MIN )
.025
.045
DETAIL A
R
.410 ± .020
(10.414 ± .508)
HOLT INTEGRATED CIRCUITS
1
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