HI-5701883 [INTERSIL]
6-Bit, 30 MSPS Flash A/D Converter; 6位， 30 MSPS的Flash A / D转换器
| 型号： | HI-5701883 |
| 厂家： | 
Intersil |
| 描述： | 6-Bit, 30 MSPS Flash A/D Converter |
| 文件： | 总8页 (文件大小：63K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-5701/883
6-Bit, 30 MSPS Flash A/D Converter
June 1994
Features
Description
• This Circuit is Processed in Accordance to MIL-STD- The HI-5701/883 is a monolithic, 6-bit, CMOS Flash Analog-
883 and is Fully Conformant Under the Provisions of to-Digital Converter. It is designed for high speed
Paragraph 1.2.1.
applications where wide bandwidth and low power
consumption are essential. Its 30 MSPS speed is made
possible by a parallel architecture which also eliminates the
need for an external sample and hold circuit. The HI-5701/
883 delivers ±0.7 LSB differential nonlinearity while
consuming only 250mW (typical) at 30 MSPS. Microproces-
sor compatible data output latches are provided which
present valid data to the output bus 1.5 clock cycles after the
convert command is received. An overflow bit is provided to
allow the series connection of two converters to achieve 7-bit
resolution.
• 30 MSPS with No Missing Codes
• 20MHz Full Power Input Bandwidth
• No Missing Codes Over Temperature
• Sample and Hold Not Required
• Single +5V Supply Voltage
• CMOS/TTL
• Overflow Bit
Ordering Information
Applications
TEMPERATURE
• Video Digitizing
PART NUMBER
RANGE
PACKAGE
• Radar Systems
o
o
HI1-5701T/883
-55 C to +125 C
18 Lead CerDIP
• Medical Imaging
• Communication Systems
• High Speed Data Acquisition Systems
Functional Block Diagram
Pinout
2
1
1
2
1
HI-5701/883
(18 LEAD CERDIP)
TOP VIEW
VIN 11
OVERFLOW
(OVF)
D
CL
R/2
Q
2
9
VREF
+
COMP
64
D
CL
1
2
3
4
5
6
7
8
9
18
17
D5 (MSB)
OVF
D4
D3
Q
R
1
3
D5 (MSB)
D4
D
CL
Q
VSS
16 1/2R
15 D2
R
COMP
63
NC
D
CL
R
R
Q
4
5
D3
16
1/2R
CE2
14 D1
D
CL
CE1
13 D0 (LSB)
COMP
32
Q
D2
R
R
CLK
12
11
10
VDD
VIN
D
CL
10
D1
Q
PHASE
COMP
2
VREF
+
VREF
-
D
CL
D0 (LSB)
Q
11
10
-
VREF
R/2
COMP
1
CE1
CE2
16
15
VDD
VSS
12
3
7
8
CLK
2 (SAMPLE)
1 (AUTO BALANCE)
PHASE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Spec Number 512031
File Number 3378
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
6-1
HI-5701/883
Pin Description
PIN #
NAME
DESCRIPTION
1
2
3
4
5
6
7
8
D5
Bit 6, Output (MSB)
Overflow, Output
Digital Ground
OVF
V
SS
NC
CE2
No Connection
Three-State Output Enable Input, Active high (See Truth Table)
Three-State Output Enable Input, Active Low (See Truth Table)
Clock Input
CE1
CLK
PHASE
Sample Clock Phase Control Input. When Phase is Low, Sample Unknown (φ1) occurs when the Clock
is Low and Auto Balance (φ2) occurs when the Clock is High (See Phase Control Table)
9
V
+
Reference Voltage Positive Input
Reference Voltage Negative Input
Analog Signal Input
Power Supply, +5V
Bit 1, Output (LSB)
Bit 2, Output
REF
10
11
12
13
14
15
16
17
18
V
-
REF
V
IN
V
DD
D0
D1
D2
Bit 3, Output
1/2R
D3
Reference Ladder Midpoint
Bit 4, Output
D4
Bit 5, Output
Chip Enable Truth Table
Phase Control
CE1
CE2
D0 - D5
Valid
OVF
CLOCK
PHASE
INTERNAL GENERATION
Sample Unknown (φ2)
Auto Balance (φ1)
0
1
1
0
Valid
Valid
0
0
1
1
0
1
0
1
1
Three-State
Three-State
X
Three-State
Auto Balance (φ1)
X = Don’t Care.
Sample Unknown (φ2)
Spec Number 512031
6-2
Specifications HI-5701/883
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V to V . . . . . . . . . . . (VSS - 0.5) < V < +7.0V Thermal Resistance
θ
θ
JC
28 C/W
DD
SS
DD
JA
0
o
Analog and Reference Input Pins. .(VSS - 0.5) < V
< (V +0.5V)
HI1-5701T/883. . . . . . . . . . . . . . . . . . . . .
70 C/W
INA
DD
o
Digital I/O Pins . . . . . . . . . . . . . . . . (VSS - 0.5) < V < (V +0.5V) Power Dissipation at +75 C (Note 1)
I/O
DD
Operating Temperature Range
HI1-5701T/883 . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
Storage Temperature Range . . . . . . . . . . . . . . . -65 C to +150 C Reliability Information
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . 300 C
ESD Clasification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Worst Case Density . . . . . . . . . . . . . . . . . . . . . . . . 3.05 x 10 A/cm
HI1-5701T/883. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4mW
o
o
o
Power Dissipation Derating Factor Above +75 C
HI1-5701T/883. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14mW/ C
o
o
o
o
o
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4815
4
2
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: V = +5.0V; V
+ = +4.0V; V
- = V = GND; F = Specified Clock Frequency at 50% Duty Cycle; C = 30pF;
DD
REF
REF SS S L
Unless Otherwise Specified.
LIMITS
GROUP A
PARAMETERS
SYMBOL
CONDITIONS
SUBGROUP
TEMPERATURE
MIN
MAX
UNIT
ACCURACY
o
Integral Linearity Error
(Best Fit Method)
INL
F
F
F
F
F
F
= 20MHz, f = DC
1
2, 3
1
+25 C
-
-
-
-
-
-
-
-
-
-
-
-
±1.25
±2.0
±1.5
±2.5
±0.6
±0.75
±0.75
±1.0
±2.0
±2.5
±2.0
±2.5
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
S
S
S
S
S
S
IN
o
o
+125 C, -55 C
o
= 30MHz, f = DC
+25 C
IN
o
o
2, 3
1
+125 C, -55 C
o
Differential Linearity Error
(Guaranteed No Missing
Codes)
DNL
= 20MHz, f = DC
+25 C
IN
o
o
2, 3
1
+125 C, -55 C
o
= 30MHz, f = DC
+25 C
IN
o
o
2, 3
1
+125 C, -55 C
o
Offset Error
(Adjustable to Zero)
VOS
FSE
= 20MHz, f = DC
+25 C
IN
o
o
2, 3
1
+125 C, -55 C
o
Full Scale Error
(Adjustable to Zero)
= 20MHz, f = DC
+25 C
IN
o
o
2, 3
+125 C, -55 C
ANALOG INPUT
o
Analog Input Resistance
R
V
V
= 4V
1
+25 C
4
4
-
MΩ
MΩ
µA
IN
IN
IN
o
o
2, 3
1
+125 C, -55 C
-
o
Analog Input Bias Current
I
= 0V, 4V
+25 C
±1.0
±1.0
B
o
o
2, 3
+125 C, -55 C
µA
REFERENCE INPUT
o
Total Reference Resistance
R
1
+25 C
250
235
-
-
Ω
Ω
L
o
o
2, 3
+125 C, -55 C
Spec Number 512031
6-3
Specifications HI-5701/883
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Tested at: V = +5.0V; V
+ = +4.0V; V
- = V = GND; F = Specified Clock Frequency at 50% Duty Cycle; C = 30pF;
DD
REF
REF SS S L
Unless Otherwise Specified.
LIMITS
GROUP A
PARAMETERS
SYMBOL
CONDITIONS
SUBGROUP
TEMPERATURE
MIN
MAX
UNIT
DIGITAL INPUTS
Input High Voltage
o
V
1
2, 3
1
+25 C
2.0
-
V
V
IH
o
o
+125 C, -55 C
2.0
-
o
Input Low Voltage
Logic Input Current
V
I
+25 C
-
-
-
-
0.8
0.8
±1
±1
V
IL
o
o
2, 3
1
+125 C, -55 C
V
o
V
= 0V, +5V
IN
+25 C
µA
µA
IN
o
o
2, 3
+125 C, -55 C
DIGITAL OUTPUTS
Output Leakage
o
I
CE2 = 0V, V = 0V, 5V
1
2, 3
1
+25 C
-
±1.0
µA
µA
OZ
O
o
o
+125 C, -55 C
-
±1.0
o
Output Logic Source Current
Output Logic Sink Current
I
V
V
= 4.5V
= 0.4V
+25 C
-3.2
-3.2
3.2
3.2
-
-
-
-
mA
mA
mA
mA
OH
O
O
o
o
2, 3
1
+125 C, -55 C
o
I
+25 C
OL
o
o
2, 3
+125 C, -55 C
POWER SUPPLY REJECTION
Offset Error PSRR
o
∆VOS
∆FSE
V
V
= 5V ±10%
= 5V ±10%
1
+25 C
-
-
-
-
±1.0
±1.5
±1.0
±1.5
LSB
LSB
LSB
LSB
DD
DD
o
o
2, 3
1
+125 C, -55 C
o
Gain Error PSRR
+25 C
o
o
2, 3
+125 C, -55 C
POWER SUPPLY CURRENT
Supply Current
o
I
F
= 30MHz
S
1
+25 C
-
-
60
75
mA
mA
DD
o
o
2, 3
+125 C, -55 C
NOTE:
1. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
Spec Number 512031
6-4
Specifications HI-5701/883
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: V = +5.0V; V
+ = +4.0V; V
- = V = GND; F = Specified Clock Frequency at 50% Duty Cycle; C = 30pF;
DD
REF
REF SS S L
Unless Otherwise Specified.
LIMITS
GROUP A
PARAMETER
SYMBOL
CONDITIONS
SUBGROUP
TEMPERATURE
MIN
MAX
-
UNIT
MSPS
MSPS
ns
o
Maximum Conversion Rate
Data Output Enable Time
Data Output Disable Time
Data Output Delay
No Missing Codes
9
10, 11
9
+25 C
30
30
-
o
o
+125 C, -55 C
-
o
t
+25 C
20
20
20
20
20
20
-
EN
o
o
10, 11
9
+125 C, -55 C
-
ns
o
t
+25 C
-
ns
DIS
o
o
10, 11
9
+125 C, -55 C
-
ns
o
t
+25 C
-
ns
OD
o
o
10, 11
9
+125 C, -55 C
-
ns
o
Data Output Hold
t
+25 C
10
5
ns
H
o
o
10, 11
+125 C, -55 C
-
ns
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (NOTE 1)
Device Characterized at: V = +5.0V; V + = +4.0V; V - = V = GND; F = Specified Clock Frequency at 50% Duty Cycle; C = 30pF;
DD
REF
REF
SS
S
L
Unless Otherwise Specified.
LIMITS
PARAMETER
SYMBOL
CONDITIONS
No Missing Codes
TEMPERATURE
MIN
MAX
UNIT
MSPS
o
o
o
Minimum Conversion Rate
NOTE:
+25 C, +125 C, -55 C
-
0.125
1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These param-
eters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization
based upon data from multiple production runs which reflect lot to lot and within lot variation.
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS
Interim Electrical Parameters (Pre Burn-In)
Final Electrical Test Parameters
Group A Test Requirements
Groups C and D Endpoints
SUBGROUPS (SEE TABLES 1 AND 2)
1
1 (Note 1), 2, 3, 9, 10, 11
1, 2, 3, 9, 10, 11
1
NOTE:
1. PDA applies to Subgroup 1 only. No other subgroups are included in PDA.
Spec Number 512031
6-5
HI-5701/883
Die Characteristics
DIE DIMENSIONS:
2220µm x 3320µm x 19 ± 1mils
METALLIZATION:
Type: Si - Al
Thickness: 11kÅ ± 1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ± 1kÅ
DIE ATTACH:
Material: Gold Silicon Eutectic Alloy
Temperature: Ceramic DIP - 460oC (Max)
WORST CASE CURRENT DENSITY:
3.05 x 104 A/cm2
Metallization Mask Layout
HI-5701/883
VSS
1/2R
D2
CE2
D1
D0
VDD
CE1
Spec Number 512031
6-6
HI-5701/883
Timing Waveforms
COMPARATOR DATA
IS LATCHED
ENCODED DATA IS
LATCHED INTO THE
OUTPUT REGISTERS
CLOCK
INPUT
1
1
1
1
2
2
2
2
2
PHASE - HIGH
CLOCK
INPUT
PHASE - LOW
SAMPLE
N-2
SAMPLE
N-1
SAMPLE
SAMPLE
N+1
SAMPLE
N+2
N
AUTO
BALANCE
tAB
AUTO
BALANCE
AUTO
BALANCE
AUTO
BALANCE
ANALOG
INPUT
tAP
tH
tAJ
tOD
DATA
OUTPUT
DATA N-4
DATA N-3
DATA N-2
DATA N-1
DATA N
FIGURE 1. INPUT-TO-OUTPUT TIMING
CE1
CE2
tEN
tDIS
tEN
tDIS
HIGH
HIGH
D0 - D5
DATA
DATA
DATA
DATA
IMPEDANCE
IMPEDANCE
HIGH
OVF
DATA
IMPEDANCE
FIGURE 2. OUTPUT ENABLE TIMING
HI-5701/883 CerDIP
Burn-In Circuit
+5V
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
C1
0.01µF/0.1µF
CAP
0V
CLK
+4V
VIN
C7
CAP
0.01µF/0.1µF
0V
NOTES:
1. Power supply and the reference voltage input to be decoupled by 0.01µF in parallel with 1µF capacitor
2. Clock input is a pulse with 1:10 duty cycle, approximately 100KHz and 0V to 4V amplitude
3. V , analog input is a slow triangular waveform (F = 10KHz) and 0V to 4V amplitude
IN
IN
4. All supplies to be protected with <7V zener diodes
Spec Number 512031
6-7
HI-5701/883
Packaging
F18.3 MIL-STD-1835 GDIP1-T18 (D-6, CONFIGURATION A)
18 LEAD FRIT SEAL DUAL-IN-LINE CERAMIC PACKAGE
FRIT SEAL DUAL-IN-LINE CERAMIC PACKAGE
c1
LEAD FINISH
INCHES MILLIMETERS
MIN
-A-
-D-
E
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.960
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
24.38
7.87
NOTES
BASE
(c)
METAL
A
b
-
-
2
3
-
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
b1
b1
b2
b3
c
M
M
-B-
(b)
SECTION A-A
4
2
3
5
5
-
S
S
S
D
bbb
C
A - B
D
c1
D
BASE
PLANE
Q
A
-C-
SEATING
PLANE
E
0.220
5.59
L
α
e
0.100 BSC
2.54 BSC
S1
b2
eA
A
A
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
-
e
eA/2
b
c
0.125
0.200
3.18
5.08
-
M
S
S
M
S
S
D
ccc
C
A - B
D
aaa
C
A - B
Q
0.015
0.005
0.005
0.070
0.38
0.13
0.13
1.78
6
7
S1
S2
α
-
-
-
-
o
o
o
o
90
105
90
105
-
-
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
NOTES:
-
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area
shown. The manufacturer’s identification shall not be used as a pin
one identification mark.
2
8
N
18
18
5. This dimension allows for off-center lid, meniscus, and glass overrun.
2. The maximum limits of lead dimensions b and c or M shall be mea-
sured at the centroid of the finished lead surfaces, when solder dip
or tin plate lead finish is applied.
6. Dimension Q shall be measured from the seating plane to the base
plane.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension M
applies to lead plating and finish thickness.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling Dimension: Inch.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial
lead paddle. For this configuration dimension b3 replaces dimension
b1.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number 512031
6-8
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