HI-574A_08 [INTERSIL]
Complete, 12-Bit A/D Converters with Converters with Microprocessor Interface; 完整的12位与微处理器接口转换器A / D转换器
| 型号： | HI-574A_08 |
| 厂家： | 
Intersil |
| 描述： | Complete, 12-Bit A/D Converters with Converters with Microprocessor Interface |
| 文件： | 总18页 (文件大小：386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-574A, HI-674A
®
Data Sheet
August 7, 2008
FN3096.6
Complete, 12-Bit A/D Converters with
Microprocessor Interface
Features
• Complete 12-Bit A/D Converter with Reference and Clock
• Full 8-Bit, 12-Bit or 16-Bit Microprocessor Bus Interface
• Bus Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 150ns
• No Missing Codes Over Temperature
The HI-X74(A) is a complete 12-bit, Analog-to-Digital
Converter, including a +10V reference clock, three-state
outputs and a digital interface for microprocessor control.
Successive approximation conversion is performed by two
monolithic dice housed in a 28 lead package. The bipolar
analog die features the Intersil Dielectric Isolation process,
which provides enhanced AC performance and freedom
from latch-up.
• Minimal Setup Time for Control Signals
• Fast Conversion Times
- HI-574A (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25µs
- HI-674A (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15µs
Custom design of each IC (bipolar analog and CMOS digital)
has yielded improved performance over existing versions of
this converter. The voltage comparator features high PSRR
plus a high speed current-mode latch, and provides precise
decisions down to 0.1 LSB of input overdrive. More than 2X
reduction in noise has been achieved by using current
instead of voltage for transmission of all signals between the
analog and digital ICs. Also, the clock oscillator is current
controlled for excellent stability over temperature.
• Low Noise, via Current-Mode Signal Transmission
Between Chips
• Byte Enable/Short Cycle (A Input)
O
- Guaranteed Break-Before-Make Action, Eliminating Bus
Contention During Read Operation. Latched by Start
Convert Input (To Set the Conversion Length)
• Supply Voltage . . . . . . . . . . . . . . . . . . . . . . ±12V to ±15V
• Pb-Free Available (RoHS Compliant)
The HI-X74(A) offers standard unipolar and bipolar input
ranges, laser trimmed for specified linearity, gain and offset
accuracy. The low noise buried zener reference circuit is
trimmed for minimum temperature coefficient.
Applications
• Military and Industrial Data Acquisition Systems
• Electronic Test and Scientific Instrumentation
• Process Control Systems
Power requirements are +5V and ±12V to ±15V, with typical
dissipation of 385mW (HI-574A, HI-674A) at 12V.
Pinout
HI-574A, HI-674A
(28 LD PDIP, SBDIP)
TOP VIEW
+5V SUPPLY, V
LOGIC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
STATUS, STS
DB11 MSB
DB10
2
3
DATA MODE SEL, 12/8
CHIP SEL, CS
BYTE ADDR/SHORT
4
DB9
CYCLE, A
O
5
DB8
READ/CONVERT, R/C
CHIP ENABLE, CE
6
DB7
DIGITAL
+12V/+15V SUPPLY, V
CC
7
DATA
DB6
DB5
DB4
DB3
DB2
DB1
DB0
OUTPUTS
+10V REF, REF OUT
8
ANALOG
COMMON, AC
9
10
11
12
REFERENCE INPUT
-12V/-15V SUPPLY, V
EE
BIPOLAR OFFSET
BIP OFF
10V INPUT 13
LSB
DIG COMMON,
DC
14
20V INPUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2001, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI-574A, HI-674A
Ordering Information
TEMPERATURE RANGE
PKG.
PART NUMBER
PART MARKING
HI3-574AJN-5
HI3-574AJN-5Z (Notes 1, 3) HI3-574AJN-5Z
HI3-574AKN-5 HI3-574AKN-5
HI3-574AKN-5Z (Notes 1, 3) HI3-574AKN-5Z
INL
(°C)
PACKAGE
28 Ld PDIP
DWG. #
HI3-574AJN-5
±1.0 LSB
±1.0 LSB
±0.5 LSB
±0.5 LSB
±1.0 LSB
±0.5 LSB
±1.0 LSB
±0.5 LSB
±1.0 LSB
±1.0 LSB
±0.5 LSB
±0.5 LSB
±0.5 LSB
±0.5 LSB
0 to +75
0 to +75
0 to +75
0 to +75
0 to +75
0 to +75
-55 to +125
-55 to +125
0 to +75
0 to +75
0 to +75
0 to +75
0 to +75
-55 to +125
E28.6
28 Ld PDIP (Pb-Free)
28 Ld PDIP
E28.6
E28.6
E28.6
D28.6
D28.6
D28.6
D28.6
E28.6
E28.6
E28.6
E28.6
D28.6
D28.6
28 Ld PDIP (Pb-Free)
28 Ld SBDIP (Pb-Free)
28 Ld SBDIP (Pb-Free)
28 Ld SBDIP (Pb-Free)
28 Ld SBDIP (Pb-Free)
28 Ld PDIP
HI1-574AJD-5 (Note 2)
HI1-574AKD-5 (Note 2)
HI1-574ASD-2 (Note 2)
HI1-574ATD-2 (Note 2)
HI3-674AJN-5
HI1-574AJD -5
HI1-574AKD -5
HI1-574ASD -2
HI1- 574ATD-2
HI3-674AJN-5
HI3-674AJN-5Z (Notes 1, 3) HI3-674AJN-5Z
HI3-674AKN-5 HI3-674AKN-5
HI3-674AKN-5Z (Notes 1, 3) HI3-674AKN-5Z
28 Ld PDIP (Pb-Free)
28 Ld PDIP
28 Ld PDIP (Pb-Free)
28 Ld SBDIP (Pb-Free)
28 Ld SBDIP (Pb-Free)
HI1-674AKD-5 (Note 2)
HI1-674ATD/883 (Note 2)
NOTES:
HI1-674AKD -5
HI1-674ATD /883
1. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
2. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with
both SnPb and Pb-free soldering operations.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
FN3096.6
August 7, 2008
2
HI-574A, HI-674A
Functional Block Diagram
BIT OUTPUTS
MSB
LSB
12/8
NIBBLE A (NOTE)
NIBBLE B (NOTE)
NIBBLE C (NOTE)
CS
CONTROL
LOGIC
THREE-STATE BUFFERS AND CONTROL
A
O
R/C
CE
V
LOGIC
POWER-UP RESET
DIGITAL
COMMON
12 BITS
SAR
STS
CLK
OSCILLATOR
STROBE
DIGITAL CHIP
ANALOG CHIP
12 BITS
V
V
CC
EE
COMP
V
IN
REF
DAC
-
10k
V
OUT
REF
5k
+
2.5k
+10V
REF
5k
10k
-
5k
ANALOG
BIP
20V
10V
COMMON
OFF INPUT INPUT
NOTE: “Nibble” is a 4-bit digital word.
FN3096.6
August 7, 2008
3
HI-574A, HI-674A
Absolute Maximum Ratings
Thermal Information
Supply Voltage
Thermal Resistance (Typical, Note 4)
SBDIP Package . . . . . . . . . . . . . . . . . .
PDIP Package* . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
θ
(°C/W)
55
60
θ
(°C/W)
18
N/A
JA
JC
V
V
V
to Digital Common . . . . . . . . . . . . . . . . . . . . . . 0V to +16.5V
to Digital Common . . . . . . . . . . . . . . . . . . . . . . . 0V to -16.5V
CC
EE
to Digital Common . . . . . . . . . . . . . . . . . . . . . . 0V to +7V
LOGIC
Analog Common to Digital Common . . . . . . . . . . . . . . . . . . . .±1V
Control Inputs
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Maximum Storage Temperature Range
(CE, CS, A , 12/8, R/C) to Digital Common . . -0.5V to V
O
+0.5V
LOGIC
Analog Inputs
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
(REFIN, BIPOFF, 10VIN) to Analog Common . . . . . . . . . . ±16.5V
20VIN to Analog Common . . . . . . . . . . . . . . . . . . . . . . . . . . ±24V
REFOUT . . . . .Indefinite Short To Common, Momentary Short To V
CC
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
Operating Conditions
Temperature Range
HI3-574Axx-5, HI1-674Axx-5 . . . . . . . . . . . . . . . . . . 0°C to +75°C
HI1-574AxD-2, HI1-674AxD-2 . . . . . . . . . . . . . . .-55°C to +125°C
Die Characteristics
Transistor Count
HI-574A, HI-674A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
4. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
DC and Transfer Accuracy Specifications Typical at +25°C with V = +15V or +12V, V
= +5V, V = -15V or -12V;
CC
LOGIC EE
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not
production tested.
TEMPERATURE RANGE
-5 (0°C to +75°C)
PARAMETER
DYNAMIC CHARACTERISTICS
J SUFFIX
K SUFFIX
UNITS
Resolution (Max)
12
12
1
Bits
Linearity Error
+25°C (Max)
±1
±1
± /
LSB
LSB
2
1
0°C to +75°C (Max)
± /
2
Max Resolution For Which No Missing Codes Is Guaranteed
+25°C
12
11
12
12
Bits
Bits
T
to T
MAX
MIN
Unipolar Offset (Max)
Adjustable to Zero
Bipolar Offset (Max)
±2
±1.5
LSB
V
V
= 0V (Adjustable to Zero)
= -10V
±4
±4
LSB
IN
IN
±0.15
±0.1
% of FS
Full Scale Calibration Error
+25°C (Max), With Fixed 50Ω Resistor From REF OUT To REF IN
±0.25
±0.25
% of FS
(Adjustable to Zero)
T
to T
to T
(No Adjustment At +25°C)
±0.475
±0.22
±0.375
±0.12
% of FS
% of FS
MIN
MIN
MAX
MAX
T
(With Adjustment To Zero +25°C)
FN3096.6
August 7, 2008
4
HI-574A, HI-674A
DC and Transfer Accuracy Specifications Typical at +25°C with V = +15V or +12V, V
= +5V, V = -15V or -12V;
CC
LOGIC EE
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not
production tested. (Continued)
TEMPERATURE RANGE
-5 (0°C to +75°C)
PARAMETER
J SUFFIX
K SUFFIX
UNITS
Temperature Coefficients
Guaranteed Max Change, T
to T (Using Internal Reference)
MAX
MIN
Unipolar Offset
±2
±2
±9
±1
±1
±2
LSB
LSB
LSB
Bipolar Offset
Full Scale Calibration
Power Supply Rejection Max Change In Full Scale Calibration
+13.5V < V
< +16.5V or +11.4V < V
CC
< +12.6V
±2
1
±1
1
LSB
LSB
LSB
CC
+4.5V < V
< +5.5V
± /
± /
LOGIC
2
2
-16.5V < V < -13.5V or -12.6V < V < -11.4V
±2
±1
EE
EE
ANALOG INPUTS
Input Ranges
Bipolar
-5 to +5 (Note 6)
-10 to +10 (Note 7)
0 to +10 (Note 6)
0 to +20 (Note 7)
V
V
V
V
Unipolar
Input Impedance
10V Span
5k, ±25%
Ω
Ω
20V Span
10k, ±25%
POWER SUPPLIES
Operating Voltage Range
V
V
V
+4.5 to +5.5
+11.4 to +16.5
-11.4 to -16.5
V
V
V
LOGIC
CC
EE
Operating Current
I
I
I
7 Typ, 15 Max
11 Typ, 15 Max
21 Typ, 28 Max
mA
mA
mA
LOGIC
+15V Supply
CC
EE
-15V Supply
Power Dissipation
±15V, +5V
515 Typ, 720 Max
385 Typ
mW
mW
±12V, +5V
Internal Reference Voltage
T
to T
+10.00 ±0.05 Max
2.0 Max
V
MIN
MAX
Output Current, Available For External Loads (External Load Should Not
Change During Conversion).
mA
FN3096.6
August 7, 2008
5
HI-574A, HI-674A
8
DC and Transfer Accuracy Specifications Typical at +25°C with V = +15V or +12V, V
= +5V, V = -15V or -12V;
CC
LOGIC EE
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not
production tested. (Continued)
TEMPERATURE RANGE
-2 (-55°C to +125°C)
PARAMETER
DYNAMIC CHARACTERISTICS
S SUFFIX
T SUFFIX
UNITS
Resolution (Max)
12
12
1
Bits
Linearity Error
+25°C
±1
±1
± /
LSB
LSB
2
-55°C to +125°C (Max)
±1
Max Resolution For Which No Missing Codes Is Guaranteed
+25°C
12
11
12
12
Bits
Bits
T
to T
MAX
MIN
Unipolar Offset (Max)
Adjustable to Zero
Bipolar Offset (Max)
±2
±1.5
LSB
V
V
= 0V (Adjustable to Zero)
= -10V
±4
±4
LSB
IN
±0.15
±0.1
% of FS
IN
Full Scale Calibration Error
+25°C (Max), With Fixed 50Ω Resistor From REF OUT To REF IN
±0.25
±0.25
% of FS
(Adjustable To Zero)
T
T
to T
to T
(No Adjustment At +25°C)
±0.75
±0.50
±0.50
±0.25
% of FS
% of FS
MIN
MAX
(With Adjustment To Zero At +25°C)
MIN
MAX
Temperature Coefficients
Guaranteed Max Change, T
to T
(Using Internal Reference)
MAX
MIN
Unipolar Offset
±2
±2
±1
±2
LSB
LSB
LSB
Bipolar Offset
Full Scale Calibration
±20
±10
Power Supply Rejection Max Change In Full Scale Calibration
+13.5V < V
< +16.5V or +11.4V < V
< +12.6V
CC
±2
1
±1
1
LSB
LSB
LSB
CC
+4.5V < V
< +5.5V
± /
± /
LOGIC
2
2
-16.5V < V < -13.5V or -12.6V < V < -11.4V
±2
±1
EE
EE
ANALOG INPUTS
Input Ranges
Bipolar
-5 to +5 (Note 6)
-10 to +10 (Note 7)
0 to +10 (Note 6)
0 to +20 (Note 7)
V
V
V
V
Unipolar
Input Impedance
10V Span
5k, ±25%
Ω
Ω
20V Span
10k, ±25%
POWER SUPPLIES
Operating Voltage Range
V
V
V
+4.5 to +5.5
+11.4 to +16.5
-11.4 to -16.5
V
V
V
LOGIC
CC
EE
FN3096.6
August 7, 2008
6
HI-574A, HI-674A
DC and Transfer Accuracy Specifications Typical at +25°C with V = +15V or +12V, V
= +5V, V = -15V or -12V;
CC
LOGIC EE
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not
production tested. (Continued)
TEMPERATURE RANGE
-2 (-55°C to +125°C)
PARAMETER
S SUFFIX
T SUFFIX
UNITS
Operating Current
I
I
I
7 Typ, 15 Max
mA
mA
mA
LOGIC
+15V Supply
11 Typ, 15 Max
21 Typ, 28 Max
CC
EE
-15V Supply
Power Dissipation
±15V, +5V
515 Typ, 720 Max
385 Typ
mW
mW
±12V, +5V
Internal Reference Voltage
T
to T
MAX
+10.00 ±0.05 Max
2.0 Max
V
MIN
Output current, available for external loads (external load should not
change during conversion).
mA
Digital Specifications All Models, Over Full Temperature Range; Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production tested.
PARAMETER
Logic Inputs (CE, CS, R/C, A ,12/8)
MIN
TYP
MAX
O
Logic “1”
Logic “0”
Current
+2.4V
-
-
+5.5V
+0.8V
±5µA
-
-0.5V
-
-
±0.1µA
5pF
Capacitance
Logic Outputs (DB11-DB0, STS)
Logic “0” (I
Logic “1” (I
Logic “1” (I
- 1.6mA)
-
-
+0.4V
SINK
- 500µA)
- 10µA)
+2.4V
-
-
-
SOURCE
SOURCE
+4.5V
-
±5µA
-
Leakage (High-Z State, DB11-DB0 Only)
Capacitance
-
-
±0.1µA
5pF
Timing Specifications (HI-574A) +25°C, Note 5, Unless Otherwise Specified.
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
CONVERT MODE
t
t
STS Delay from CE
CE Pulse Width
-
-
-
200
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
DSC
HEC
50
50
50
50
50
0
-
-
t
CS to CE Setup
-
SSC
HSC
SRC
HRC
t
t
CS Low During CE High
R/C to CE Setup
-
-
-
-
t
R/C Low During CE High
-
-
t
A
A
to CE Setup
-
-
SAC
HAC
O
O
t
Valid During CE High
50
15
10
-
-
t
Conversion Time
12-Bit Cycle T
MIN
to T
MAX
20
13
25
17
C
8-Bit Cycle T
to T
MAX
MIN
FN3096.6
August 7, 2008
7
HI-574A, HI-674A
Timing Specifications (HI-574A) +25°C, Note 5, Unless Otherwise Specified. (Continued)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
READ MODE
t
t
Access Time from CE
Data Valid After CE Low
Output Float Delay
CS to CE Setup
-
25
-
75
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DD
HD
-
-
t
100
150
HL
t
50
0
-
-
-
-
-
-
-
-
SSR
t
R/C to CE Setup
-
SRR
t
A
to CE Setup
O
50
0
-
SAR
HSR
HRR
t
CS Valid After CE Low
R/C High After CE Low
-
t
0
-
-
t
A
Valid After CE Low
O
50
300
HAR
t
STS Delay After Data Valid
1200
HS
Timing Specifications (HI-674A) +25°C, Note 5, Unless Otherwise Specified.
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
CONVERT MODE
t
t
STS Delay from CE
CE Pulse Width
-
-
-
200
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
DSC
HEC
50
50
50
50
50
0
-
-
t
CS to CE Setup
-
SSC
HSC
SRC
HRC
t
t
CS Low During CE High
R/C to CE Setup
-
-
-
-
t
R/C Low During CE High
-
-
t
A
A
to CE Setup
-
-
SAC
HAC
O
O
t
Valid During CE High
50
8
-
-
t
Conversion Time
12-Bit Cycle T
MIN
to T
MAX
12
8
15
10
C
8-Bit Cycle T
to T
MAX
5
MIN
READ MODE
t
t
Access Time from CE
Data Valid After CE Low
Output Float Delay
CS to CE Setup
-
75
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DD
HD
25
-
-
-
t
100
150
HL
t
50
0
-
-
-
-
-
-
-
-
SSR
SRR
t
R/C to CE Setup
-
t
A
to CE Setup
O
50
0
-
SAR
HSR
HRR
t
CS Valid After CE Low
R/C High After CE Low
-
t
0
-
-
t
A
Valid After CE Low
O
50
25
HAR
t
STS Delay After Data Valid
850
HS
NOTES:
5. Time is measured from 50% level of digital transitions. Tested with a 50pF and 3kΩ load.
6. For the “10V Input”, Pin 13.
7. For the “20V Input”, Pin 14.
FN3096.6
August 7, 2008
8
HI-574A, HI-674A
The HI-X74AK grade is guaranteed for maximum nonlinearity
Pin Descriptions
1
of ± / LSB. For this grade, this means that an analog value
2
PIN
SYMBOL
DESCRIPTION
which falls exactly in the center of a given code width will result
in the correct digital output code. Values nearer the upper or
lower transition of the code width may produce the next upper
or lower digital output code. The HI-X74AJ is guaranteed to ±1
LSB max error. For this grade, an analog value which falls
within a given code width will result in either the correct code for
that region or either adjacent one.
1
V
Logic supply pin (+5V)
LOGIC
2
12/8
Data Mode Select - Selects between
12-bit and 8-bit output modes.
3
4
CS
Chip Select - Chip Select high disables
the device.
A
Byte Address/Short Cycle - See Table 3
for operation.
O
Note that the linearity error is not user-adjustable.
5
6
R/C
CE
Read/Convert - See Table 3 for operation.
Differential Linearity Error (No Missing Codes)
Chip Enable - Chip Enable low disables
the device.
A specification which guarantees no missing codes requires
that every code combination appear in a monotonic increasing
sequence as the analog input level is increased. Thus every
code must have a finite width. For the HI-X74AK grade, which
guarantees no missing codes to 12-bit resolution, all 4096
codes must be present over the entire operating temperature
ranges. The HI-X74AJ grade guarantees no missing codes to
11-bit resolution over temperature; this means that all code
combinations of the upper 11 bits must be present; in practice
very few of the 12-bit codes are missing.
7
8
V
Positive Supply (+12V/+15V)
CC
REF OUT +10V Reference
9
AC
Analog Common
10
11
12
13
REF IN
Reference Input
V
Negative Supply (-12V/-15V).
EE
BIP OFF Bipolar Offset
10V Input 10V Input - Used for 0V to 10V and -5V to
+5V input ranges.
Unipolar Offset
14
20V Input 20V Input - Used for 0V to 20V and -10V to
+10V input ranges.
1
The first transition should occur at a level / LSB above analog
2
common. Unipolar offset is defined as the deviation of the
actual transition from that point. This offset can be adjusted as
discussed on the following pages. The unipolar offset
temperature coefficient specifies the maximum change of the
transition point over temperature, with or without external
adjustment.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DC
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
STS
Digital Common
Data Bit 0 (LSB)
Data Bit 1
Data Bit 2
Data Bit 3
Bipolar Offset
Data Bit 4
Similarly, in the bipolar mode, the major carry transition
Data Bit 5
(0111 1111 1111 to 1000 0000 0000) should occur for an
1
Data Bit 6
analog value / LSB below analog common. The bipolar
2
Data Bit 7
offset error and temperature coefficient specify the initial
deviation and maximum change in the error over
temperature.
Data Bit 8
Data Bit 9
Data Bit 10
Data Bit 11 (MSB)
Full Scale Calibration Error
The last transition (from 1111 1111 1110 to 1111 1111 1111)
1
should occur for an analog value 1 / LSB below the
2
Status Bit - Status high implies a conversion
is in progress.
nominal full scale (9.9963V for 10.000V full scale). The full
scale calibration error is the deviation of the actual level at
the last transition from the ideal level. This error, which is
typically 0.05 to 0.1% of full scale, can be trimmed out as
shown in Figures 1 and 2. The full scale calibration error
over temperature is given with and without the initial error
trimmed out. The temperature coefficients for each grade
indicate the maximum change in the full scale gain from the
initial value using the internal 10V reference.
Definitions of Specifications
Linearity Error
Linearity error refers to the deviation of each individual code
from a line drawn from “zero” through “full scale”. The point
1
used as “zero” occurs / LSB (1.22mV for 10V span) before
2
the first code transition (all zeros to only the LSB “on”). “Full
scale” is defined as a level 1 / LSB beyond the last code
2
1
transition (to all ones). The deviation of a code from the true
straight line is measured from the middle of each particular
code.
FN3096.6
August 7, 2008
9
HI-574A, HI-674A
In general, sensitive analog signals should be routed between
Temperature Coefficients
ground traces and kept well away from digital lines. If analog
and digital lines must cross, they should do so at right angles.
The temperature coefficients for full-scale calibration,
unipolar offset, and bipolar offset specify the maximum
change from the initial (25°C) value to the value at T
or
MIN
Power Supplies
T
.
MAX
Supply voltages to the HI-X74A (+15V, -15V and +5V) must be
“quiet” and well regulated. Voltage spikes on these lines can
affect the converter’s accuracy, causing several LSBs to flicker
when a constant input is applied. Digital noise and spikes from
a switching power supply are especially troublesome. If
Power Supply Rejection
The standard specifications for the HI-X74A assume use of
+5.00V and ±15.00V or ±12.00V supplies. The only effect of
power supply error on the performance of the device will be
a small change in the full scale calibration. This will result in
a linear change in all lower order codes. The specifications
show the maximum change in calibration from the initial
value with the supplies at the various limits.
switching supplies must be used, outputs should be carefully
filtered to assure “quiet” DC voltage at the converter terminals.
Further, a bypass capacitor pair on each supply voltage
terminal is necessary to counter the effect of variations in
supply current. Connect one pair from pin 1 to 15 (V
LOGIC
Code Width
supply), one from pin 7 to 9 (V
CC
to Analog Common) and
A fundamental quantity for A/D converter specifications is
the code width. This is defined as the range of analog input
values for which a given digital output code will occur. The
nominal value of a code width is equivalent to 1 least
significant bit (LSB) of the full scale range or 2.44mV out of
10V for a 12-bit ADC.
one from pin 11 to 9 (V to Analog Common). For each
EE
capacitor pair, a 10µF tantalum type in parallel with a 0.1µF
ceramic type is recommended.
Ground Connections
Pins 9 and 15 should be tied together at the package to
guarantee specified performance for the converter. In
addition, a wide PC trace should run directly from pin 9 to
(usually) +15V common, and from pin 15 to (usually) the +5V
Logic Common. If the converter is located some distance from
the system’s “single point” ground, make only these
connections to pins 9 and 15: Tie them together at the
package, and back to the system ground with a single path.
This path should have low resistance. (Code dependent
Quantization Uncertainty
Analog-to-digital converters exhibit an inherent quantization
1
uncertainty of ± / LSB. This uncertainty is a fundamental
2
characteristic of the quantization process and cannot be
reduced for a converter of given resolution.
Left-Justified Data
The data format used in the HI-X74A is left-justified. This
means that the data represents the analog input as a fraction
of full-scale, ranging from 0 to
point to the left of the MSB.
currents flow in the V , V and V
terminals, but not
CC EE LOGIC
through the HI-X74A’s Analog Common or Digital Common).
4095
4096
. This implies a binary
Analog Signal Source
Applying the HI-X74A
HI-574A and HI-674A
For each application of this converter, the ground
The device chosen to drive the HI-X74A analog input will see a
nominal load of 5kΩ (10V range) or 10kΩ (20V range).
However, the other end of these input resistors may change
±400mV with each bit decision, creating abrupt changes in
current at the analog input. Thus, the signal source must
maintain its output voltage while furnishing these step changes
in load current, which occur at 1.6μs and 950ns intervals for the
HI-574A and HI-674A, respectively. This requires low output
impedance and fast settling by the signal source.
connections, power supply bypassing, analog signal source,
digital timing and signal routing on the circuit board must be
optimized to assure maximum performance. These areas
are reviewed in the following sections, along with basic
operating modes and calibration requirements.
Physical Mounting and Layout Considerations
LAYOUT
The output impedance of an op amp, for example, has an
open loop value which, in a closed loop, is divided by the
loop gain available at a frequency of interest. The amplifier
should have acceptable loop gain at 600kHz for use with the
HI-X74A. To check whether the output properties of a signal
source are suitable, monitor the HI-X74A’s input (pin 13 or
14) with an oscilloscope while a conversion is in progress.
Each of the twelve disturbances should subside in 1μs or
less for the HI-574A and 500ns or less for the HI-674A. (The
comparator decision is made about 1.5µs and 850ns after
each code change from the SAR for the HI-574A and
HI-674A, respectively.)
Unwanted, parasitic circuit components, (L, R, and C) can
make 12-bit accuracy impossible, even with a perfect A/D
converter. The best policy is to eliminate or minimize these
parasitics through proper circuit layout, rather than try to
quantify their effects.
The recommended construction is a double-sided printed
circuit board with a ground plane on the component side.
Other techniques, such as wire-wrapping or point-to-point
wiring on vector board, will have an unpredictable effect on
accuracy.
FN3096.6
August 7, 2008
10
HI-574A, HI-674A
If the application calls for a Sample/Hold to precede the
Range Connections and Calibration Procedures
converter, it should be noted that not all Sample/Holds are
compatible with the HI-574A in the manner described above.
These will require an additional wideband buffer amplifier to
lower their output impedance. A simpler solution is to use the
Intersil HA-5320 Sample/Hold, which was designed for use
with the HI-574A.
The HI-X74A is a “complete” A/D converter, meaning it is fully
operational with addition of the power supply voltages, a Start
Convert signal, and a few external components as shown in
Figures 1 and 2. Nothing more is required for most
applications.
Whether controlled by a processor or operating in the
stand-alone mode, the HI-X74A offers four standard input
ranges: 0V to +10V, 0V to +20V, ±5V and ±10V. The
maximum errors for gain and offset are listed under
Specifications. If required, however, these errors may be
adjusted to zero as explained below. Power supply and
ground connections have been discussed in an earlier
section.
STS 28
2 12/8
HIGH BITS
24-27
3
4
5
CS
A
O
MIDDLE BITS
20-23
OFFSET
R1
100K
R/C
CE
LOW BITS
16-19
+15V
GAIN
-15V
6
Unipolar Connections and Calibration
R2
Refer to Figure 1. The resistors shown (see Note below)
are for calibration of offset and gain. If this is not required,
replace R2 with a 50Ω, 1% metal film resistor and remove
the network on pin 12. Connect pin 12 to pin 9. Then,
connect the analog signal to pin 13 for the 0V to 10V range,
or to pin 14 for the 0V to 20V range. Inputs to +20V (5V
over the power supply) are no problem - the converter
operates normally.
10 REF IN
REF OUT
100K
100Ω
8
100Ω
+5V
1
7
12 BIP OFF
0V TO +10V
ANALOG
+15V
13 10V
IN
INPUTS
-15V 11
14 20V †
IN
0V TO +20V
DIG COM 15
9 ANA
COM
Calibration consists of adjusting the converter’s most
negative output to its ideal value (offset adjustment), then,
adjusting the most positive output to its ideal value (gain
adjustment). To understand the procedure, note that in
principle, one is setting the output with respect to the
midpoint of an increment of analog input, as denoted by
two adjacent code changes. Nominal value of an increment
is one LSB. However, this approach is impractical because
nothing “happens” at a midpoint to indicate that an
adjustment is complete. Therefore, calibration is performed
in terms of the observable code changes instead of the
midpoint between code changes.
†When driving the 20V (pin 14) input, minimize capacitance on pin 13.
FIGURE 1. UNIPOLAR CONNECTIONS
STS 28
2 12/8
HIGH BITS
24-27
3
4
5
CS
A
O
MIDDLE BITS
20-23
R/C
CE
For example, midpoint of the first LSB increment should be
LOW BITS
16-19
positioned at the origin, with an output code of all 0’s. To do
1
6
this, apply an input of + / LSB (+1.22mV for the 10V range;
2
GAIN
R2
+2.44mV for the 20V range). Adjust the Offset potentiometer
R1 until the first code transition flickers between
0000 0000 0000 and 0000 0000 0001.
10 REF IN
REF OUT
12 BIP OFF
100Ω
100Ω
8
Next, perform a Gain Adjust at positive full scale. Again, the
+5V 1
ideal input corresponding to the last code change is applied.
1
R1
±5V
This is 1 / LSBs below the nominal full scale (+9.9963V for
2
OFFSET
+15V 7
-15V 11
13 10V
IN
ANALOG
INPUTS
10V range; +19.9927V for 20V range). Adjust the Gain
potentiometer R2 for flicker between codes 1111 1111 1110
and 1111 1111 1111.
14 20V †
IN
±10V
DIG COM 15
9 ANA
COM
Bipolar Connections and Calibration
Refer to Figure 2. The gain and offset errors listed under
Specifications may be adjusted to zero using
†When driving the 20V (pin 14) input, minimize capacitance on pin 13.
potentiometers R1 and R2 (see Note below). If this isn’t
FIGURE 2. BIPOLAR CONNECTIONS
FN3096.6
August 7, 2008
11
HI-574A, HI-674A
required, either or both pots may be replaced by a 50Ω, 1%
TABLE 1. HI-574A STAND-ALONE MODE TIMING
metal film resistor.
SYMBOL
PARAMETER
Low R/C Pulse Width
STS Delay from R/C
Data Valid after R/C Low
MIN TYP MAX UNITS
Connect the Analog signal to pin 13 for a ±5V range, or to
pin 14 for a ±10V range. Calibration of offset and gain is
t
50
-
-
-
-
-
-
-
-
200
-
ns
ns
ns
ns
ns
ns
HRL
t
DS
similar to that for the unipolar ranges as discussed above.
1
t
25
First apply a DC input voltage / LSB above negative full
2
HDR
scale (i.e., -4.9988V for the ±5V range, or -9.9976V for the
±10V range). Adjust the offset potentiometer R1 for flicker
t
STS Delay after Data Valid 300
1200
-
HS
t
t
High R/C Pulse Width
Data Access Time
150
-
HRH
DDR
between output codes 0000 0000 0000 and 0000 0000
1
150
0001. Next, apply a DC input voltage 1 / LSBs below
2
positive full scale (+4.9963V for ±5V range; +9.9927V for
±10V range). Adjust the Gain potentiometer R2 for flicker
between codes 1111 1111 1110 and 1111 1111 1111.
Time is measured from 50% level of digital transitions. Tested with a
50pF and 3kΩ load.
TABLE 2. HI-674A STAND-ALONE MODE TIMING
NOTE: The 100Ω potentiometer R2 provides Gain Adjust for the 10V
and 20V ranges. In some applications, a full scale of 10.24V (LSB
equals 2.5mV) or 20.48V (LSB equals 5.0mV) is more convenient.
For these, replace R2 by a 50Ω, 1% metal film resistor. Then, to pro-
vide Gain Adjust for the 10.24V range, add a 200Ω potentiometer in
series with pin 13. For the 20.48V range, add a 500Ω potentiometer
in series with pin 14.
SYMBOL
PARAMETER
Low R/C Pulse Width
STS Delay from R/C
MIN TYP MAX UNITS
t
50
-
-
-
-
-
-
ns
ns
ns
ns
HRL
t
200
-
DS
t
Data Valid after R/C Low 25
HDR
t
STS Delay after Data
Valid
25
850
HS
Controlling the HI-X74A
The HI-X74A includes logic for direct interface to most
microprocessor systems. The processor may take full
control of each conversion, or the converter may operate in
the “stand-alone” mode, controlled only by the R/C input.
Full control consists of selecting an 8-bit or 12-bit
t
t
High R/C Pulse Width
Data Access Time
150
-
-
-
-
ns
ns
HRH
DDR
150
Time is measured from 50% level of digital transitions. Tested with
a 50pF and 3kΩ load.
conversion cycle, initiating the conversion, and reading the
output data when ready-choosing either 12 bits at once or 8
followed by 4, in a left-justified format. The five control
Conversion Length
A Convert Start transition (see Table 1) latches the state of
inputs are all TTL/CMOS-compatible: (12/8, CS, A , R/C
A , which determines whether the conversion continues for
O
O
and CE). Table 3 illustrates the use of these inputs in
controlling the converter’s operations. Also, a simplified
schematic of the internal control logic is shown in Figure 6.
12 bits (A low) or stops with 8 bits (A high). If all 12 bits are
O O
read following an 8-bit conversion, the last three LSBs will
read ZERO and DB3 will read ONE. A is latched because it
O
is also involved in enabling the output buffers (see ““Reading
the Output Data” on page 13). No other control inputs are
latched.
“Stand-Alone Operation”
The simplest control interface calls for a single control line
connected to R/C. Also, CE and 12/8 are wired high, CS and
TABLE 3. TRUTH TABLE FOR HI-X74A CONTROL INPUTS
A
are wired low, and the output data appears in words of
O
12 bits each.
CE CS R/C 12/8
A
OPERATION
O
The R/C signal may have any duty cycle within (and
including) the extremes shown in Figures 7 and 8. In
general, data may be read when R/C is high unless STS is
also high, indicating a conversion is in progress. Timing
parameters particular to this mode of operation are listed in
Tables 1 and 2.
0
X
↑
↑
1
1
1
1
1
1
1
X
1
0
0
↓
↓
0
0
0
0
0
X
X
0
0
0
0
↓
↓
1
1
1
X
X
X
X
X
X
X
X
1
X
None
None
X
0
1
0
1
0
1
X
0
1
Initiate 12-bit conversion
Initiate 8-bit conversion
Initiate 12-bit conversion
Initiate 8-bit conversion
Initiate 12-bit conversion
Initiate 8-bit conversion
Enable 12-bit Output
0
Enable 8 MSBs Only
0
Enable 4 LSBs Plus 4 Trailing Zeroes
FN3096.6
August 7, 2008
12
HI-574A, HI-674A
12 output lines become active simultaneously, for interface
Conversion Start
to a 12-bit or 16-bit data bus. The A input is ignored.
O
A conversion may be initiated as shown in Table 3 by a logic
transition on any of three inputs: CE, CS or R/C. The last of
the three to reach the correct state starts the conversion, so
one, two or all three may be dynamically controlled. The
nominal delay from each is the same, and if necessary, all
three may change state simultaneously. However, to ensure
that a particular input controls the start of conversion, the
other two should be set up at least 50ns earlier. See the
HI-X74A Timing Specifications, Convert Mode.
With 12/8 low, the output is organized in two 8-bit bytes,
selected one at a time by A . This allows an 8-bit data bus
O
to be connected as shown in Figure 5. A is usually tied to
O
the least significant bit of the address bus, for storing the
HI-X74A output in two consecutive memory locations. (With
A
low, the 8 MSBs only are enabled. With A high, 4 MSBs
O
O
are disabled, bits 4 through 7 are forced low, and the 4 LSBs
are enabled). This two byte format is considered “left justified
data,” for which a decimal (or binary!) point is assumed to
the left of byte 1:
This variety of HI-X74A control modes allows a simple
interface in most system applications. The Convert Start
timing relationships are illustrated in Figure 3.
BYTE 1
BYTE 2
The output signal STS indicates status of the converter by
going high only while a conversion is in progress. While STS
is high, the output buffers remain in a high impedance state
and data cannot be read. Also, an additional Start Convert
will not reset the converter or re-initiate a conversion while
STS is high.
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
•
MSB
LSB
Further, A may be toggled at any time without damage to
O
the converter. Break-before-make action is guaranteed
between the two data bytes, which assures that the outputs
strapped together in Figure 5 will never be enabled at the
same time.
Reading the Output Data
The output data buffers remain in a high impedance state
until four conditions are met: R/C high, STS low, CE high
and CS low. At that time, data lines become active according
A read operation usually begins after the conversion is
complete and STS is low. For earliest access to the data,
however, the read should begin no later than (t
before STS goes low. See Figure 4.
to the state of inputs 12/8 and A . Timing constraints are
O
+ t
)
DD
HS
illustrated in Figure 4.
The 12/8 input will be tied high or low in most applications,
though it is fully TTL/CMOS-compatible. With 12/8 high, all
CE
t
HEC
HSC
CE
CS
t
t
HSR
SSR
t
SSC
CS
t
HRR
t
t
SRC
R/C
R/C
t
t
SRR
t
HRC
A
O
A
O
t
SAR
HAR
t
SAC
STS
t
HAC
t
STS
HS
t
t
C
HD
t
DSC
DATA
VALID
DB11-DB0
HIGH IMPEDANCE
HIGH IMPEDANCE
DB11-DB0
t
t
HL
DD
See HI-X74A Timing Specifications for more information.
See HI-X74A Timing Specifications for more information.
FIGURE 4. READ CYCLE TIMING
FIGURE 3. CONVERT START TIMING
FN3096.6
August 7, 2008
13
HI-574A, HI-674A
A
ADDRESS BUS
O
1
2
28
27
26
25
24
23
22
21
20
19
18
17
STS
12/8
DB11 (MSB)
3
4
A
O
5
DATA
BUS
6
7
HI-X74A
8
9
10
11
12
13
14
DB0 (LSB) 16
DIG.
15
COM.
FIGURE 5. INTERFACE TO AN 8-BIT DATA BUS
NIBBLE B ZERO
OVERRIDE
NIBBLE A, B
NIBBLE C
INPUT BUFFERS
12/8
READ CONTROL
CS
A
O
STATUS
R/C
CE
CURRENT
CONTROLLED
OSCILLATOR
STROBE
CLOCK
CONVERT
CONTROL
EOC9
CK
POWER UP
RESET
Q
D
RESET
Q
A
LATCH
O
EOC13
FIGURE 6. HI-X74A CONTROL LOGIC
FN3096.6
August 7, 2008
14
HI-574A, HI-674A
t
HRL
R/C
t
DS
STS
t
C
t
HDR
t
HS
DATA
VALID
DATA
VALID
DB11-DB0
FIGURE 7. LOW PULSE FOR R/C - OUTPUTS ENABLED AFTER CONVERSION
R/C
t
t
DS
HRH
STS
t
C
t
HDR
t
DDR
HIGH-Z
HIGH-Z
DB11-DB0
DATA
VALID
FIGURE 8. HIGH PULSE FOR R/C - OUTPUTS ENABLED WHILE R/C HIGH, OTHERWISE HIGH-Z
FN3096.6
August 7, 2008
15
HI-574A, HI-674A
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
Analog: 3070mm x 4610mm
Digital: 1900mm x 4510mm
Type: Nitride Over Silox
Nitride Thickness: 3.5kÅ ±0.5kÅ
Silox Thickness: 12kÅ ±1.5kÅ
METALLIZATION:
WORST CASE CURRENT DENSITY:
Digital Type: Nitrox
Thickness: 10kÅ ±2kÅ
5
2
1.3 x 10 A/cm
Metal 1: AlSiCu
Thickness: 8kÅ ±1kÅ
Metal 2: AlSiCu
Thickness: 16kÅ ±2kÅ
Analog Type: Al
Thickness: 16kÅ ±2kÅ
Metallization Mask Layout
HI-574A, HI-674A
R/C
DB10
DB9
CE
V
CC
V
REFOUT
ANALOG
COMMON
DB8
DB7
DB6
DB5
ANALOG
COMMON
ANALOG
COMMON
V
REFIN
DB4
DB3
DB2
V
EE
FN3096.6
August 7, 2008
16
HI-574A, HI-674A
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
c1 LEAD FINISH
D28.6 MIL-STD-1835 CDIP2-T28 (D-10, CONFIGURATION C)
28 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
-A-
-D-
E
INCHES MILLIMETERS
MIN
BASE
METAL
(c)
SYMBOL
MAX
0.232
0.026
0.023
0.065
0.045
0.018
0.015
1.490
0.610
MIN
-
MAX
5.92
NOTES
b1
A
b
-
-
2
3
-
M
A
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
0.66
-B-
b1
b2
b3
c
0.58
SECTION A-A
S
S
S
D
bbb
C
A - B
1.65
D
1.14
4
2
3
-
BASE
PLANE
S2
Q
0.46
-C-
SEATING
PLANE
c1
D
0.38
L
37.85
15.49
S1
b2
eA
A A
E
0.500
12.70
-
e
eA/2
aaa M C A - B S D S
b
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.600 BSC
0.300 BSC
15.24 BSC
7.62 BSC
-
ccc
M
C A - B S D S
-
NOTES:
0.125
0.200
3.18
5.08
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.005
0.060
0.38
0.13
0.13
1.52
5
6
7
-
S1
S2
α
-
-
-
-
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
o
o
o
o
90
105
90
105
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
-
2
8
N
28
28
5. Dimension Q shall be measured from the seating plane to the
base plane.
Rev. 0 5/18/94
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
FN3096.6
August 7, 2008
17
HI-574A, HI-674A
Dual-In-Line Plastic Packages (PDIP)
E28.6 (JEDEC MS-011-AB ISSUE B)
28 LEAD DUAL-IN-LINE PLASTIC PACKAGE
N
E1
INCHES MILLIMETERS
INDEX
1
2
3
N/2
AREA
SYMBOL
MIN
MAX
0.250
-
MIN
-
MAX
6.35
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
0.015
0.125
0.014
0.030
0.008
1.380
0.005
0.600
0.485
0.39
3.18
0.356
0.77
0.204
4
D
E
0.195
0.022
0.070
0.015
1.565
-
4.95
0.558
1.77
0.381
39.7
-
-
BASE
PLANE
A2
A
-
SEATING
PLANE
B1
C
8
L
C
L
-
D1
B1
eA
A1
A
D1
e
D
35.1
5
eC
C
B
D1
E
0.13
15.24
12.32
5
eB
0.010 (0.25) M
C
B S
0.625
0.580
15.87
14.73
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.600 BSC
2.54 BSC
15.24 BSC
-
e
e
6
A
B
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.700
0.200
-
17.78
5.08
7
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
N
28
28
JEDEC seating plane gauge GS-3.
Rev. 1 12/00
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
e
6. E and
are measured with the leads constrained to be perpendic-
A
-C-
ular to datum
.
7. e and e are measured at the lead tips with the leads unconstrained.
B
C
e
must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3096.6
August 7, 2008
18
相关型号：
©2020 ICPDF网 联系我们和版权申明