IMISM562BZ [CYPRESS]
Clock Generator, 200MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8;
| 型号： | IMISM562BZ |
| 厂家： | 
CYPRESS |
| 描述： | Clock Generator, 200MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总8页 (文件大小：384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SM562
Spread Spectrum Clock Generator
Features
Applications
• 54- to 200-MHz operating frequency range
• Wide (9) range of spread selections
• Accepts clock and crystal inputs
• Low power dissipation
• 3.3V = 165 mw. (Fin = 200 MHz)
• Frequency spread disable function
• Center spread modulation
• High-resolution VGA controllers
• LCD panels and monitors
• Workstations and servers
Benefits
• Peak electromagnetic interference (EMI) reduction by
8 to 16 dB
• Fast time to market
• Cost reduction
• Low cycle-to cycle jitter
• 8-pin SOIC package
Pin Configuration
Block Diagram
250 K
Xin/CLK
VDD
1
2
3
4
8
7
6
5
Xout
S0
Xin/
CLK
REFERENCE
DIVIDER
1
8
LF
4 pf
PD
CP
VSS
S1
MODULATION
CONTROL
Xout
SSCLK
SSCC
FEEDBACK
DIVIDER
8 pF
VCO
2
3
VDD
VSS
INPUT
DECODER
LOGIC
DIVIDER
AND MUX
4
SSCLK
5
6
7
SSCC
S1
S0
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07022 Rev. *A
Revised May 2,2002
SM562
.
Pin Description
Pin
Pin
Type
Pin Description
Number Name
1
2
3
4
5
Xin/CLK
VDD
I
Clock or Crystal connection input. Refer to Table 1 for input frequency range selection.
Positive power supply.
P
P
O
I
GND
Power supply ground.
SSCLK
SSCC
SSCG Modulated clock output.
Spread Spectrum Clock Control (Enable/Disable) function. SSCG function is enabled when input
is high and disabled when input is low. This pin is pulled high internally.
6
7
8
S1
S0
I
I
Tri-Level Logic input control pin used to select Frequency and Bandwidth. See Figure 1 for
programming details. This pin does not have an internal pull-up or pull-down resistor.
Tri-Level Logic input control pin used to select Frequency and Bandwidth. See Figure 1 for
programming details. This pin does not have an internal pull-up or pull-down resistor.
Xout
O
Oscillator output pin connected to crystal. Leave this pin unconnected when Xin/CLK is driven by
an external clock source.
select one of the nine available Frequency Modulation and
Spread% ranges. Refer to Table 1 for programming details.
General Description
The CYPRESS SM562 is a Spread Spectrum Clock Generator
(SSCG) IC used for the purpose of reducing EMI found in
today’s high-speed digital electronic systems.
The SM562 is intended for applications with a reference
frequency in the range of 54 to 200 MHz.
A wide range of digitally selectable spread percentages is
made possible by using Three-Level (High, Low and Middle)
logic at the S0 and S1 digital control inputs.
The SM562 uses a Cypress proprietary phase-locked loop
(PLL) and Spread Spectrum Clock (SSC) technology to
synthesize and frequency modulate the input frequency of the
reference clock. By frequency modulating the clock, the
measured EMI at the fundamental and harmonic frequencies
of clock (SSCLK) is greatly reduced.
The output spread (frequency modulation) is symmetrically
centered on the input frequency.
Spread Spectrum Clock Control (SSCC) function enables or
disables the frequency spread and is provided for easy
comparison of system performance during EMI testing.
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory requirements and time to
market without degrading system performance.
The SM562 is available in an eight-pin SOIC package with a
0° to 70°C operating temperature range.
The SM562 is a very simple and versatile device to use. The
frequency and spread% range is selected by programming S0
and S1 digital inputs. These inputs use three (3) logic states
including High (H), Low (L), and Middle (M) logic levels to
Refer to SM561 for applications with lower drive requirements
and the SM560 with lower drive and frequency requirements.
Table 1. Frequency and Spread% Selection (Center Spread)
54– 108 MHz (Low Range)
Input
Frequency
(MHz)
S1=M
S0=M
S1=M
S0=0
S1=1
S0=0
S1=0
S0=0
S1=0
S0=M
Select the
Frequency and
Spread %
desired and then
set S1, S0 as
indicated.
54– 60
3.6
3.5
3.3
3.0
2.6
3.1
3.0
2.8
2.5
2.3
2.6
2.5
2.4
2.1
1.9
2.1
2.0
1.9
1.7
1.5
1.8
1.7
1.6
1.4
1.3
60 – 70
70 – 80
80 - 100
100 - 108
108 – 200 MHz (High Range)
Input
Frequency
(MHz)
S1=1
S0=M
S1=0
S0=1
S1=1
S0=1
S1=M
S0=1
Select the
Frequency and
Spread %
desired and then
set S1, S0 as
indicated.
108 – 120
120 – 130
130 – 140
140 – 150
150 - 160
160 – 170
170 - 180
180 – 190
190 - 200
2.3
2.3
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.7
1.7
1.7
1.6
1.5
1.5
1.4
1.3
1.2
1.1
1.1
1.1
1.1
1.0
0.9
0.9
0.8
0.7
0.9
0.9
0.9
0.9
0.8
0.8
0.7
0.7
0.6
Document #: 38-07022 Rev. *A
Page 2 of 8
SM562
pin. These states are defined as “0” (Low), “M” (Middle), and
“1” (One). Each of these states has a defined voltage range
that is interpreted by the SM561 as a “0,” an “M,” or a “1” logic
state. Refer to Table 1 for each logic state. By using two equal
value resistors (typically 20K), the “M” state can easily be
programmed. Pins 6 or 7 can be tied directly to ground or VDD
for logic “0” or “1,” respectively.
Tri-Level Logic
With binary logic, four states can be programmed with two
control lines whereas Tri-Level Logic can program nine logic
states using two control lines. Tri-Level Logic in the SM561 is
implemented by defining a third logic state in addition to the
standard logic “1” and “0.” Pins 6 and 7 of the SM561
recognize a logic state by the voltage applied to the respective
VDD = 3.3 VDC
VDD = 3.3 VDC
VDD = 3.3 VDC
SM562
SM562
SM562
20K
20K
7
6
5
1.65 VDC
0 VDC
VDD
7
6
5
7
6
5
VDD
EX. 1
EX. 2
EX. 3
Figure 1.
Document #: 38-07022 Rev. *A
Page 3 of 8
SM562
Absolute Maximum Ratings[1]
Supply Voltage (AVDD or DVDD:......................................+ 6V
AVDD–DVDD: ............................................................± 300mV
AGND–DGND..........................................................± 300mV
Junction Temperature: ......................................0°C to +70°C
Storage Temperature (10 sec. soldering): ................ + 300°C
Operating Temperature:...................................... 0°C to 70°C
Storage Temperature................................... -65°C to +150°C
DC Electrical Characteristics VDD = 3.3V, Temp. = 25°C and CL (pin 4) = 15 pF, unless otherwise noted
Parameter
VDD
Description
Power Supply Range
Input High Voltage
Input Middle Voltage
Input Low Voltage
Conditions
Min.
2.97
Typ.
3.3
Max.
3.63
VDD
Unit
V
± 10%
VINH
VINM
VINL
VOH1
VOH2
VOL1
VOL2
Cin1
S0 and S1 only
0.85VDD
VDD
V
S0 and S1 only
0.40VDD 0.50VDD 0.60VDD
V
S0 and S1 only
0.0
2.4
2.0
0.0
0.15VDD
V
Output High Voltage
Output High Voltage
Output Low Voltage
Output Low Voltage
Input Capacitance
Input Capacitance
Input Capacitance
Power Supply Current
Power Supply Current
Power Supply Current
IOH = 6 ma
V
IOH = 20 ma
V
IOH = 6 ma
0.4
1.2
5
V
IOH = 20 ma
V
Xin/CLK (pin 1)
3
6
3
4
8
pF
pF
pF
mA
mA
Cin2
Xout (pin 8)
10
5
Cin2
S0, S1, SSCC (pins 7,6,5)
FIN = 65 MHz, CL = 15 pF
FIN = 200 MHz, CL = 33 pF
FIN = 200 MHz, No Load
4
IDD1
IDD2
IDD3
35
50
48
45
56
54
Electrical Timing Characteristics VDD = 3.3V, T = 25°C and CL = 15 pF, unless otherwise noted.
Rise/Fall@ 0.4 – 2.4V, Duty@ 1.5V
Parameter
ICLKFR
tR
Description
Input Clock Frequency Range
Clock Rise Time (pin 4)
Clock Fall Time (pin 4)
Clock Rise Time (pin 4)
Clock Fall Time (pin 4)
Input Clock Duty Cycle
Output Clock Duty Cycle
Frequency Modulation
Frequency Modulation
Cycle-to-Cycle Jitter
Conditions
Peak-Peak = 3.0V
Min.
54
Typ.
Max.
200
0.80
0.80
1.60
1.85
80
Unit
MHz
ns
SSCLK1, CL = 15 pF, 200 MHz
SSCLK1, CL = 15 pF, 200 MHz
SSCLK1, CL = 33 pF, 200 MHz
SSCLK1, CL = 33 pF, 200 MHz
XIN/CLK (pin 1)
0.70
0.70
1.40
1.65
20
0.75
0.75
1.50
1.75
50
tF
ns
tR
ns
tF
ns
DTYin
DTYout
FM1
%
SSCLK1 (pin 4)
45
50
55
%
Fin = 70 MHz
29.5
85.0
30.0
85.4
150
175
250
30.5
86.0
175
200
300
kHz
kHz
ps
FM2
Fin = 200 MHz
JCC1
JCC2
Fin = 54 MHz, Mod ON
Fin =120 MHz, Mod ON
Fin = 200 MHz, Mod ON
Cycle-to-Cycle Jitter
ps
JCC3
Cycle-to-Cycle Jitter
ps
Note:
1. Operation at any Absolute Maximum Rating is not Implied.
Document #: 38-07022 Rev. *A
Page 4 of 8
SM562
consider a 200-MHz clock with a 50% duty cycle. From a
200-MHz clock we know the following.
SSCG Theory of Operation
The SM562 is a PLL-type clock generator using a proprietary
Cypress design to modulate the reference clock. By precisely
controlling the bandwidth of the output clock, the SM562
becomes a low-EMI clock generator. The theory and detailed
operation of the SM562 will be discussed in the following
sections.
50 %
50 %
Tc = 5.0 ns
Clock Frequency = fc = 200MHz
Clock Period = Tc =1/200 MHz = 5.0 ns
EMI
All digital clocks generate unwanted energy in their harmonics.
Conventional digital clocks are square waves with a duty cycle
that is very close to 50%. Because of this 50/50-duty cycle,
digital clocks generate most of their harmonic energy in the
odd harmonics, i.e., third, fifth, seventh, etc. It is possible to
reduce the amount of energy contained in the fundamental
and odd harmonics by increasing the bandwidth of the funda-
mental clock frequency. Conventional digital clocks have a
very high Q factor, which means that all of the energy at that
frequency is concentrated in a very narrow bandwidth, conse-
quently, higher energy peaks. Regulatory agencies test
electronic equipment by the amount of peak energy radiated
from the equipment. By reducing the peak energy at the funda-
mental and harmonic frequencies, the equipment under test is
able to satisfy agency requirements for EMI. Conventional
methods of reducing EMI have been to use shielding, filtering,
multilayer PCBs etc. The SM562 reduces the peak energy in
the clock by increasing the clock bandwidth, thus, lowering
the Q.
If this clock is applied to the Xin/CLK pin of the SM562, the
output clock at pin 4 (SSCLK) will be sweeping back and forth
between two frequencies. These two frequencies, F1 and F2,
are used to calculate to total amount of spread or bandwidth
applied to the reference clock at pin 1. As the clock is making
the transition, sweep, from F1 to F2, the amount of time and
sweep waveform become a very important factor in the
amount of EMI reduction realized from an SSCG clock.
The modulation domain analyzer is used to visualize the
sweep waveform and sweep period. Figure 2 shows the
modulation profile of a 200-MHz SSCG clock. Notice that the
actual sweep waveform is not a simple sine or sawtooth
waveform. Figure 2 also shows a scan of the same SSCG
clock using a spectrum analyzer. The spectrum analyzer scan
in Figure 2 shows a 10-dB reduction in the peak RF energy
when using the SM562 SSCG clock.
Modulation Rate
Spectrum Spread Clock Generators utilize frequency
modulation (FM) to distribute energy over a specific band of
frequencies. The maximum frequency of the clock (Fmax) and
minimum frequency of the clock (Fmin) determine this band of
frequencies. The time required to transition from Fmin to Fmax
and back to Fmin is the period of the Modulation Rate, Tmr.
Modulation Rates of SSCG clocks are generally referred to in
terms of frequency or Fmod = 1/Tmod.
SSCG
SSCG uses a patented technology of modulating the clock
over a very narrow bandwidth and controlled rate of change,
both peak and cycle to cycle. The SM562 takes a narrow band
digital reference clock in the range of 54–200 MHz and
produces a clock that sweeps between a controlled start (F1)
and stop (F2) frequency at a precise rate of change. To under-
stand what happens to a clock when SSCG is applied,
The input clock frequency, Fin, and the internal divider count,
Cdiv, determine the Modulation Rate. In some SSCG clock
generators, the selected range determines the internal divider
count. In other SSCG clocks, the internal divider count is fixed
over the operating range of the part. The SM562 has a fixed
divider count of 2332.
Document #: 38-07022 Rev. *A
Page 5 of 8
SM562
Device
Cdiv
SM562
2332 (All Ranges)
Example:
Device =
Fin
Range =
SM562
200 MHz
S1 = 1, S0 = 1
=
Then;
Modulation Rate = Fmod = 200 MHz/2332 = 85.7 kHz.
Modulation Profile
Spectrum Analyzer
Figure 2. SSCG Clock, SM562, Fin = 200 MHz
SM562 Application Schematic
200 MHz Reference Clock
1
2
8
N/C
Xin/CLK
VDD
Xout
VDD
7
VDD
S0
SM562
C5
22 uF.
C6
0.1 uF
3
6
5
GND
S1
R5
22
4
SSCLK
SSCC
Application Load
Figure 3. Application Schematic
The schematic in Figure 3 above demonstrates how the
SM562 is configured in a typical application. This application
is using a 200-MHz reference clock connected to pin 1.
Because an external reference clock is used, pin 8 (Xout) is
left unconnected.
This configuration depicts the profile and spectrum scans
shown in figure 3. Note that S0 = S1 = 1, for a spread of
approximately 0.7%.
Document #: 38-07022 Rev. *A
Page 6 of 8
SM562
Ordering Information[2]
Part Number
IMISM562BZ
Package Type
Product Flow
Commercial, 0° to 70°C
Commercial, 0° to 70°C
8-pin SOIC
IMISM562BZT
8-pin SOIC–Tape and Reel
Marking: Example:
IMI
SM562BS
Date Code, Lot#
SM562 B S
Package
S = SOIC
Revision
IMI Device Number
Package Drawing and Dimensions
8-lead (150-Mil) SOIC S8
51-85066-A
All product and company names mentioned in this document are the trademarks of their respective holders.
Note:
2. The ordering part number differs from the marking on the actual device.
Document #: 38-07022 Rev. *A
Page 7 of 8
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
SM562
Document Title:SM562 Spread Spectrum Clock Generator
Document Number: 38-07022
Orig. of
Rev.
ECN No. Issue Date
Description of Change
Convert from IMI to Cypress
Change the marking suffix
Change
**
106950
113522
06/06/01
05/08/02
IKA
*A
DMG
Document #: 38-07022 Rev. *A
Page 8 of 8
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