IMISSTV850DT [CYPRESS]
PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO48, TSSOP-48;
| 型号： | IMISSTV850DT |
| 厂家： | 
CYPRESS |
| 描述： | PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO48, TSSOP-48 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总9页 (文件大小：78K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
50
PRELIMINARY
SSTV850
Differential Clock Buffer/Driver
Features
Description
• Phase-Lock Loop Clock Distribution for Double Data
Rate Synchronous DRAM Applications
This PLL clock buffer is designed for 2.5 VDD and 2.5AVDD
operation and differential data input and output levels.
• Input to Ten Differential Outputs
• ExternalFeedbackPins(FBINT, FBINC)areusedtoSyn-
chronize the Outputs to the Clock Input
• SSCG: Spread Aware for EMI Reduction
• 48 Pin TSSOP Package
This device is a zero delay buffer that distributes a differential
clock input pair (CLKINT, CLKINC) to ten differential pair of
clock outputs (YT[0:9], YC[0:9]) and one differential pair feed-
back clock output (FBOUTT, FBOUTC). The clock outputs are
individually controlled by the serial inputs SCLK and SDATA.
• Conforms to JEDEC JC40 & JC42.5 DDR Specifications
The two line serial bus can set each output clock pair (YT[0:9],
YC[0:9]) to the Hi-Z state. When AVDD is grounded, the PLL
is turned off and bypassed for the test purposes.
The PLL in this device uses the input clocks (CLKINT,CLKINC)
and the feedback clocks (FBINT,FBINC) to provide high-per-
formance, low skew, low jitter output differential clocks.
Block Diagram
Pin Configuration
10
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VSS
VSS
YC0
YT0
YC0
2
YC5
YT1
YC1
3
YT5
YT0
4
VDDQ
YT6
VDDQ
YT1
5
YT2
YC2
6
YC6
YC1
7
VSS
VSS
YT3
YC3
8
VSS
VSS
SCLK
Serial
Interface
Logic
9
YC7
YC2
YT4
YC4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
YT7
SDATA
YT2
VDDQ
SDATA
FBINT
FBINC
VDDQ
VDD
YT5
YC5
SCLK
CLKINT
CLKINC
VDDI
AVDD
AVSS
VSS
YT6
YC6
CLKINT
CLKINC
YT7
YC7
FBOUTC
FBOUTT
PLL
YT8
YC8
VSS
YC8
YT8
FBINT
FBINC
YC3
YT3
YT9
YC9
VDDQ
YT9
VDDQ
YT4
AVDD
YC9
VSS
YC4
FBOUTT
FBOUTC
VSS
Cypress Semiconductor Corporation
Document #: 38-07215 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised December 3, 2001
PRELIMINARY
SSTV850
Pin Description[1, 2]
Pin
13
14
35
Name
CLKINT
CLKINC
FBINC
I/O
Description
Electrical Characteristics
I
I
I
Complementary Clock Input.
Complementary Clock Input.
LV Differential Input
FeedbackClockInput.Connectto Differential Input
FBOUTC for accessing the PLL.
36
FBINT
YT(0:9)
YC(0:9)
FBOUTT
I
FeedbackClockInput.Connectto
FBOUTT for accessing the PLL.
3, 5, 10, 20, 22
46, 44, 39, 29,27
O
O
O
Clock Outputs
Differential Outputs
2, 6, 9, 19, 23
47, 43, 40,30,26
Clock Outputs
32
Feedback Clock Output. Connect Differential Outputs
to FBINT for normal operation. A
bypass delay capacitor at this out-
put will control Input Reference/
Output Clocks phase relation-
ships.
33
FBOUTC
O
Feedback Clock Output. Connect
to FBINC for normal operation. A
bypass delay capacitor at this out-
put will control Input Reference/
Output Clocks phase relation-
ships.
12
37
SCLK
I, PU
Serial Clock Input. Clocks data at DataInputforthetwo-lineserial
SDATA into the internal register. bus
SDATA
I/O, PU
Serial Data Input. Input data is
Data Input and Output for the
clocked to the internal register to two-line serial bus
enable/disableindividualoutputs.
This provides flexibility in power
management.
11
VDD
2.5V power Supply for Logic
2.5V Nominal
2.5V Nominal
4, 21, 28, 34, 38, 45
VDDQ
2.5V Power Supply for Output
Clock Buffers.
16
15
AVDD
VDDI
2.5V Power Supply for PLL
2.5V Nominal
Power Supply for two line serial
Interface
2.5V or 3.3V Nominal
1, 7, 8, 18, 24, 25, 31,
41, 42, 48
VSS
Common Ground
0.0V Ground
17
AVSS
Analog Ground
0.0V Analog Ground
Notes:
1. PU= Internal Pull-Up
2. A bypass capacitor (0.1 µF) should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces
Document #: 38-07215 Rev. *A
Page 2 of 9
PRELIMINARY
SSTV850
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields; however,
precautions should be taken to avoid application of any volt-
age higher than the maximum rated voltages to this circuit. For
proper operation, Vin and Vout should be constrained to the
range:
Maximum Ratings
Input Voltage Relative to VSS:...............................VSS – 0.3V
Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V
Storage Temperature: .................................–65°C to +150°C
Operating Temperature:....................................0°C to +85°C
Maximum Power Supply: ................................................3.5V
VSS < (Vin or Vout) < VDD
Unused inputs must always be tied to an appropriate logic volt-
age level (either VSS or VDD).
DC Parameters[3] (VDDA = VDDQ = 2.5V ± 5%, VDDI = 3.3V ± 5%, TA = 0°C to +85°C)
Parameter
Description
Input Low Voltage
Input High Voltage
Conditions
SDATA, SCLK
Min.
Typ.
Max.
Unit
V
VIL
VIH
VID
1.0
2.2
V
Differential Input
Voltage[4]
CLKINT, FBINT
CLKTIN, FBINT
0.35
VDDQ + 0.6
(VDDQ/2) + 0.2
10
V
VIX
IIN
Differential Input
(VDDQ/2) –
VDDQ/2
V
Crossing Voltage[5]
0.2
Input Current
VIN =0VorVIN =VDDQ, CLKINT,
FBINT
–10
µA
IOL
IOH
Output Low Current
Output High Current
Output Low Voltage
Output High Voltage
Output Voltage Swing[6}
VDDQ = 2.375V, VOUT = 1.2V
VDDQ = 2.375V, VOUT = 1V
VDDQ = 2.375V, IOL = 12 mA
VDDQ = 2.375V, IOH = –12 mA
26
35
mA
mA
V
–18
–32
VOL
VOH
VOUT
VOC
0.6
1.7
1.1
V
VDDQ-0.4
V
Output Crossing
Voltage[7]
(VDDQ/2) –
VDDQ/2
(VDDQ/2) + 0.2
V
0.2
IOZ
High-ImpedanceOutput VO = GND or VO = VDDQ
Current
–10
10
µA
IDDQ
Dynamic Supply
Current[8]
All VDDQ and VDDI
FO = 170 MHz
,
235
300
mA
IDD
Cin
PLL Supply Current
VDDA only
9
3
12
mA
pF
Input Pin Capacitance
2.5
3.5
Notes:
3. Unused inputs must be held HIGH or LOW to prevent them from floating.
4. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and VCP is the complementary
input level.
5. Differential cross-point input voltage is expected to track VDDQ and is the voltage at which the differential signals must be crossing.
6. For load conditions see Figure 7.
7. The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120Ω resistor. See Figure 7.
8. All outputs switching loaded with 16 pF in 60Ω environment. See Figure 7.
Document #: 38-07215 Rev. *A
Page 3 of 9
PRELIMINARY
SSTV850
AC Parameters[9, 10] (VDD = VDDQ = 2.5V±5%, VDDI = 3.3V±5%, TA = 0°C to +85°C)
Parameter
fCLK
Description
Operating Clock Frequency
Input Clock Duty Cycle[11]
Maximum PLL lock Time
Output Clocks Slew Rate
Output Enable Time[12]
(all outputs)
Output Disable Time[12]
(all outputs)
Conditions
Min.
60
Typ. Max.
Unit
MHz
%
AVDD, VDD = 2.5V ± 0.2V
170
60
tDC
40
tlock
100
2
µs
tR/tF
20% to 80% of VOD
1
V/ns
ns
tpZL, tpZH
3
3
tpLZ, tpHZ
ns
tCCJ
Cycle to Cycle Jitter
Half-period jitter [14]
f > 66MHz
f > 66MHz
–100
–100
100
100
6
ps
ps
ns
tjit(h-per)
tPLH
Low-to-High Propagation Delay,
CLKINT to YT[0:9]
1.5
1.5
3.5
3.5
tPHL
High-to-Low Propagation Delay,
CLKINT to YT[0:9]
6
ns
tSKEW
Any Output to Any Output Skew[13]
Phase Error[13]
100
150
50
ps
ps
ps
tPHASE
tPHASEJ
–150
–50
Phase Error Jitter
f > 66MHz
Zero Delay Buffer
When used as a zero delay buffer the SSTV850 will likely be
in a nested clock tree application. For these applications the
SSTV850 offers a differential clock input pair as a PLL refer-
ence. The SSTV850 then can lock onto the reference and
translate with near zero delay to low skew outputs. For normal
operation, the external feedback input, FBINT, is connected to
the feedback output, FBOUTT. By connecting the feedback
output to the feedback input the propagation delay through the
device is eliminated. The PLL works to align the output edge
with the input reference edge thus producing a near zero de-
lay. The reference frequency affects the static phase offset of
the PLL and thus the relative delay between the inputs and
outputs.
When VDDA is strapped low, the PLL is turned off and by-
passed for test purposes.
Function Table
Inputs
Outputs
PLL
VDDA
GND
GND
2.5V
CLKINT
CLKINC
YT(0:9)[15] YC(0:9)[15]
FBOUTT
FBOUTC
L
H
L
H
L
L
H
L
H
L
L
H
L
H
L
BYPASSED/OFF
BYPASSED/OFF
H
L
H
L
H
L
On
On
2.5V
H
H
H
Nom
Design
Nom
Design
< 20MHz <30MHZ < 20MHz < 30MHz
2.5V
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Off
Note:
9. Parameters are guaranteed by design and characterization. Not 100% tested in production.
10. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz with a down
spread of –0.5%.
11. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = tWH/tC,
where the cycle time (tC) decreases as the frequency goes up
12. Refers to transition of non-inverting output
13. All differential input and output terminals are terminated with 120Ω/16 pF as shown in Figure 7.
14. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other.
15. Each output pair can be Three-stated via the two-line serial interface.
Document #: 38-07215 Rev. *A
Page 4 of 9
PRELIMINARY
SSTV850
Power Management
Serial Control Registers
The individual output enable/disable control of the SSTV850
allows the user to implement unique power management
schemes into the design. Outputs are three-stated when dis-
abled through the two-line interface as individual bits are set
low in Byte0 and Byte1 registers. The feedback output pair
(FBOUTT, FBOUTC) cannot be disabled via two line serial
bus. The enabling and disabling of individual outputs is done
in such a manner as to eliminate the possibility of partial “runt”
clocks.
Following the acknowledge of the Address Byte, two additional
bytes must be sent:
“Command Code” byte, and
“Byte Count” byte.
Byte0: Output Register (1 = Enable, 0 = Disable)
Bit
7
@Pup
Pin#
3, 2
Description
YT0, YC0
YT1, YC1
YT2, YC2
YT3, YC3
YT4, YC4
YT5, YC5
YT6, YC6
YT7, YC7
1
1
1
1
1
1
1
1
6
5, 6
5
10, 9
20, 19
22, 23
46, 47
44, 43
39, 40
4
3
2
1
0
Byte1: Output Register (1 = Enable, 0 = Disable)
Bit
7
@Pup
Pin#
29, 30
27, 26
Description
YT8, YC8
YT9, YC9
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
1
0
0
0
0
0
0
6
5
4
3
2
1
0
Differential Parameter Measurement Information
CLKINT
CLKINC
FBINT
FBINC
t(
)n+1
t(
)n
=
Σn1=N
t( )n
(N is large number of samples)
t(
)n
Figure 1. Static Phase Offset
Document #: 38-07215 Rev. *A
Page 5 of 9
PRELIMINARY
SSTV850
CLKINT
CLKINC
FBINT
FBINC
t
(
)
t
(
)
t
d(
t
d(
)
)
t
t
d(
d( )
)
Figure 2. Dynamic Phase Offset
YT[0:9], FBOUTT
YC[0:9], FBOUTC
YT[0:9], FBOUTT
YC[0:9], FBOUTC
tsk(o)
Figure 3. Output Skew
YT[0:9], FBOUTT
YC[0:9], FBOUTC
t
c(n)
YT[0:9], FBOUTT
CYC[0:9], FBOUTC
1
f(o)
t
= t
c(n)
- 1
fo
jit(hper)
Figure 4. Period Jitter
Document #: 38-07215 Rev. *A
Page 6 of 9
PRELIMINARY
SSTV850
YT[0:9], FBOUTT
YC[0:9], FBOUTC
t
t
(hper_N+1)
(hper_n)
1
f(o)
t
= t
- 1
2x fo
jit(hper)
hper(n)
Figure 5. Half-Period Jitter
YT[0:9], FBOUTT
YC[0:9], FBOUTC
t c(n)
t c(n)
tj
= t -t
c(n) c(n+1)
it(cc)
Figure 6. Cycle-to-Cycle Jitter
VDD
VDD
VDD/2
16pF
VTR
60 O hm
C LKT
C LKC
RT = 120 O hm
VCP
60 O hm
Receiver
16pF
VDD/2
Figure 7. Differential Signal Using Direct Termination Resistor
Document #: 38-07215 Rev. *A
Page 7 of 9
PRELIMINARY
SSTV850
Ordering Information
Part Number
IMISSTV850DT
IMISSTV850DTT
Package Type
Product Flow
48-Pin TSSOP
Commercial, 0° to 85°C
Commercial, 0° to 85°C
48-Pin TSSOP - Tape and Reel
Package Drawing and Dimensions
48 Pin TSSOP Outline Dimensions
Inches
Millimeters
C
Symbol
Min.
-
Nom.
Max.
0.047
0.006
Min. Nom. Max.
L
A
A1
A2
B
-
-
-
-
1.20
0.15
1.05
0.27
0.20
H
E
0.002
0.05
0.80
0.17
0.09
-
0.031 0.039 0.041
1.00
D
0.007
0.004
-
-
0.011
0.008
-
-
A2
A
C
D
E
a
A1
0.488 0.492 0.496 12.40 12.50 12.60
B
e
0.236 0.240 0.244
0.02 BSC
6.00
6.10
0.50 BSC
8.10
6.20
e
H
L
0.315 0.319 0.323
0.018 0.024 0.030
8.00
0.45
0°
8.20
0.75
8°
0.60
a
0°
-
8°
-
Document #: 38-07215 Rev. *A
Page 8 of 9
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
SSTV850
Revision History
Document Title: SSTV850 Differential Clock Buffer/Driver
Document Number: 38-07215
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
110402
112824
Description of Change
12/07/01
04/03/02
DMG
BSS
New data sheet
Obsolete Part. Data sheet is being deleted.
*A
Document #: 38-07215 Rev. *A
Page 9 of 9
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