IMIXG571CTB [ROCHESTER]
66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48, TSSOP-48;
| 型号： | IMIXG571CTB |
| 厂家： | 
Rochester Electronics |
| 描述： | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48, TSSOP-48 光电二极管 |
| 文件： | 总17页 (文件大小：797K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XG571C
I2C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology
for Pentium Processor Based Designs.
Approved Product
Frequency Table
Product Features
SEL
CPU
PCI
30.0
33.3*
•
Supports Pentium and Pentium Pro and Mobil
Pentium Processor designs.
0
60.0
1
66.6*
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
4 CPU clocks up to 8 loads.
*Spread Spectrum mode capable
Up to 8 SDRAM clocks for 2 DIMMs.
Supports Power Management.
7 PCI synchronous clocks.
Optional common or mixed supply mode:
(Vdd = Vddq3 = Vddq2 = 3.3V) or
(Vdd = Vddq3 = 3.3V, Vddq2 = 2.5V)
< 250ps skew CPU and SDRAM clocks.
< 250ps skew among PCI clocks.
I2C 2-Wire serial interface
Programmable registers featuring:
enable/disable each output pin
mode as tri-state, test, or normal
24/48 MHz selections
1 IOAPIC clock for multiprocessor support.
48-pin SSOP and TSSOP package
Spread Spectrum Technology for up to 13dB of
EMI reduction
Pin Configuration
IMIXG571
48
REF1
REF0
1
Vdd
2
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF2
Vss
3
Vddq2
IOAPIC0
Xin
4
Xout
5
PWR_DWN#
Vss
6
MODE
Vddq3
7
CPUCLK0
CPUCLK1
Vddq2
PCICLK_F
PCICLK0
Vss
8
9
10
11
12
13
14
15
16
17
18
19
20
CPUCLK2
PCICLK1
PCICLK2
PCICLK3
PCICLK4
Vddq3
CPUCLK3
Vss
Block Diagram
SDRAM0
SDRAM1
Vddq3
Buffers
3
REF0,1,2
IOAPIC0
Xin
REF
OSC
Vddq2
Xout
PCICLK5
Vss
SDRAM2
SDRAM3
Vss
Buffer
Vddq2
Vddq3
SDATA
SDCLK
4
CPUCLK0~3
Buffers
SEL
8
6
SDRAM0~7
PCICLK0~5
SDATA
SDCLK
Vddq3
SDRAM4
SDRAM5
Vddq3
Buffers
Buffers
SEL
PLL1
dly
21
22
23
24
PCI_STOP#
CPU_STOP#
PWR_DWN#
MODE
PCICLK_F
Buffer
48/24MHZ
48/24MHZ
Vss
SDRAM6/CPU_STOP#
SDRAM7/PCI_STOP#
Vdd
Buffer
Buffer
48/24MHZ
48/24MHZ
PLL2
Purchase of I2C components of International Microcircuits, Inc. or one
of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system,
provided that the system conforms to the I2C Standard Specification
as defined by Philips.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.8
10/22/1999
Page 1 of 16
XG571C
I2C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology
for Pentium Processor Based Designs.
Approved Product
Pin Description
Xin, Xout - These pins form an on-chip reference
oscillator when connected to terminals of an external
parallel resonant crystal (nominally 14.318 MHz). Xin
may also serve as input for an externally generated
reference signal.
PCICLK_F - A PCI clock output that does not stop until
in power down mode. It is synchronous with other PCI
clocks.
REF(0:2) - Buffered outputs of on-chip reference.
SEL - Standard frequency select input. It has internal
pull-up.
IOAPIC0
-
Buffered output of 14.3MHZ for
multiprocessor support. It is powered by Vddq2.
PWR_DWN# - Power down pin. When this pin is
asserted low, the IC is in shutdown mode where all
circuitry is turned off including VCO, crystal buffer and
PCICLK_F. It has an internal pull-up. The I2C interface
is disabled with the PWR_DWN# pin is low.
CPUCLK(0:3) - Low skew (<250 pS) clock outputs for
host frequencies such as CPU, Chipset, Cache. Vddq2
is the supply voltage for these outputs.
SDRAM(0:5) - Synchronous DRAM DIMs clocks. They
are powered by Vddq3.
48/24MHz(0:1) - Programmable 48 MHZ or 24 MHZ
clock outputs.
SDRAM6/CPU_STOP# - If MODE=1, this pin is a
Synchronous DRAM DIMs clock output powered by
Vddq3. If MODE=0, this pin is a CPU_STOP# input
signal, where a low level stops the CPU however, the
SDRAM clocks will stay active. It has an internal pull-
up.
SDATA - serial data of I2C 2-wire control interface. Has
internal pull-up resistor.
SDCLK - serial clock of I2C 2-wire control interface.
Has internal pull-up resistor.
SDRAM7/PCI_STOP# - If MODE=1, this pin is a
Synchronous DRAM DIMs clock output powered by
Vddq3. If MODE=0, this pin is a PCI_STOP# input
signal, where a low level stops the PCI clocks. It has an
internal pull-up.
Vss - Ground pins for the chip.
Vdd - 3.3 Volt power supply pins for analog circuit and
core logic.
Vddq3 - Power supply pins for 3.3V IO pins.
MODE - A low level on this pin causes pins 26, and 27
to be power management inputs PCI_STOP#, and
CPU_STOP# respectly. A high level on this pin causes
pins 26, and 27 to be clock output signals SDRAM7,
and SDRAM6 respectively. It has an internal pull-up
resistor.
Vddq2 - Power supply pins for 2.5V/3.3V IO pins.
PCICLK(0:5) - Low skew (<250pS) clock outputs for
PCI frequencies.
These buffers voltage level is
controlled by Vddq3
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.8
10/22/1999
Page 2 of 16
XG571C
I2C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology
for Pentium Processor Based Designs.
Approved Product
Power Management Functions
All clocks can be individually enabled or stopped via the 2-wire control interface. All clocks are stopped in the low state.
All clocks maintain a valid high period on transitions from running to stopped and on transitions from stopped to running
when the chip was not powered down. On power up, the VCOs will stabilize to the correct pulse widths within about 0.2
mS. The CPU, SDRAM, and PCI clocks transition between running and stopped by waiting for one positive edge on
PCICLK_F followed by a negative edge on the clock of interest, after which high levels of the output are either enabled
or disabled.
When MODE=0, pins 26 and 27 are inputs PCI_STOP# and CPU_STOP# respectively (when MODE=1, these functions
are not available). A particular output is enabled only when both the serial interface and these pins indicate that it should
be enabled. The IMIXG571 clocks may be disabled according to the following table in order to reduce power
consumption. All clocks are stopped in the low state. All clocks maintain a valid high period on transitions from running
to stopped. On low to high transitions of PWR_DWN#, external circuitry should allow 0.2 mS for the VCOs to stabilize
prior to assuming the clock periods are correct. The CPU and PCI clocks transition between running and stopped by
waiting for one positive edge on PCICLK_F followed by a negative edge on the clock of interest, after which high levels
of the output are either enabled or disabled.
CPU_STOP#
PCI_STOP#
PWR_DWN#
CPUCLK
PCICLK
OTHER CLKs XTAL & VCOs
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
LOW
LOW
LOW
LOW
LOW
33/30 MHZ
LOW
LOW
OFF
RUNNING
RUNNING
RUNNING
RUNNING
RUNNING
RUNNING
RUNNING
RUNNING
66/60 MHZ
66/60 MHZ
33/30 MHZ
Power Management Timing
PCICLK_F
PCI_STOP#
PCICLK(0:5)
CPU_STOP#
CPUCLK(0:3)
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.8
10/22/1999
Page 3 of 16
XG571C
I2C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology
for Pentium Processor Based Designs.
Approved Product
2-Wire I2C Control Interface
The 2-wire control interface implements a write only slave interface. The IMIXG571 cannot be read back. Sub-
addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2-
wire control interface allows each clock output to be individually enabled or disabled. It also allows 24/48 MHZ frequency
selection and test mode enable.
During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK
is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to indicate the
start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer
cycle is a 7-bit address with a Read/Write bit as the LSB. Data is transferred MSB first.
The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal on
the SDATA wire following reception of each byte. The device will not respond to any other control interface conditions.
The I2C interface is disabled when the PWR_DWN# pin is low. Previously set control registers are retained.
Serial Control Registers
NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true
power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is activated.
Following the acknowledge of the Address Byte (D2), two additional bytes must be sent:
1) “Command Code “ byte, and
2) “Byte Count” byte.
Although the data (bits) in these two bytes are considered “don’t care”, they must be sent and will be acknowledged.
Byte 0: Function Select Register
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
*
*
*
*
Description
Reserved
Reserved
Reserved
0
0
0
0
1
1
0
0
Reserved
23
22
48/24 Mhz (a”1” sets the output to 48MHz, a “0” sets the output to 24MHz)
48/24 Mhz (a”1” sets the output to 48MHz, a “0” sets the output to 24MHz)
Bit1 Bit0
1
1
0
0
1 Tri-State
0 Spread Spectrum operating mode
1 Test Mode
0
Normal operating mode
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.8
10/22/1999
Page 4 of 16
XG571C
I2C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology
for Pentium Processor Based Designs.
Approved Product
Serial Control Registers (Cont.)
Function Table
Function
Description
Tri-State
Test Mode
Normal SEL=1
Normal SEL=0
Outputs
Ref
Hi-Z
Tclk
14.318
14.318
CPU
Hi-Z
Tclk/2
66
PCI
Hi-Z
Tclk/4
CPU/2
CPU/2
SDRAM
Hi-Z
Tclk/2
CPU
IOAPIC
Hi-Z
Tclk
14.318
14.318
24MHZ
Hi-Z
Tclk/4
24
48MHZ
Hi-Z
Tclk/2
48
60
CPU
24
48
Notes:
1. Tclk is a test clock over driven on the Xin input during test mode.
2. The frequency ratio Fout/Fin for the USB output is 3.35294.
Byte 1: CPU, 48/24 MHz Clock Register (1 = enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
23
22
-
Description
1
1
x
x
1
1
1
1
48/24 MHz enable/Stopped
48/24 MHz enable/Stopped
Reserved
-
Reserved
38
39
41
42
CPUCLK3 enable/Stopped
CPUCLK2 enable/Stopped
CPUCLK1 enable/Stopped
CPUCLK0 enable/Stopped
Byte 2: PCI Clock Register (1 = enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
-
8
16
14
13
12
11
9
Description
Reserved
x
1
1
1
1
1
1
1
PCICLK_F enable/Stopped
PCICLK5 enable/Stopped
PCICLK4 enable/Stopped
PCICLK3 enable/Stopped
PCICLK2 enable/Stopped
PCICLK1 enable/Stopped
PCICLK0 enable/Stopped
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.8
10/22/1999
Page 5 of 16
XG571C
I2C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology
for Pentium Processor Based Designs.
Approved Product
Serial Control Registers (Cont.)
Byte 3: SDRAM Clock Register (1 = enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
26
27
29
30
32
33
35
36
Description
1
1
1
1
1
1
1
1
SDRAM7 enable/Stopped
SDRAM6 enable/Stopped
SDRAM5 enable/Stopped
SDRAM4 enable/Stopped
SDRAM3 enable/Stopped
SDRAM2 enable/Stopped
SDRAM1 enable/Stopped
SDRAM0 enable/Stopped
Byte 4: Additional SDRAM Clock Register (1 = enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
x
x
x
x
x
x
x
x
-
-
-
-
-
-
-
-
Byte 5: Peripheral Control (1 = enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
-
-
-
45
-
47
1
2
Description
Reserved
Reserved
Reserved
IOAPIC0 enable/Stopped
Reserved
REF2 enable/Stopped
REF1 enable/Stopped
REF0 enable/Stopped
x
x
1
1
x
1
1
1
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.8
10/22/1999
Page 6 of 16
XG571C
I2C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology
for Pentium Processor Based Designs.
Approved Product
Serial Control Registers (Cont.)
Byte 6: Reserved Register
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
x
x
x
x
x
x
x
x
-
-
-
-
-
-
-
-
Byte 7: Frequency Control
Bit
7
6
5
4
3
2
1
0
@Pup
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
x
x
x
x
x
1
x
x
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.8
10/22/1999
Page 7 of 16
XG571C
I2C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology
for Pentium Processor Based Designs.
Approved Product
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique applied here for maximum efficiency in minimizing Electro-Magnetic
Interference radiation generated from repetitive digital signals mainly clocks. A clock accumulates EM energy at the
center frequency it is generating. Spread Spectrum distributes this energy over a small frequency bandwidth therefore
spreading the same amount of energy over a spectrum. This technique is achieved by modulating the clock down from
its resting frequency by a certain percentage (which also determines the energy distribution bandwidth). In this product,
the modulation is 1.0% down from the resting frequency.
Amplitude
(dB)
Without Spectrum Spread
With Spectrum Spread
Frequency(MHz)
Modulated Center
Frequency
Rested Center
frequency
Spectrum Analysis
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.8
10/22/1999
Page 8 of 16
XG571C
I2C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology
for Pentium Processor Based Designs.
Approved Product
Maximum Ratings
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
Voltage Relative to VSS:
Voltage Relative to VDD:
Storage Temperature:
Operating Temperature:
Maximum Power Supply:
-0.3V
0.3V
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
-65ºC to + 150ºC
0ºC to +70ºC
7V
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
Electrical Characteristics
Characteristic
Symbol Min
Typ
Max
0.8
Units
Vdc
Vdc
µA
Conditions
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
VIL
VIH
IIL
-
-
-
-
-
2.0
-
-66
5
IIH
µA
Output Low Voltage
IOL = 4mA
VOL
-
-
-
0.4
Vdc
All Outputs (see buffer spec)
Output High Voltage
IOH = 4mA
VOH
2.4
-
Vdc
All Outputs Using 3.3V Power
(see buffer spec)
Tri-State leakage Current
Dynamic Supply Current
Static Supply Current
Short Circuit Current
Ioz
Idd
-
-
-
-
-
-
10
100
1
µA
mA
mA
mA
CPU = 66.6 MHz, PCI = 33.3 MHz
Powered Down = Active
Isdd
ISC
-
25
-
1 output at a time - 30 seconds
VDD = VDDQ3 =3.3V ±5%, VDDQ2 = 2.5V±5% , TA = 0ºC to +70ºC
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.8
10/22/1999
Page 9 of 16
XG571C
I2C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology
for Pentium Processor Based Designs.
Approved Product
Switching Characteristics
Characteristic
Symbol
-
Min
45
1
Typ
Max
55
Units
%
Conditions
Measured at 1.5V
Output Duty Cycle
CPU to PCI Offset
50
-
tOFF
tSKEW
4
ns
15 pf Load Measured at 1.5V
15 pf Load Measured at 1.5V
Buffer out Skew All CPU
and PCI Buffer Outputs
-
-
250
ps
-
-
-
+250
500
ps
-
∆Period Adjacent Cycles
∆P
Jitter Spectrum 20 dB
Bandwidth from Center
BWJ
KHz
Overshoot/Undershoot
Beyond Power Rails
Vover
-
1.5
V
22 ohms @ source of 8 inch PCB run
to 15 pf load
Ring Back Exclusion
VRBE
0.7
2.1
V
Note1
VDD = VDDQ3 =3.3V ±5%, VDDQ2 = 2.5V±5% , TA = 0ºC to +70ºC
Note 1: Ring Back must not enter this range.
Buffer Characteristics for CPUCLK(0:3), IOAPIC
Characteristic
Symbol
IOH
Min
22
Typ
Max
31
56
41
102
-
Units
mA
mA
mA
mA
nS
Conditions
Vout = VDD - .5V
Pull-Up Current
Pull-Up Current
Pull-Down Current
Pull-Down Current
-
-
-
-
-
IOH
37
Vout = 1.25V
Vout = 0.4V
Vout = 1.2V
10 pF Load
IOL
30
IOL
75
Rise/Fall Time Min
TRFmin
0.4
Between 0.4 V and 2.0 V
Rise/Fall Time Max
TRFmax
-
-
2.0
nS
20 pF Load
Between 0.4 V and 2.0 V
VDD = VDDQ3 =3.3V ±5%, VDDQ2 = 2.5V±5% , TA = 0ºC to +70ºC
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.8
10/22/1999
Page 10 of 16
XG571C
I2C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology
for Pentium Processor Based Designs.
Approved Product
Buffer Characteristics for REF(1:2) and 48/24 MHz
Characteristic
Symbol
IOH
Min
13
30
13
32
1.0
-
Typ
Max Units Conditions
Pull-Up Current
-
-
-
-
-
-
17
44
19
44
-
mA
mA
mA
mA
nS
Vout = VDD - .5V
Vout = 1.5V
Vout = 0.4V
Vout = 1.5V
10 pF Load
Pull-Up Current
IOH
Pull-Down Current
IOL
Pull-Down Current
IOL
Rise/Fall Time Min Between 0.4 V and 2.4 V
Rise/Fall Time Max Between 0.4 V and 2.4 V
TRFmin
TRFmax
2.0
nS
20 pF Load
VDD = VDDQ3 =3.3V ±5%, VDDQ2 = 2.5V±5% , TA = 0ºC to +70ºC
Buffer Characteristics for REF0 and SDRAM(0:7)
Characteristic
Symbol
IOH
Min
30
75
30
75
0.5
-
Typ
Max Units Conditions
Pull-Up Current
-
-
-
-
-
-
39
109
40
mA
mA
mA
mA
nS
Vout = VDD - .5V
Vout = 1.5V
Vout = 0.4V
Vout = 1.2V
20 pF Load
Pull-Up Current
IOH
Pull-Down Current
IOL
Pull-Down Current
IOL
103
-
Rise/Fall Time Min Between 0.4 V and 2.4 V
Rise/Fall Time Max Between 0.4 V and 2.4 V
TRFmin
TRFmax
2.0
nS
30 pF Load
VDD = VDDQ3 =3.3V ±5%, VDDQ2 = 2.5V±5% , TA = 0ºC to +70ºC
Buffer Characteristics for PCICLK(0:5,F)
Characteristic
Symbol
IOH
Min
18
44
18
50
0.5
-
Typ
Max Units Conditions
Pull-Up Current
-
-
-
-
-
-
23
64
25
70
-
mA
mA
mA
mA
nS
Vout = VDD - .5V
Vout = 1.5V
Vout = 0.4V
Vout = 1.5V
15 pF Load
Pull-Up Current
IOH
Pull-Down Current
IOL
Pull-Down Current
IOL
Rise/Fall Time Min Between 0.4 V and 2.4 V
Rise/Fall Time Max Between 0.4 V and 2.4 V
TRFmin
TRFmax
2.0
nS
30 pF Load
VDD = VDDQ3 =3.3V ±5%, VDDQ2 = 2.5V±5% , TA = 0ºC to +70ºC
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.8
10/22/1999
Page 11 of 16
XG571C
I2C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology
for Pentium Processor Based Designs.
Approved Product
Crystal and Reference Oscillator Parameters
Characteristic
Frequency
Symbol
Fo
Min
Typ
Max
16.00
+/-100
+/- 100
5
Units
MHz
PPM
PPM
PPM
Conditions
12.00
14.31818
Tolerence
TC
-
-
-
-
-
-
Calibration note 1
TS
Stability (Ta -10 to +60C) note 1
Aging (first year @ 25C) note 1
Parallell Resonant
TA
-
Mode
OM
CP
-
-
Pin Capacitance
6
pF
Capacitance of XIN and Xout pins to
ground (each)
DC Bias Voltage
Startup time
VBIAS
Ts
0.3Vdd
Vdd/2
0.7Vdd
V
µS
-
-
-
-
20
-
30
-
Load Capacitance
CL
pF
The crystal’s rated load. Note 1
Effective Series
resonant
R1
40
Ohms
resistance
Power Dissipation
Shunt Capacitance
DL
-
-
-
0.10
8
mW
pF
Note 1
CO
--
Crystal’s internal package
capacitance (total)
For maximum accuracy, the total circuit loading capacitance should be equal to CL. This loading capacitance is the
effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit
traces, the clock generator and any onboard discrete load capacitors.
Budgeting Calculations
Typical trace capacitance, (< half inch) is 4 pF, Load to the crystal is therefore
Clock generator internal pin capacitance of 36 pF, Load to the crystal is therefore
External crystal loading capacitors (connect to ground)
2.0 pF
3.0 pF
15.0 pF
the total parasitic capacitance would therefore be
= 20.0.0 pF.
Note 1: It is recommended but not mandatory that a crystal meets these specifications.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.8
10/22/1999
Page 12 of 16
XG571C
I2C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology
for Pentium Processor Based Designs.
Approved Product
PCB Layout Suggestion
Via to VDD Island
Via to GND plane
IMIXG571
VCC3.3V
FB1
C12
48
1
47
2
C11
46
45
3
4
C3
22µF
44
43
42
41
40
VCC2.5V
5
6
FB2
C4
7
8
C10
C9
9
39
38
37
36
35
10
11
12
13
14
C14
22µF
C5
C6
34
15
33
32
31
30
29
16
17
18
19
20
C8
C7
28
27
26
21
22
23
24
25
This is only a layout recommendation for best performance and lower EMI. The designer may choose a
different approach but C4, C5, C6, C7, C8, C9, C10, C11and C12 (all are 0.1µf) should always be used and
placed close to their VDD pins.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.8
10/22/1999
Page 13 of 16
XG571C
I2C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology
for Pentium Processor Based Designs.
Approved Product
Package Drawing and Dimensions
48 Pin SSOP Outline Dimensions
INCHES
NOM
0.102
0.012
0.090
0.010
-
MILLIMETERS
SYMBOL
MIN
MAX
MIN
2.41
0.20
2.24
NOM
2.59
0.31
2.29
MAX
A
A1
A2
B
0.095
0.008
0.088
0.008
0.005
0.620
0.292
0.110
0.016
0.092
0.0135
0.010
0.630
0.299
2.79
0.41
2.34
C
L
0.203 0.254 0.343
0.127 0.254
15.75 15.88 16.00
H
E
C
D
E
-
0.625
0.296
0.025 BSC
0.406
0.013
0.032
5º
7.42
7.52
7.59
e
0.635 BSC
D
H
a
0.400
0.10
0.024
0º
0.410
0.016
0.040
8º
10.16 10.31 10.41
a
0.25
0.61
0º
0.33
0.81
5º
0.41
1.02
8º
A2
A
L
a
A1
X
0.085
0.093
0.100
2.16
2.36
2.54
e
B
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.8
10/22/1999
Page 14 of 16
XG571C
I2C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology
for Pentium Processor Based Designs.
Approved Product
Package Drawing and Dimensions (Cont.)
48 Pin TSSOP Dimensions
D
INCHES
MILLIMETERS
R0.1
SYMBOL
A
MIN
-
NOM
MAX
MIN
-
NOM
-
MAX
-
0.004
0.035
0.023
-
0.0433
1.10
0.15
0.95
0.75
-
A1
A2
L
0.002
0.033
0.019
0.043
0.006
0.006
0.004
0.004
0°
0.006
0.037
0.029
-
0.05
0.85
0.10
0.90
0.60
-
E1
BO
L20
0.50
R
0.10
-B-
b
-
0.010
0.009
0.007
0.006
8°
0.170
0.170
0.105
-
0.27
0.225
0.175
385
SURFACES ROUGHNESS: 6+ 27n(RZ)
b1
c
0.008
-
0.20
-
4
RD
[10° TYP
c1
θ
0.005
-
0.105 0.125 0.145
-C-
0.07
C
B
e
e
0.020 BSC
0.492
0.319
0.240
0.50 BSC
R1.30
1.0
D
0.488
0.313
0.236
0.496
0.325
0.244
12.40 12.50 12.60
0.00
~ 0.05
0.10~0.15
E
7.95
6.00
8.1
6.1
8.25
6.20
E1
SECTION V-V
R0.15
14 TYP
°
1.0
0.05 MAX.
1.0
0.05 MAX.
A
E
b
.08
C
B
A
8
°
R
A
A2
c
c1
0.25
L
b1
A1
DETAIL A
DETAIL B
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.8
10/22/1999
Page 15 of 16
XG571C
I2C Frequency Clock Generator w/ EMI Reduction Spread Spectrum Technology
for Pentium Processor Based Designs.
Approved Product
Ordering Information
Part Number
IMIXG571CYB
IMIXG571CTB
Package Type
48 PIN SSOP
48 PIN TSSOP
Production Flow
Commercial, 0ºC to +70ºC
Commercial, 0ºC to +70ºC
Note:
The ordering part number is formed by a combination of device number, device revision, package style, and
screening as shown below.
Marking: Example: IMI
XG571CYB
Date Code, Lot #
IMIXG571CYB
Flow
B = Commercial, 0ºC to + 70ºC
Package
Y = SSOP
T = TSSOP
Revision
IMI Device Number
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.8
10/22/1999
Page 16 of 16
相关型号：
IMIZ9104DAB
PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32
CYPRESS
IMIZ9104DABT
PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32
CYPRESS
©2020 ICPDF网 联系我们和版权申明