IMIZ9952 [ETC]

Clocks and Buffers ; 时钟和缓冲器\n


型号：	IMIZ9952
厂家：	ETC
描述：	Clocks and Buffers 时钟和缓冲器\n 时钟
文件：	总9页 (文件大小：49K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Z9952

3.3V, 180MHz, Multi-Output Zero Delay Buffer

Product Features

Frequency Table

VCO_SEL SEL (A:C) QA(0:4) QB(0:3) QC (0,1)

•

180MHz Clock Support

000

001

010

011

100

101

110

111

000

001

010

011

100

101

110

111

VCO/4

VCO/6

VCO/8

VCO/12

VCO/4

VCO/2

VCO/4

VCO/2

VCO/8

VCO/4

VCO/8

VCO/4

VCO/2

VCO/4

VCO/2

VCO/4

VCO/2

VCO/4

VCO/2

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

150ps Maximum Output to Output Skew

Supports PowerPC^TM, Intel and RISC Processors

11 Clock Outputs: Frequency Configurable

Outputs Drive up to 22 Clock Lines

LVCMOS/LVTTL Compatible Inputs

Output Tri-state Control

Spread Spectrum Compatible

3.3V Power Supply

Pin Compatible with MPC952

Industrial Temp. Range: -40°C to +85°C

32-Pin TQFP Package

Block Diagram

PLL_EN#

VCO/12

Table 1

REFCLK

QA0

Phase

Detector

VCO

200-480M

/4,

QA1

QA2

QA3

QA4

FB_IN

Pin Configuration

LPF

VCO_SEL

SELA

/4,

QB0

QB1

SELB

QB2

QB3

VCO_SEL

SELC

SELB

VSS

QB1

QB0

VDDC

SELA

MR/OE#

REFCLK

VSS

Z9952 20 VDDC

/2,

QC0

QC1

QA4

QA3

VSS

FB_IN

SELC

MR/OE#

Figure 1

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07085 Rev. *B

12/22/2002

Page 1 of 9

Z9952

3.3V, 180MHz, Multi-Output Zero Delay Buffer

Pin Description

NAME

REFCLK

QA(0:4)

PWR

I/O

Description

External Test Clock Input.

Clock Output. See Frequency Table.

12, 14, 15,

VDDC

18, 19

22, 23, 26, 27

30, 31

VDDC

Clock Output. See Frequency Table.

Clock Outputs. See Frequency Table.

Feedback Clock Input. Connect to an output for normal operation.

QB(0:3)

QC(0,1)

FB_IN

I, PD

VCO Divider Select Input. When set high, the VCO output is

divided by 2. When set low, the divider is bypassed. See

Table 1

VCO_SEL

I, PD

Master Reset/Output Enable Input. When asserted high,

resets all of the internal flip-flops and also disables all of the

outputs. When pulled low, releases the internal flip-flops from

reset and enables all of the outputs.

MR/OE#

PLL Enable Input. When asserted low, PLL is enabled. And

when set high, PLL is bypassed.

Frequency Select Inputs. See Frequency Table.

If SEL_ = 0, then QA, QB divider = ÷4, QC divider = ÷2

If SEL_ = 1, then QA divider = ÷6, QB divider = ÷2, QC divider

= ÷4

PLL_EN#

SEL(C:A)

2, 3, 4

I, PD

16, 20, 21,

25, 32

3.3V Power Supply for Output Clock Buffers.

VDDC

3.3V Power Supply for PLL

3.3V Power Supply for Core Logic

Common Ground

VDDA

VDD

VSS

7, 13, 17, 24,

28, 29

PD = Internal Pull-Down

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07085 Rev. *B

12/22/2002

Page 2 of 9

Z9952

3.3V, 180MHz, Multi-Output Zero Delay Buffer

Maximum Ratings¹

This device contains circuitry to protect the inputs

against damage due to high static voltages or electric

field; however, precautions should be taken to avoid

application of any voltage higher than the maximum

rated voltages to this circuit. For proper operation, Vin

and Vout should be constrained to the range:

Maximum Input Voltage Relative to VSS: VSS - 0.3V

Maximum Input Voltage Relative to VDD: VDD + 0.3V

Storage Temperature:

Operating Temperature:

Maximum ESD protection

-65°C to + 150°C

-40°C to +85°C

2KV

VSS<(Vin or Vout)<VDD

Maximum Power Supply:

Maximum Input Current:

5.5V

±20mA

Unused inputs must always be tied to an appropriate

logic voltage level (either VSS or VDD).

DC Parameters

Characteristic

Symbol Min

Typ

Max

0.8

Units

Conditions

Input Low Voltage

VIL

VIH

IIL

VSS

2.0

Input High Voltage

VDD

Input Low Current (@VIL = VSS)

Input High Current (@VIL =VDD)

Output Low Voltage

µA

Note 2

IIH

120

0.5

VOL

VOH

IDDC

IDD

Cin

IOL = 20mA, Note 3

IOH = -20mA, Note 3

All VDDC, VDDA, and VDD

VDDA only

Output High Voltage

Quiescent Supply Current

PLL Supply Current

2.4

Input Capacitance

VDDA = VDD = VDDC = 3.3V ±5%, TA = -40°C to +85°C

Note 1: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is

NOT required.

Note 2: Inputs have internal pull-down resistors that affect input current.

Note 3: Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines.

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07085 Rev. *B

12/22/2002

Page 3 of 9

Z9952

3.3V, 180MHz, Multi-Output Zero Delay Buffer

AC Parameters¹

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

CONDITIONS

Freq

Fvco

Tlock

Tr / Tf

Fout

Reference Input Frequency

PLL VCO Lock Range

Note 2

200

Note 2

480

MHz

Maximum PLL lock Time

Output Clocks Rise / Fall Time^4,5

0.10

1.0

0.8V to 2.0V

QB, QC = (÷2)

QA, QB, QC = (÷4)

QA = (÷6)

Maximum Output Frequency

180

120

MHz

FoutDC

Output Duty Cycle^4,5

TCYCLE/2 –

750

TCYCLE/2 +

750

tpZL, tpZH

tpLZ, tpHZ

TCCJ

Output enable time (all outputs)

Output disable time (all outputs)

Cycle to Cycle Jitter (peak to peak)⁵

REFCLK to FB_IN Delay^3,,4,5

+/- 100

Tpd

-200

200

150

250

TSKEW0

Any Output to Any Output Skew^4,5

Same frequencies

Different frequencies

VDDA = VDD = VDDC = 3.3V +/- 5%, TA = -40°C to +85°C

Note 1: Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with

loaded outputs.

Note 2: Maximum and minimum input reference is limited by the VCO lock range.

Note 3: The Tpd window is specified for a 50MHz input reference clock. The window will enlarge/reduce proportionally from the

minimum limits with an increase/decrease of the input reference clock period.

Note 4: Driving series or parallel terminator 50Ω (or 50Ω to VDD/2).

Note 5: Outputs loaded with 30pF each

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07085 Rev. *B

12/22/2002

Page 4 of 9

Z9952

3.3V, 180MHz, Multi-Output Zero Delay Buffer

Description

The Z9952 has an integrated PLL that provides low skew and low jitter clock outputs for high performance

microprocessors. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 480

MHz. This allows a wide range of output frequencies up to 180MHz. The Z9952 features three banks of individually

configurable outputs: Bank A five outputs, Bank B four outputs, and Bank C two outputs. When MR/OE# input is set

high, all the outputs are tri-stated. The Z9952 outputs are LVCMOS compatible and can drive two series terminated 50Ω

transmission lines. With this capability the Z9952 has an effective fanout of 1:22. Low output-to-output skews make the

Z9952 ideal for clock distribution in nested clock trees in the most demanding of synchronous systems.

The phase detector compares the input reference clock to the external feedback input. For normal operation, the

external feedback input, FB_IN, is connected to one of the outputs. The internal VCO is running at multiples of the input

reference clock set by SEL(A:C) select inputs, see Table 2. The VCO_SEL input allows for the choice of two VCO

ranges to optimize PLL stability and jitter performance, see Table 1. The VCO frequency is then divided down to provide

the required output frequencies. The use of even dividers ensures that the output duty cycle remains at 50%.

SELA

SELB

SELC

÷4

÷6

÷4

÷2

÷4

Table 2

Zero Delay Buffer

When used as a zero delay buffer the Z9952 will likely be in a nested clock tree application. Any of the eleven outputs

can be used as the feedback to the PLL. By using one of the outputs as a feedback to the PLL the propagation delay

through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a

near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between

the inputs and outputs. Because the static phase offset is a function of the reference clock the Tpd of the Z9952 is a

function of the configuration used.

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07085 Rev. *B

12/22/2002

Page 5 of 9

Z9952

3.3V, 180MHz, Multi-Output Zero Delay Buffer

Package Drawing and Dimensions

32 Pin TQFP Outline Dimensions

INCHES

MILLIMETERS

SYMBOL

MIN

NOM

MAX

0.047

0.006

0.041

MIN

NOM

MAX

A₁

1.20

0.15

1.05

0.002

0.037

0.05

0.95

0.354

9.00

D₁

0.276

7.00

0.012

0.018

0.30

0.45

D₁

0.031 BSC

0.80 BSC

12°

0.018

0.030

0.45

0.75

A₁

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07085 Rev. *B

12/22/2002

Page 6 of 9

Z9952

3.3V, 180MHz, Multi-Output Zero Delay Buffer

Ordering Information

Part Number

Package Type

Production Flow

Z9952AA

32 PIN TQFP

Industrial, -40°C to +85°C

Note:

The ordering part number is formed by a combination of device number, device revision, package style, and

screening as shown below.

Marking: Example: Cypress

Z9952AA

Date Code, Lot #

Z9952AA

Package

A = TQFP

Revision

IMI Device Number

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07085 Rev. *B

12/22/2002

Page 7 of 9

Z9952

3.3V, 180MHz, Multi-Output Zero Delay Buffer

Notice

Cypress Semiconductor Corporation reserves the right to make changes to its products in order to improve design,

performance or reliability. Cypress Semiconductor Corporation assumes no responsibility for the use of its products in

life supporting and medical applications where the failure or malfunction of the product could cause failure of the life

supporting and medical systems. Products are not authorized for use in such applications unless a written approval is

requested by the manufacturer and an approval is given in writing Cypress Semiconductor Corporation for the use of its

products in the life supporting and medical applications.

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07085 Rev. *B

12/22/2002

Page 8 of 9

Z9952

3.3V, 180MHz, Multi-Output Zero Delay Buffer

Document Title: Z9952 3.3V, 180 MHz Multi-Output Zero Delay Buffer

Document Number: 38-07085

Rev. ECN

No.

Issue

Date

06/05/01

07/03/01

12/22/02

Orig. of

Change

IKA

NDP

RBI

Description of Change

107121

Convert from IMI to Cypress

Changed Commercial to Industrial

Add power up requirements to maximum ratings

information

108064

122770

Cypress Semiconductor Corporation

http://www.cypress.com

Document#: 38-07085 Rev. *B

12/22/2002

Page 9 of 9

IMIZ9952 [ETC]

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