IMIZ9960AL [CYPRESS]
2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer; 2.5V / 3.3V ， 200 MHz的多输出零延迟缓冲器
| 型号： | IMIZ9960AL |
| 厂家： | 
CYPRESS |
| 描述： | 2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer |
| 文件： | 总7页 (文件大小：254K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Z9960
2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer
Table 1. Frequency Table[1]
F
Features
• 2.5V or 3.3V operation
B
_
• Output frequency up to 200 MHz
• Supports PowerPC, and Pentium® processors
• 21 clock outputs: drive up to 42 clock lines
• LVPECL or LVCMOS/LVTTL clock input
• Output-to-output skew < 150 ps
• Split 2.5V/3.3V outputs
S
E
L
S
E
L
S
E
L
S
E
L
A
QA
B
QB
C
QC
FB_OUT
VCO/8
VCO/12
0
VCO/2
0
VCO/2
0
VCO/2
0
1
VCO/4
1
VCO/4
1
VCO/4
1
• Spread spectrum compatible
• Glitch-free output clocks transitioning
• Output disable control
• Pin-compatible with MPC9600
• Industrial temperature range: –40°C to +85°C
• 48-pin LQFP package
Pin Configuration
Block Diagram
AVDD
A
REF_SEL
TCLK
PECL_CLK
PECL_CLK#
0
1
/2
/4
0
1
PLL
D Q
0
1
0
1
REF
FB
/8
/12
2
3
4
5
FB_IN
SELA
48 47 46 45 44 43 42 41 40 39 38 37
VSSA
FB_OUT
QB0
1
36
35
34
33
32
31
30
29
28
27
26
25
VSS
TCLK
B
6
0
1
2
0
D Q
1
3
4
PECL_CLK
QB1
PECL_CLK#
VDD
REF_SEL
FB_SEL
AVDD
2
3
4
5
SELB
SELC
VDDB
QB2
QB3
VSSB
QB4
QB5
QB6
VDDB
5
6
Z9960
7
8
6
0
1
C
9
SELA
SELB
SELC
VSSC
0
1
D Q
10
11
12
2
3
4
5
13 14 15 16 17 18 19 20 21 22 23 24
6
OE#
FB
0
1
FB_OUT
D Q
FB_SEL
Note:
1. Input frequency range: 16 MHz to 33 MHz (FB_SEL = 1), or 25 MHz to 50 MHz (FB_SEL = 0).
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-07087 Rev. *C
Revised May 03, 2004
Z9960
Pin Definition
Pin Name
PECL_CLK
PECL_CLK#
TCLK
No.
3
4
Type
I, PD
I, PU
I, PD
Pin Description
PECL Clock Input.
PECL Clock Input.
2
External Reference/Test Clock Input.
QA(6:0)
38, 39, 40, 42,
O
Clock Outputs. See Table 1 for frequency selections.
43, 45, 46
VDDA
QB(6:0)
QC(6:0)
FB_OUT
26, 27, 28, 30,
31, 33, 34
O
Clock Outputs. See Table 1 for frequency selections.
Clock Outputs. See Table 1 for frequency selections.
VDDB
15, 16, 18, 19,
O
21, 22, 23
VDDC
35
O
Feedback Clock Output. Connect to FB_IN for normal operation. The divider
ratio for this output is set by FB_SEL; see Table 1. A bypass delay capacitor at
this output will control Input Reference/ Output Banks phase relationships.
VDD
SELA
SELB
9
10
11
7
I, PU
I, PU
I, PU
I, PU
Frequency Select Inputs. These inputs select the divider ratio at QA(0:6)
outputs. See Table 1.
Frequency Select Inputs. These inputs select the divider ratio at QB(0:6)
outputs. See Table 1.
SELC
Frequency Select Inputs. These inputs select the divider ratio at QC(0:6)
outputs. See Table 1.
FB_SEL
Feedback Select Inputs. These inputs select the divide ratio at FB_OUT output.
See Table 1.
FB_IN
REF_SEL
47
6
I, PD
I, PU
Feedback Clock Input. Connect to FB_OUT for accessing the PLL.
Reference Select Input. When high, the PECL clock is selected. And when low,
TCLK is the reference clock.
OE#
14
I, PD
Output Enable Input. When asserted low, enables all of the outputs. When
pulled high, disables to high impedance all of the outputs except FB_OUT.
VDDA
VDDB
VDDC
VDD
37, 44
25, 32
13, 20
5
Power Supply for Bank A Clock Buffers.
Power Supply for Bank B Clock Buffers.
Power Supply for Bank C Clock Buffers.
Power Supply for Core
AVDD
VSSA
VSSB
VSSC
VSS
8
Power Supply for PLL. When AVDD is set low, PLL is bypassed.
Common Ground for Bank A.
Common Ground for Bank B.
Common Ground for Bank C.
Common Ground.
36, 41
24, 29
12, 17
1, 48
A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors
are not close to the pins, their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
Document #: 38-07087 Rev. *C
Page 2 of 7
Z9960
Function Table
Control Pin
REF_SEL
AVDD
OE#
SELA
SELB
SELC
FB_SEL
0
1
TCLK
PECL_CLK
PLL Power
PLL Bypass, Outputs Controlled by OE#
Outputs Enabled
Outputs Disabled (except FB_OUT)
Output Bank A at VCO/4
Output Bank B at VCO/4
Output Bank C at VCO/4
Feedback Output at VCO/12
Output Bank A at VCO/2
Output Bank B at VCO/2
Output Bank C at VCO/2
Feedback Output at VCO/8
Overview
Zero Delay Buffer
The Z9960 has an integrated PLL that provides low skew and
low jitter clock outputs for high-performance microprocessors.
Three independent banks of seven outputs as well as an
independent PLL feedback output, FB_OUT, provide excep-
tional flexibility for possible output configurations. The PLL is
ensured stable operation given that the VCO is configured to
run between 200 MHz to 400 MHz. This allows a wide range
of output frequencies up to 200 MHz.
When used as a zero delay buffer the Z9960 will likely be in a
nested clock tree application. For these applications the
Z9960 offers a low-voltage PECL clock input as a PLL
reference. This allows the user to use LVPECL as the primary
clock distribution device to take advantage of its far-superior
skew performance. The Z9960 then can lock onto the LVPECL
reference and translate with near zero delay to low skew
outputs.
The phase detector compares the input reference clock to the
external feedback input. For normal operation, the external
feedback input, FB_IN, is connected to the feedback output,
FB_OUT. The internal VCO is running at multiples of the input
reference clock set by FB_SEL select inputs; refer to Table 1.
The VCO frequency is then divided down to provide the
required output frequencies.
By using one of the outputs as a feedback to the PLL, the
propagation delay through the device is eliminated. The PLL
works to align the output edge, with the input reference edge
thus producing a near-zero delay. The reference frequency
affects the static phase offset of the PLL and thus the relative
delay between the inputs and outputs. Because the static
phase offset is a function of the reference clock, the Tpd of the
Z9960 is a function of the configuration used.
Document #: 38-07087 Rev. *C
Page 3 of 7
Z9960
Absolute Maximum Ratings[2]
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, VIN and VOUT should be constrained to
the range
Input Voltage Relative to VSS:...............................VSS – 0.3V
Input Voltage Relative to VDD: ............................. VDD + 0.3V
Storage Temperature: .................................-65°C to + 150°C
Operating Temperature:................................-40°C to + 85°C
Maximum ESD Protection................................................2kV
Maximum Power Supply: ................................................5.5V
V
< (V or V
) < V
.
SS
IN
OUT
DD
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
Maximum Input Current:..................................................± 20mA
Note:
2. The voltage on any input or I/O or pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Characteristics VDD = 2.5V ±5%, TA = –40°C to +85°C
Parameter
Description
Input Low Voltage
Input High Voltage
Test Condition
Min.
VSS
1.7
Typ.
Max.
0.7
VDD
1000
Unit
V
V
[3]
VIL
VIH
–
–
–
[3]
VPP
Peak-to-Peak Input Voltage
500
mV
PECL_CLK
VCMR[4]
Common Mode Range
PECL_CLK
Input Low Current (@ VIL = VSS
VDD –1.4
–
VDD –0.6
V
[5]
IIL
)
–
–
–
–
–120
120
µA
µA
[5]
IIH
Input High Current (@ VIH
=
VDD
)
[6]
VOL
Output Low Voltage
IOL = 15 mA
IOH = –15 mA
VDD and AVDD
–
1.8
–
–
–
10
4
0.6
V
V
mA
pF
[6]
VOH
Output High Voltage
Quiescent Supply Current
Input Pin Capacitance
IDD
CIN
13
–
–
DC Electrical Characteristics VDD = 3.3V +5%, TA = –40°C to +85°C
Parameter
Description
Input Low Voltage
Input High Voltage
Test Condition
Min.
VSS
2.0
Typ.
Max.
0.8
VDD
1000
Unit
V
V
[3]
VIL
VIH
–
–
–
[3]
VPP
Peak-to-Peak Input Voltage
500
mV
PECL_CLK
VCMR[4]
Common Mode Range PECL_CLK
Input Low Current (@ VIL = VSS
Input High Current (@ VIH = VDD
Output Low Voltage
Output High Voltage
Quiescent Supply Current
Input Pin Capacitance
VDD –1.4
–
–
–
–
–
VDD –0.6
–120
120
0.55
–
V
µA
µA
V
V
mA
pF
[5]
IIL
)
–
–
–
2.4
–
–
[5]
IIH
)
[6]
VOL
IOL = 24 mA
IOH = –24 mA
VDD and AVDD
[6]
VOH
IDD
CIN
15
4
20
–
Notes:
3. The LVCMOS inputs threshold is at 30% of V
.
DD
4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when HIGH input is within the VCMR range
and the input lies within the V specification.
PP
5. Inputs have pull-up/pull-down resistors that affect input current.
6. Driving series or parallel terminated 50Ω (or 50Ω to V /2) transmission lines.
DD
Document #: 38-07087 Rev. *C
Page 4 of 7
Z9960
AC Electrical Characteristics VDD = 2.5V ±5% or 3.3V ±5%, TA = –40°C to +85°C[7]
Symbol
Fref
Parameter
Reference Input Frequency
Test Condition
FB_SEL = 1
FB_SEL = 0
Min.
16
25
25
200
–
0.1
–
100
50
45
2
Typ.
–
–
–
–
–
–
–
–
Max.
33
50
75
400
10
1.0
–
200
100
55
Unit
MHz
FrefDC
Fvco
Tlock
Tr / Tf
Reference Input Duty Cycle
PLL VCO Lock Range
Maximum PLL lock Time
%
MHz
ms
Output Clocks Rise / Fall
0.55V to 2.0V, VDD = 3.3V
0.5V to 1.8V, VDD = 2.5V
Q (÷2)
ns
Time[8],[9]
Fout
Maximum Output Frequency
Output Duty Cycle[8],[9]
MHz
Q (÷4)
–
50
–
FoutDC
%
ns
tpZL, tpZH Output Enable Time[8] (all
outputs)
10
tpLZ, tpHZ Output Disable Time[8] (all
outputs)
2
–
8
ns
TCCJ
Tskew
Cycle to Cycle Jitter[8],[9]
Any Output to Any Output
–
–
–
–
–
±100
–
–
–
–
–
ps
ps
Same frequency
Different frequency
Banks at different voltages
150
300
400
450
200
225
Skew[8],[9]
Tskew
Tskew(pp)
Tpd
Bank to Bank Skew
Part to Part Skew[10]
ps
ps
ps
Phase
TCLK or
VDD = 3.3V
0
25
100
125
Error[8],[9]
PECL_CLK to
FB_IN
VDD = 2.5V
Note:
7. Parameters are guaranteed by design and characterization. Not 100% tested in production.
8. Outputs loaded with 30pF each.
9. 50Ω transmission line terminated into VDD/2.
10. Part to Part skew at a given temperature and voltage
Document #: 38-07087 Rev. *C
Page 5 of 7
Z9960
Ordering Information
Ordering Code
Package Name
Package Type
IMIZ9960AL
48 LQFP
Industrial, -40°C to +85°C
IMIZ9960ALT
48 LQFP - Tape and Reel
Industrial, -40°C to +85°C
Package Drawing and Dimension
48-Lead Thin Plastic Quad Flat Pack (7x7x1.4 mm) A48
51-85135-**
PowerPC is a trademark of IBM®. Pentium® is a trademark of Intel Corporation. All product or company names mentioned in this
document are the trademarks of their respective holders.
Document #: 38-07087 Rev. *C
Page 6 of 7
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Cypressproductsarenotwarrantednorintendedtobeusedformedical, life-support, life-saving, criticalcontrolorsafetyapplications, unlesspursuanttoanexpresswrittenagreementwithCypress.
Z9960
Document History
Document Title: Z9960 2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer
Document #: 38-07087 Rev. *C
Issue
Date
Orig. of
Change
Rev.
**
ECN No.
107123
108715
122772
223804
Description of Change
06/06/01
11/07/01
12/21/02
See ECN
IKA
NDP
RBI
Convert from IMI to Cypress
*A
Updated AVDD Pin Functionality.
*B
Add power up requirements to maximum ratings information
Corrected the Ordering information entry
*C
RGL
Document #: 38-07087 Rev. *C
Page 7 of 7
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