IMIZ9104DAB [CYPRESS]
PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32;
| 型号： | IMIZ9104DAB |
| 厂家： | 
CYPRESS |
| 描述： | PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32 驱动 逻辑集成电路 |
| 文件： | 总7页 (文件大小：119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Z9104
Variable Delay Motherboard Clock Buffer
Table 1. Feedback Scale Select Codes
Features
Mode FBS1 FBS0 Pcounter
Ncounter
³ 8
MF[1]
2.0
• Outputphaserelationshipispreciselycontrollablewith
respecttoinputclockviaadedicatedexternalfeedback
path
• Two-kV ESD protected
• Six low-skew clocks generated
• One 2.5V output clock
• Outputs are individually enabled
• Output frequencies from 30 to 120 MHz
• 3.3V power supply
• Synchronous output enable and disable control
• 45–55% output duty cycle
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
³ 4
³ 4
³ 4
³ 8
³ 4
³ 4
³ 4
³ 8
³ 10
³ 12
³ 12
³ 4
2.5
3.0
1.5
1.0
³ 5
1.25
1.5
³ 6
• ±100 ps cycle-to-cycle jitter
• 32-lead TQFP package
³ 8
1.0
Note:
1. Multiplication Factor – The multiplication factor for these configurations is
the output frequency with respect to REFIN (FOUT = FIN × multiplication
factor).
• Pin-compatible with MPC932P
Block Diagram
Pin Configuration
MODE
FBS0
FBS1
VDDF
Ncounter
FBOUT
FBIN
REFIN
PLL
1
0
Pcounter
PLLEN
VDDI
REFIN
PLLEN
FBS0
1
2
3
4
5
6
7
8
24
23
22
21
VSS
CLK3
VDD
CLK4
Stop
Logic
CLK25
SC25
VDD25
FBS1
Z9104 20 VSS
CLK2
CLK3
CLK4
OEALL
STOPCLK
VSSI
19
18
17
CLK5
VDD
CLK6
Stop
Logic
SC2,3
Stop
SC4
SC5
SC6
Logic
CLK5
CLK6
Stop
Logic
Stop
Logic
VDD
STOPCLK
OEALL
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07083 Rev. *C
Revised May 6, 2002
Z9104
Pin Description
Pin
Name
PWR
I/O[2]
Description
External reference clock input pin.
2
REFIN
PLLEN
VDDI
I
I
When LOW, Ref input bypass PLL. It is intended for static testing at the part’s
internal logic.
3
VDD
VDD
PU
Feedback selection pins. These input pins control the internal routing of the
feedback output clock that produce the multiplier values listed in the “Feedback
Scale Select Code” table on page 1.
I
4, 5
FBS(0:1)
PU
I
Combined with the FBS pins, this pin determines the output clocks frequency
with respect to the REFIN pin. See table on page 1 for functionality.
31
6
MODE
OEALL
VDD
VDD
PD
I
Output Enable for all CLK output clocks. When at a logic LOW level, all outputs
are driven to a three-state.
PU
Stop Clock for all CLK output clocks. When at a logic LOW CLK (2:6) and CLK25
are driven to a logic LOW level synchronously with their next occurring HIGH
to LOW transition. This signal does NOT effect the FBOUT clock.
I
7
STOPCLK
FBOUT
VDD
PU
Clock source that is used in the device’s external feedback loop. This pin is
connected to the device’s FBIN pin either directly or through an external delay
circuit.
15
27
VDDF
O
CLK25
VDD25
VDD
O
O
2.5V output clock copy of CLK(2:6).
25, 23, 21,
19, 17
CLK(2:6)
These output clocks are the synthesized product of the REFIN clock and the
selections programmed on the FB0, FB1 and MODE pins.
20, 24, 28
18, 22
14
VSS
VDD
P
P
P
Ground pins for the device.
3.3V power supply pins for clock buffer circuit.
3.3V power supply pins for the FBOUT clock output buffers.
Synchronous output enable control pin for CLK25.[3]
VDDF
I
30
29
12
11
10
SC25
SC2:3
SC4
VDD
VDD
VDD
VDD
VDD
PU
I
Synchronous output enable control pin for CLK2 and CLK3 pins.[3]
Synchronous output enable control pin for CLK4 pins.[3]
Synchronous output enable control pin for CLK5 pins.[3]
Synchronous output enable control pin for CLK6 pins.[3]
PU
I
PU
I
SC5
PU
I
SC6
PU
26
32
16
9
VDD25
VDDA
VSSF
VSSA
VSSI
P
P
P
P
P
P
2.5V power supply pin for the CLK25 clock output buffers.
Analog power. See recommended circuitry later in this data sheet.
Ground supply for pin 15 (FBOUT) buffer.
Ground power connection for analog circuitry.
8
Ground power connection for input clock circuitry.
3.3V power connection for input clock circuitry.
1
VDDI
Notes:
2. Pins with “PU” or “PD” listed in the Type column indicate that these pins have internal pull-up or pull down resistors. These resistors ensure that the device will
sense a logic 1 (HIGH) or logic 0 (LOW) condition respectively when the device is powered up and no electrical connection is made to these pins.
3. All synchronous output enables, when driven to a logic LOW level, will cause their associated output clocks to transition to a logic LOW level and remain there.
Likewise, they will cause their associated output clocks to begin running when driven to a logic HIGH level. This enabling and disabling action will produce no
runt (short or long) clock output cycles.
Document #: 38-07083 Rev. *C
Page 2 of 7
Z9104
Output Clock Disable and Enable Timing
When each clock enable pin (SC25 through SC6) is brought
to a logic low level, its related output clock (CLK25 through
CLK6) will be forced to a logic low level after one complete
cycle. The enable pins are synchronized to the internal clock
such that upon assertion, these signals will hold the clocks low
until the beginning of a new clock period and thus avoid a runt
pulse generation on the outputs.
Figure 2 shows the recommended power supply decoupling
circuitry to obtain minimum device clock noise (jitter). Designs
shown implements this decoupling scheme in noisy VDD
environments to protect the device’s internal analog circuitry
from digital noise generated on the main 3.3V supply. A range
of 2.2 to 15 Ohms is recommended for Rs. Rs should be
adjusted to the minimum value required to produce acceptable
performances from the device. The ultimate limitation on the
Rs maximum value is the device’s minimum VDD spec.
CLK
SCx
Stop on next falling edge
CLKx
Start on next
rising edge
Figure 1.
Rs
3.3V
VDDA
+
-
.01
µ
F
22 µF
Z9104
Device
Figure 2.
Applications Examples
Table 2. Z9104 Input Reference Frequency Ranges
REFIN Frequency
REFIN Frequency
Max. (MHz)
CLK(25:6), Output
Frequency (MHz)
Mode
FBS1
FBS0
Min. (MHz)
Example
1
0
0
50
120
96
80
60
60
48
40
40
1 x REFIN
1.25 x REFIN
1.5 x REFIN
1 x REFIN
REFIN = 66.7 MHz
CLK* = 66.7 MHz
1
1
1
0
0
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
40
33.3
25
REFIN = 66.7 MHz
CLK* = 83.3 MHz
REFIN = 66.7 MHz
CLK* = 100 MHz
REFIN = 33.3 MHz
CLK* = 33.3 MHz
25
2 x REFIN
REFIN = 33.3 MHz
CLK* = 66.7 MHz
20
2.5 x REFIN
3 X REFIN
1.5 X REFIN
REFIN = 33.3 MHz
CLK* = 83.3 MHz
16.7
16.7
REFIN = 33.3 MHz
CLK* = 100 MHz
REFIN = 33.3 MHz
CLK* = 50 MHz
Document #: 38-07083 Rev. *C
Page 3 of 7
Z9104
Maximum Ratings
Voltage Relative to VSS:................................................–0.3V
Voltage Relative to VDD: .................................................0.3V
Storage Temperature: ................................–65°C to + 150°C
Operating Temperature:................................–40°C to +85°C
Maximum Power Supply: ...................................................7V
Maximum ESD protection ............................................... 2KV
This device contains circuitry to protect the inputs against
damage due to up to 2,000 volt static voltages or electric field;
however, precautions should be taken to avoid application of
any voltage higher than the maximum rated voltages to this
circuit. For proper operation, Vin and Vout should be
constrained to the range:
VSS < (Vin or Vout) < VDD
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
DC Parameters: VDD = VDDF = 3.3V±5%, VDD25 = 2.5V±5%, TA = –40°C to +85°C
Parameter
VIL
Description
Input Low Voltage
Conditions
Min.
VSS
2.0
Typ.
Max.
0.8
Unit
V
VIH
Input High Voltage
Input Low Current[5]
Input High Current[5]
VDD
–100
+100
V
IIL
VIN = VSS
VIN = VDD
mA
mA
V
IIH
VOH
Output Voltage High for CLK(2:6)[4] @IOH = –20 mA
Output Voltage for High CLK25[4,6] @IOH = –13 mA
Output Low Voltage for CLK(2:6)[4] @IOL = 20mA
Output Low Voltage for CLK25[4,6] @IOL = 13 mA
Three-State Leakage Current
2.4
1.8
VOHC25
VOL
VOLC25
Ioz
V
0.5
0.5
10
V
V
mA
pF
mA
Cpd
Power Dissipation Capacitance
Quiescent Supply Current
Per Output
20
ICCQ
15
130
20
Maximum Core Supply
Current
ICC
mA
mA
ICCPLL
Maximum PLL Supply Current
Notes:
4. Z9104D outputs can drive series or parallel terminated 50W (or 50W to VDD/2) transmission lines.
5. Inputs have pull-up and pull-down resistors, which affect the input current
6. Varies 1:1 with VDD25
.
Document #: 38-07083 Rev. *C
Page 4 of 7
Z9104
AC Parameters[7]: VDD = VDDF = 3.3V±5%, VDD25 = 2.5V±5%, TA = –40°C to +85°C
Parameter
Tr,Tf
Description
REFIN Rise/Fall Time
VCO lock range
Conditions
Min.
Typ.
Max.
Unit
ns
0.4 to 2.4 Volts
3.0
480
120
FVCO
200
MHz
MHz
MHz
Fmax
Maximum output frequency
Input Reference Frequency
Pcounter = 4
REFIN
See Table 2
Controlled by VCO lock
range
FrefDC
Reference Input Duty Cycle
Measured @ 1.5V
25
75
%
TSkewO
Output to Output clock skew
(CLK(2:6])[8]
Measured at 1.5 Volts
300
ps
TSkewO25
OutputtoOutputclockskew (CLK25 Measured at 1.5 V on CLK(2:6) and at
to Q(2:6))[8]
1.25V on CLK25
600
ps
Tpd
DC
REFIN to FBIN Average Delay[9,10] Fin = 66.6 MHz
–150
0
+150
55
ps
%
Output Duty Cycle
Measured at 1.5 V on CLK(2:6) and at
1.25V on CLK25
45
50
Tr,Tf
Output Rise/Fall Time
Measured from 0.8V to 2.0V on CLK(2:6)
and from 0.8V to 1.8V on CLK25
0.1
1.2
ns
Ten
Output Enable Time
Output Disable Time
Cycle-to-cycle jitter
2.0
2.0
10
ns
ns
ps
Tdis
Tjitter
8.0
Short term jitter (adjacent cycle) Select
Code 100 50 MHz in/out
+100
Tlock
Maximum PLL Lock Time
Power Up Ramp Time
10
ms
ns
Tpr
Measured between 0.3V and 3.0V
250
20 ms
Notes:
7. Parameters are guaranteed by design and characterization. Not 100% tested in production.
8. Outputs are loaded with 33 pF each.
9. REFIN rise time = FBIN rise time.
10. Tpd measurement uses the averaging feature of the scope to filter out the jitter component.
Document #: 38-07083 Rev. *C
Page 5 of 7
Z9104
Ordering Information
Part Number
Package Type
Production Flow
Industrial, –40°C to +85°C
Industrial, –40°C to +85°C
IMIZ9104DAB
IMIZ9104DABT
32-lead TQFP
32-lead TQFP–Tape and Reel
Package Drawing and Dimension
32-lead Thin Plastic Quad Flatpack 7 × 7 × 1.0 mm A32
51-85063-B
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07083 Rev. *C
Page 6 of 7
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Z9104
Document Title: Z9104 Variable Delay Motherboard Clock Buffer
Document Number: 38-07083
Orig. of
REV.
**
ECN No. Issue Date
Change
Description of Change
Convert from IMI to Cypress
107119
108351
06/05/01
6/29/01
IKA
*A
NDP
Change Production flow from “Commercial” to “Industrial.” Change Part
Number Revision from “C” to “D.”
*B
*C
109808
113686
02/01/02
05/13/02
DSG
CTK
Convert from Word Doc to Adobe Framemaker Cypress Format
Changed the Output Frequency (30 to 10 MHz) to (30 to 120 MHz)
Corrected ordering information to indicate “Industrial” range
Document #: 38-07083 Rev. *C
Page 7 of 7
相关型号：
IMIZ9104DABT
PLL Based Clock Driver, 6 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32
CYPRESS
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