IMIXF652AYB [CYPRESS]

Processor Specific Clock Generator, 83.3MHz, CMOS, PDSO48, SSOP-48;
IMIXF652AYB
型号: IMIXF652AYB
厂家: CYPRESS    CYPRESS
描述:

Processor Specific Clock Generator, 83.3MHz, CMOS, PDSO48, SSOP-48

时钟 光电二极管 外围集成电路 晶体
文件: 总7页 (文件大小:113K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
XF652  
Enhanced Clock Generator for 2 DIMM Systems  
Preliminary  
FREQUENCY TABLE (MHz)  
PRODUCT FEATURES  
SELECTORS  
OUTPUTS (MHz)  
n
Supports Pentium, Pentiumä II, Pentiumä -Pro,  
FCT1  
FCT0  
S1  
S0  
CPUCLK  
PCICLK  
AMD and Cyrix CPUs.  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TEST  
73.38  
83.3  
69.80  
57.27  
76.96  
62.64  
50.11  
83.3  
75  
61.57  
68.01  
55  
75  
60  
TEST  
36.9  
a.32  
n
n
n
n
Supports Intel chipset requirements.  
Supports Sychronous DRAM designs  
4 host (CPU/AGP) clocks & 8 SDRAM clocks.  
Optional common or mixed supply mode :  
34.90  
28.63  
38.48  
31.32  
25.05  
41.76  
a.32  
30.78  
34.01  
27.50  
37.50  
30.00  
33.30  
(VDD = VDD3 = VDD4 = VDD2 = 3.3V)  
(VDD = VDD3 = VDD4 = 3.3V, VDD2 = 2.5V)  
< 250 pS skew on CPU buffers  
n
n
n
n
< 250 pS skew on PCI buffers  
Supports Single Pin Power Management.  
66.8  
F.A.S.T. (Frequency Augmentation System Test)  
Function for board performance testing.  
.A.32 = Asynchronous 32 MHz.  
n
48 Pin SSOP package for minimum board space  
CONNECTION DIAGRAM  
BLOCK DIAGRAM  
REF2  
REF1  
Vss  
OSCin  
OSCout  
FCT1  
1
2
3
4
5
6
7
8
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
Vdd  
REF3  
Vdd2  
IOAPIC  
PWR_DWN#  
Vss  
CPUCLK1  
CPUCLK2  
Vdd2  
CPUCLK3  
CPUCLK4  
Vss  
SDRAM1  
SDRAM2  
Vdd3  
SDRAM3  
SDRAM4  
Vss  
SDRAM5  
SDRAM6  
Vdd3  
OSCin  
B
REF(1:3)  
IOAPIC  
3
REF  
OSCout  
Vdd4  
PCICLK_F  
PCICLK1  
Vss  
PCICLK2  
PCICLK3  
PCICLK4  
PCICLK5  
Vdd4  
Vdd2  
9
S1  
S0  
CPUCLK(1:4)  
B
B
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
4
PLL1  
FCT0  
FCT1  
SDRAM (1:8)  
PCICLK_F  
8
PCICLK(1:6)  
dly  
B
6
PCICLK6  
Vss  
PWR_DWN#  
S0  
S1  
FCT0  
Vdd4  
48 MHz  
24 Mhz  
Vss  
24 MHz  
48 MHz  
PLL2  
SDRAM7  
SDRAM8  
Vdd  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.  
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571  
Rev.1.3  
5/6/97  
Page 1 of 7  
XF652  
Enhanced Clock Generator for 2 DIMM Systems  
Preliminary  
PIN DESCRIPTION  
PIN No.  
4
Pin Name  
OSCin  
Power  
Vdd  
I/O  
I
TYPE  
OSC1  
Description  
On-chip reference oscillator input pin. Requires either an  
external parallel resonant crystal (nominally 14.318 MHz) or  
externally generated reference signal  
5
O
OSC1  
On chip reference oscillator output pin. Drives an external  
parallel resonant crystal. When an externally generated  
reference signal is used, this pin is left unconnected  
OSCout  
Vdd4  
18, 19, 6,  
20  
I
Internal Frequency select input pins. See page 1 for frequency selection.  
Pull-Up  
S(0:1),  
FCT(0:1)  
-
42, 41, 39,  
38  
36, 35, 33,  
32, 30, 29,  
27, 26  
O
O
Type1  
Clock outputs. CPU frequency table specified. Power is applied  
by Vdd2 pin.  
Synchronous Dynamic RAM clocks. These may be disabled (in  
groups of 2) by programming (with a resistor) the lower  
numbered clock to ground with a 20 K resistor. See output buffer  
disable table.  
CPUCLK(1:4)  
Vdd2  
Vdd3  
Type4  
SDRAM(1:8)  
GND  
43, 37, 31,  
24, 17, 10.  
3
P
Ground pins for the device.  
-
48, 25  
46, 40  
34, 28  
21, 15, 7  
23  
P
P
P
Power supply pins for analog circuit , Fixed clocks and core logic  
Power supply pins for 2.5V/3.3V CPU buffers.  
Power supply pins for 3.3V PCI and SDRAM buffers.  
Vdd  
Vdd2  
Vdd3  
-
-
-
Vdd4  
-
O
O
O
O
Type3  
Type3  
Type4  
Type5  
Frequency output for super I/O  
Frequency output for USB.  
Buffered output of on-chip 14.31818 Mhz reference oscillator.  
PCI clock outputs. See frequency table  
24MHz  
48MHZ  
REF(1:3)  
PCICLK(1:6)  
Vdd4  
Vdd4  
Vdd  
Vdd  
22  
2, 1, 47  
9, 11, 12,  
13, 14, 16  
8
O
O
Type5  
Type2  
PCI clock outputs. See frequency table.  
- Buffered output of 14.3MHZ for multiprocessor support. It is  
powered by Vdd2  
PCICLK_F  
IOAPIC  
Vdd  
Vdd2  
45  
44  
I
Internal Power down, turns off power to entire IC, including VCO.  
Pull-Up  
PWR_DWN#  
-
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.  
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571  
Rev.1.3  
5/6/97  
Page 2 of 7  
XF652  
Enhanced Clock Generator for 2 DIMM Systems  
Preliminary  
POWER MANAGEMENT FUNCTION  
The device clocks may be disabled using the PWR_DWN# pin in order to reduce power consumption. All clocks are  
stopped in the low state. All clocks maintain a valid high period on transitions from running to stopped. When powered  
down, the reference oscillator and VCOs are stopped. On low to high transitions of PWR_DWN#, external circuitry  
should allow 2 mS for the VCOs to stabilize prior to assuming that the pulse widths are correct.  
MAXIMUM RATINGS  
This device contains circuitry to protect the inputs  
against damage due to high static voltages or electric  
Voltage Relative to VSS:  
Voltage Relative to VDD:  
Storage Temperature:  
Ambient Temperature:  
Maximum Power Supply:  
-0.3V  
0.3V  
field; however, precautions should be taken to avoid  
application of any voltage higher than the maximum  
rated voltages to this circuit. For proper operation, Vin  
and Vout should be constrained to the range:  
VSS<(Vin or Vout)<VDD  
-65ºC to + 150ºC  
-55ºC to +125ºC  
7V  
Unused inputs must always be tied to an appropriate  
logic voltage level (either VSS or VDD).  
SWITCHING CHARACTERISTICS  
Characteristic  
Symbol  
Min  
Typ  
Max  
Units  
Conditions  
Measured at 1.5V  
Output Duty Cycle  
CPU to PCI Offset  
Skew (CPU-CPU)  
Skew (CPu-SDRAM)  
Skew (PCI-PCI)  
-
45  
1
-
50  
-
55  
4
%
ns  
tOFF  
15 pf Load Measured at 1.5V  
15 pf Load Measured at 1.5V  
15 pf Load Measured at 1.5V  
15 pf Load Measured at 1.5V  
-
tSKEW1  
tSKEW2  
tSKEW3  
DP  
-
250  
500  
250  
+250  
500  
ps  
-
-
ps  
-
-
ps  
-
-
ps  
DPeriod Adjacent Cycles  
Jitter Spectrum 20 dB  
Bandwidth from Center  
BWJ  
KHz  
VDD = VDD3 =3.3V ±5%, VDD2 = 2.375V to 2.9V, TA = 0ºC to +70ºC  
note 1: Ring Back must not enter this range.  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.  
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571  
Rev.1.3  
5/6/97  
Page 3 of 7  
XF652  
Enhanced Clock Generator for 2 DIMM Systems  
Preliminary  
TYPE 1 BUFFER CHARACTERISTICS FOR CPUCLK(1:4)  
Characteristic  
Symbol  
Min  
Typ  
Max  
Units  
Conditions  
Pull-Up Current Min  
Pull-Up Current Max  
Pull-Down Current Min  
Pull-Down Current Max  
Rise Time  
IOHmin  
IOHmax  
IOLmin  
IOLmax  
TR  
-49  
-
-
-
-
-
-
-
mA  
mA  
mA  
mA  
nS  
Vout = 1.0 V  
-19  
Vout = 2.5 V  
Vout = 1.2 V  
Vout = 0.3 V  
20 pF Load  
48  
-
-
41  
1.6  
0.4  
Between 0.4 V and 2.0 V  
Fall Time  
TF  
0.4  
-
1.6  
nS  
20 pF Load  
Between 0.4 V and 2.0 V  
VDD = VDD3 =3.3V ±5%, VDD2 = 2.5V +/-5%, TA = 0ºC to +70ºC  
TYPE 2 BUFFER CHARACTERISTICS FOR IOAPIC  
Characteristic  
Symbol  
Min  
Typ  
Max  
Units  
Conditions  
Pull-Up Current Min  
Pull-Up Current Max  
Pull-Down Current Min  
Pull-Down Current Max  
IOHmin  
IOHmax  
IOLmin  
IOLmax  
TR  
-36  
-
-
-
-
-
-
-
mA  
mA  
mA  
mA  
nS  
Vout = 1.4 V  
Vout = 2.7 V  
Vout = 1.0 V  
Vout = 0.2 V  
20 pF Load  
-29  
36  
-
-
28  
1.6  
Rise Time  
0.4  
Between 0.4 V and 2.0 V  
Fall Time  
TF  
0,4  
-
1.6  
nS  
20 pF Load  
Between 0.4 V and 2.0 V  
VDD = VDD3 =3.3V ±5%, VDD2 = 2.5V +/-5%, TA = 0ºC to +70ºC  
TYPE 3 BUFFER CHARACTERISTICS FOR REF(2:3) and 48/24 MHz  
Characteristic  
Symbol  
Min  
Typ  
Max  
Units  
Conditions  
Pull-Up Current Min  
Pull-Up Current Max  
Pull-Down Current Min  
Pull-Down Current Max  
IOHmin  
IOHmax  
IOLmin  
IOLmax  
TR  
-29  
-
-
-
-
-
-
-
mA  
mA  
mA  
mA  
nS  
Vout = 1.0 V  
Vout = 3.135 V  
Vout = 1.95 V  
Vout = 0.4 V  
20 pF Load  
-23  
29  
-
-
TBD  
4.0  
Rise Time  
1.0  
Between 0.4 V and 2.4 V  
Fall Time  
TF  
1.0  
-
4.0  
nS  
20 pF Load  
Between 0.4 V and 2.4 V  
VDD = VDD3 =3.3V ±5%, VDD2 = 2.5V +/-5%, TA = 0ºC to +70ºC  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.  
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571  
Rev.1.3  
5/6/97  
Page 4 of 7  
XF652  
Enhanced Clock Generator for 2 DIMM Systems  
Preliminary  
TYPE 4 BUFFER CHARACTERISTICS FOR REF1, SDRAM(1:8)  
Characteristic  
Symbol  
Min  
Typ  
Max  
Units  
Conditions  
Pull-Up Current Min  
Pull-Up Current Max  
Pull-Down Current Min  
Pull-Down Current Max  
IOHmin  
IOHmax  
IOLmin  
IOLmax  
TR  
-54  
-
-
-
-
-
-
-
mA  
mA  
mA  
mA  
nS  
Vout = 2.0 V  
-46  
Vout = 3.135 V  
Vout = 1.0 V  
Vout = 0.4 V  
54  
-
-
53  
2.0  
Rise Time  
0.5  
45 pF Load, REF1  
Between 0.4 V and 2.4 V  
Fall Time  
Between 0.4 V and 2.4 V  
TF  
TR  
TF  
0.5  
0.5  
0.5  
-
-
-
2.0  
1.3  
1.3  
nS  
nS  
nS  
45 pF Load, REF1  
Rise Time  
Between 0.4 V and 2.4 V  
30 pF Load, SDRAM(1:8)  
30 pF Load, SDRAM(1:8)  
Fall Time  
Between 0.4 V and 2.4 V  
VDD = VDD3 =3.3V ±5%, VDD2 =2.5V +/-5%, TA = 0ºC to +70ºC  
TYPE 5 BUFFER CHARACTERISTICS FOR PCICLK(1:6,F)  
Characteristic  
Symbol  
Min  
Typ  
Max  
Units  
Conditions  
Pull-Up Current Min  
Pull-Up Current Max  
Pull-Down Current Min  
Pull-Down Current Max  
IOHmin  
IOHmax  
IOLmin  
IOLmax  
TR  
-33  
-
-
-
-
-
-
-
mA  
mA  
mA  
mA  
nS  
Vout = 1.0 V  
Vout = 3.135 V  
Vout = 1.95 V  
Vout = 0.4 V  
30 pF Load  
-33  
30  
-
-
38  
2.0  
RiseTime  
0.5  
Between 0.4 V and 2.4 V  
Fall Time  
TF  
0.5  
-
2.0  
nS  
30 pF Load  
Between 0.4 V and 2.4 V  
VDD = VDD3 =3.3V ±5%, VDD2 = 2.5V +/-5%,, TA = 0ºC to +70ºC  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.  
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571  
Rev.1.3  
5/6/97  
Page 5 of 7  
XF652  
Enhanced Clock Generator for 2 DIMM Systems  
Preliminary  
PCB LAYOUT RECOMMENDATION  
Via to GND plane  
Via to VDD Island  
Via to VCC plane  
VCC3.3V  
IMIXF652  
FB1  
C12  
C11  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1
VCC2.5V  
2
3
C3  
4
22mF  
5
FB1  
6
C4  
7
8
C10  
9
C13  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
22mF  
C9  
C5  
C6  
C8  
C7  
This is only a layout recommendation for best performance and lower EMI. The designer may choose a differnent approach but  
C4, C5, C6, C7, C8, C9, C10, C11and C12 (all are 0.1mf) should always be used and placed close to their VDD pins.  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.  
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571  
Rev.1.3  
5/6/97  
Page 6 of 7  
XF652  
Enhanced Clock Generator for 2 DIMM Systems  
Preliminary  
PACKAGE DRAWING AND DIMENSIONS  
48 PIN SSOP OUTLINE DIMENSIONS  
INCHES  
MILLIMETERS  
C
SYMBOL  
MIN  
NOM  
MAX  
MIN  
NOM  
MAX  
L
A
A1  
A2  
B
0.095  
0.008  
0.088  
0.008  
0.005  
0.620  
0.292  
0.102  
0.012  
0.090  
0.010  
-
0.110  
0.016  
0.092  
0.0135  
0.010  
0.630  
0.299  
2.41  
0.20  
2.24  
2.59  
0.31  
2.29  
2.79  
0.41  
2.34  
H
E
0.203 0.254 0.343  
0.127 0.254  
15.75 15.88 16.00  
C
D
E
-
0.625  
0.296  
0.025 BSC  
0.406  
0.013  
0.032  
5º  
D
a
7.42  
7.52  
7.59  
e
0.635 BSC  
A2  
A
H
a
0.400  
0.10  
0.024  
0º  
0.410  
0.016  
0.040  
8º  
10.16 10.31 10.41  
0.25  
0.61  
0º  
0.33  
0.81  
5º  
0.41  
1.02  
8º  
A1  
L
e
B
a
X
0.085  
0.093  
0.100  
2.16  
2.36  
2.54  
ORDERING INFORMATION  
Part Number  
Package Type  
Production Flow  
Commercial, 0ºC to +70ºC  
IMIXF652AYB  
Note:  
48 PIN SSOP  
The ordering part number is formed by a combination of device number, device revision, package style, and  
screening as shown below.  
IMIXF652AYB  
Flow  
B = Commercial, 0ºC to + 70ºC  
Package  
Y = SSOP  
Revision  
IMI Device Number  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.  
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571  
Rev.1.3  
5/6/97  
Page 7 of 7  

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