IMISM561BZ [CYPRESS]
Spread Spectrum Clock Generator; 扩频时钟发生器
| 型号： | IMISM561BZ |
| 厂家： | 
CYPRESS |
| 描述： | Spread Spectrum Clock Generator |
| 文件： | 总8页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SM561
Spread Spectrum Clock Generator
Features
Applications
• 54- to 166-MHz operating frequency range
• Wide (9) range of spread selections
• Accepts clock and crystal inputs
• Low power dissipation
• 3.3V = 165 mw. (Fin = 120 MHz)
• Frequency spread disable function
• Center spread modulation
• High-resolution VGA controllers
• LCD panels and monitors
• Workstations and servers
Benefits
• Peak electromagnetic interference (EMI) reduction by 8 to
16 dB
• Fast time to market
• Cost reduction
• Low cycle-to-cycle jitter
• Eight-pin SOIC package
Pin Configuration
Block Diagram
250 K
Xin/CLK
VDD
1
2
3
4
8
7
6
5
Xout
S0
Xin/
CLK
REFERENCE
DIVIDER
1
8
LF
4 pf
PD
CP
VSS
S1
MODULATION
CONTROL
SSCLK
SSCC
Xout
FEEDBACK
DIVIDER
8 pF
VCO
2
3
VDD
VSS
INPUT
DECODER
LOGIC
DIVIDER
AND MUX
4
SSCLK
5
6
7
SSCC
S1
S0
Cypress Semiconductor Corporation
Document #: 38-07021 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised December 14, 2002
SM561
.
Pin Description
Pin
Number
Pin
Type
Pin Name
Pin Description
1
Xin/CLK
I
Clock or Crystal connection input. Refer to Table 1 for input frequency range
selection.
2
3
4
5
VDD
GND
P
P
O
I
Positive power supply.
Power supply ground.
Modulated clock output.
SSCLK
SSCC
Spread Spectrum Clock Control (Enable/Disable) function. SSCG function is
enabled when input is high and disabled when input is low. This pin is pulled high
internally.
6
7
8
S1
S0
I
I
Tri-level Logic input control pin used to select Frequency and Bandwidth.
Frequency/Bandwidth selection and Tri-level Logic programming. See Figure 1 on
page 3.
Tri-level Logic input control pin used to select Frequency and Bandwidth.
Frequency/Bandwidth selection and Tri-level Logic programming. See Figure 1 on
page 3.
Xout
O
Oscillator output pin connected to crystal. Leave this pin unconnected If an
external clock drives Xin/CLK.
General Description
The Cypress SM561 is a Spread Spectrum Clock Generator
(SSCG) IC used for the purpose of reducing EMI found in
today’s high-speed digital electronic systems.
nine available Frequency Modulation and Spread% ranges.
Refer to Table for programming details.
The SM561 is intended for use with applications with a
reference frequency in the range of 54 to 166 MHz.
The SM561 uses a Cypress proprietary phase-locked loop
(PLL) and Spread Spectrum Clock (SSC) technology to
synthesize and frequency modulate the input frequency of the
reference clock. By frequency modulating the clock, the
measured EMI at the fundamental and harmonic frequencies
of Clock (SSCLK) is greatly reduced.
A wide range of digitally selectable spread percentages is
made possible by using Tri-level (High, Low, and Middle) logic
at the S0 and S1 digital control inputs.
The output spread (frequency modulation) is symmetrically
centered on the input frequency.
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory requirements and time to
market without degrading the system performance.
Spread Spectrum Clock Control (SSCC) function enables or
disables the frequency spread and is provided for easy
comparison of system performance during EMI testing.
The SM561 is a very simple and versatile device to use. The
frequency and spread% range is selected by programming S0
and S1 digital inputs. These inputs use three (3) logic states
including High (H), Low (L), and Middle (M) to select one of the
The SM561 is available in an eight-pin SOIC package with a
0°C-to-70°C operating temperature range.
Refer to the SM560 data sheet for operation at frequencies
from 25 to 108 MHz.
Document #: 38-07021 Rev. *C
Page 2 of 8
SM561
Table 1. Frequency and Spread% Selection (Center Spread)
54-108 M Hz (Low Range)
Input
Frequency
(M Hz)
54 - 60
60 - 70
S1=M
S0=M
(% )
3.6
S1=M
S0=0
(% )
3.1
S1=1
S0=0
(% )
2.6
S1=0
S0=0
(% )
2.1
S1=0
S0=M
(% )
1.8
Select the
Frequency and
Center Spread %
desired and then
set S1, S0 as
3.5
3.0
2.5
2.0
1.7
indicated.
70 - 80
3.3
2.8
2.4
1.9
1.6
80 - 100
100 - 108
3.0
2.6
2.5
2.3
2.1
1.9
1.7
1.5
1.4
1.3
108 - 166 M Hz (H igh Range)
Input
Frequency
(M Hz)
180 - 120
120 -130
130 - 140
140 - 150
150 - 166
S1=1
S0=M
(% )
2.3
2.3
2.3
S1=0
S0=1
(% )
1.7
1.7
1.7
S1=1
S0=1
(% )
1.1
1.1
1.1
S1=M
S0=1
(% )
0.9
0.9
0.9
Select the
Frequency and
Center Spread %
desired and then
set S1, S0 as
indicated.
2.2
2.1
1.6
1.5
1.1
1.0
0.9
0.8
Tri-level Logic
With binary logic, four states can be programmed with two
control lines where as Tri-level Logic can program nine logic
states using two control lines. Tri-level Logic in the SM561 is
implemented by defining a third logic state in addition to the
standard logic “1” and “0”. Pins 6 and 7 of the SM561
recognize a logic state by the voltage applied to the respective
pin. These states are defined as “0” (Low), “M” (Middle), and
VDD = 3.3 VDC
“1” (One). Each of these states have a defined voltage range
that is interpreted by the SM561 as a “0”, “M,” or “1” logic state.
Refer to Table 1 for voltage ranges for each logic state. By
using two equal value resistors (typically 20K) the “M” state
can be easily programmed. Pins 6 or 7 can be tied directly to
ground or VDD for Logic “0” or “1,” respectively.
VDD = 3.3 VDC
VDD = 3.3 VDC
SM561
SM561
SM561
20K
7
6
5
1.65 VDC
0 VDC
7
6
5
7
6
5
20K
EX. 1
EX. 2
EX. 3
Figure 1.
Document #: 38-07021 Rev. *C
Page 3 of 8
SM561
Absolute Maximum Ratings[1]
Supply Voltage (VDD): .................................... –0.5V to +6.0V
DC Input Voltage:...................................–0.5V to VDD + 0.5V
Junction Temperature .................................–40°C to +140°C
Operating Temperature:...................................... 0°C to 70°C
Storage Temperature.................................. –65°C to +150°C
Static Discharge Voltage(ESD)........................... 2,000V–Min
DC Electrical Characteristics (VDD = 3.3V, Temp. = 25°C and CL (pin 4) = 15 pF, unless otherwise noted)
Parameter
VDD
Description
Power Supply Range
Input High Voltage
Input Middle Voltage
Input Low Voltage
Conditions
Min.
2.97
Typ.
3.3
Max.
3.63
VDD
Unit
V
± 10%
VINH
VINM
VINL
VOH1
VOH2
VOL1
VOL2
Cin1
S0 and S1 only
S0 and S1 only
S0 and S1 only
IOH = 6 ma
0.85VDD
VDD
V
0.40VDD 0.50VDD 0.60VDD
V
0.0
2.4
2.0
0.0
0.15VDD
V
Output High Voltage
Output High Voltage
Output Low Voltage
Output Low Voltage
Input Capacitance
Input Capacitance
Input Capacitance
Power Supply Current
Power Supply Current
V
I
OH = 20 ma
V
IOH = 6 ma
0.4
1.2
5
V
IOH = 20 ma
V
Xin/CLK (pin 1)
Xout (pin 8)
3
6
3
4
8
pF
pF
pF
mA
mA
Cin2
10
5
Cin2
S0, S1, SSCC (pins 7, 6, 5)
FIN = 65 MHz
4
IDD1
IDD2
35
50
45
55
FIN = 166 MHz
Electrical Timing Characteristics (VDD = 3.3V, T = 25°C and CL=15 pF, unless otherwise noted)
Parameter
Description
Conditions
VDD = 3.30V
Min.
Typ.
Max.
Unit
ICLKFR
Input Clock Frequency
Range
54
166
MHz
Trise
Clock Rise Time (pin 4)
Clock Fall Time (pin 4)
Input Clock Duty Cycle
SSCLK1 @ 0.4 – 2.4V
SSCLK1 @ 0.4 – 2.4V
XIN/CLK (pin 1)
1.2
1.2
20
45
–
1.4
1.4
50
1.6
1.6
80
ns
ns
%
Tfall
DTYin
DTYout
JCC1
Output Clock Duty Cycle SSCLK1 (pin 4)
50
55
%
Cycle-to-Cycle Jitter
Cycle-to-Cycle Jitter
Fin = 140 MHz
Fin = 140 MHz
125
150
175
200
ps
ps
JCC2
–
Note:
1. Single Power Supply: The Voltage on any input or I/O pin cannot exceed the power pin during power up.
Document #: 38-07021 Rev. *C
Page 4 of 8
SM561
SSCG Theory of Operation
50 %
50 %
The SM561 is a PLL-type clock generator using a proprietary
Cypress design. By precisely controlling the bandwidth of the
output clock, the SM561 becomes a Low EMI clock generator.
The theory and detailed operation of the SM561 will be
discussed in the following sections.
Tc = 15.4 ns
Clock Frequency = fc = 65 MHz
Clock Period = Tc =1/65 MHz = 15.4 ns
EMI
If this clock is applied to the Xin/CLK pin of the SM561, the
output clock at pin 4 (SSCLK) will be sweeping back and forth
between two frequencies. These two frequencies, F1 and F2,
are used to calculate to total amount of spread or bandwidth
applied to the reference clock at pin 1. As the clock is making
the transition from F1 to F2, the amount of time and sweep
waveform play a very important role in the amount of EMI
reduction realized from an SSCG clock.
All digital clocks generate unwanted energy in their harmonics.
Conventional digital clocks are square waves with a duty cycle
that is very close to 50%. Because of this 50/50 duty cycle,
digital clocks generate most of their harmonic energy in the
odd harmonics, i.e., third, fifth, seventh, etc. It is possible to
reduce the amount of energy contained in the fundamental
and odd harmonics by increasing the bandwidth of the funda-
mental clock frequency. Conventional digital clocks have a
very high Q factor, which means that all of the energy at that
frequency is concentrated in a very narrow bandwidth, conse-
quently, higher energy peaks. Regulatory agencies test
electronic equipment by the amount of peak energy radiated
from the equipment. By reducing the peak energy at the funda-
mental and harmonic frequencies, the equipment under test is
able to satisfy agency requirements for EMI. Conventional
methods of reducing EMI have been to use shielding, filtering,
multilayer PCBs, etc. The SM561 uses the approach of
reducing the peak energy in the clock by increasing the clock
bandwidth, and lowering the Q.
The modulation domain analyzer is used to visualize the
sweep waveform and sweep period. Figure 1 also shows the
modulation profile of a 65-MHz SSCG clock. Notice that the
actual sweep waveform is not a simple sine or sawtooth
waveform. Figure 2 is a scan of the same SSCG clock using
a spectrum analyzer. In this scan you can see a 6.48-dB
reduction in the peak RF energy when using the SSCG clock.
Modulation Rate
Spectrum Spread Clock Generators utilize frequency
modulation (FM) to distribute energy over a specific band of
frequencies. The maximum frequency of the clock (Fmax) and
minimum frequency of the clock (Fmin) determine this band of
frequencies. The time required to transition from Fmin to Fmax
and back to Fmin is the period of the Modulation Rate, Tmr.
Modulation Rates of SSCG clocks are generally referred to in
terms of frequency or Fmod = 1/Tmod.
SSCG
SSCG uses a patented technology of modulating the clock
over a very narrow bandwidth and controlled rate of change,
both peak and cycle to cycle. The SM561 takes a narrow band
digital reference clock in the range of 54–166 MHz and
produces a clock that sweeps between a controlled start and
stop frequency and precise rate of change. To understand
what happens to a clock when SSCG is applied, consider a
65-MHz clock with a 50% duty cycle. From a 65-MHz clock we
know the following, as illustrated here.
The input clock frequency, Fin, and the internal divider count,
Cdiv, determine the Modulation Rate. In some SSCG clock
generators, the selected range determines the internal divider
count. In other SSCG clocks, the internal divider count is fixed
over the operating range of the part. The SM560 and SM561
have a fixed divider count, as listed below.
Document #: 38-07021 Rev. *C
Page 5 of 8
SM561
Device
Cdiv
SM561
2332
(All Ranges)
Example:
Device
Fin
= SM561
= 65 MHz
Range
Then;
= S1 = 1, S0 = 0
Modulation Rate = Fmod = 65 MHz/2332 = 27.9 kHz.
Modulation Profile
Spectrum Analyzer
Figure 2. SSCG Clock, SM561, Fin = 65 MHz
SM560 Application Schematic
VDD
R2
65 MHz Reference Clock
VDD
1
2
8
7
20 K
Xin/CLK
VDD
Xout
S0
C5
C6
0.1 uF
R4
22 uF.
20 K
3
6
5
GND
S1
R5
22
4
VDD
SSCLK
SM561
SSCC
Application Load
Figure 3. Application Schematic
The schematic in Figure 3 demonstrates how SM561 is
configured in a typical application. This application uses a
65-MHz reference clock connected to pin 1. Because an
external reference clock is used, pin 8 (Xout) is left uncon-
nected.
create a voltage divider that places VDD/2 on pin 7 to satisfy
the voltage requirement for an “M” state.
With this configuration, the SM561 will produce an SSCG
clock that is at a center frequency of 65 MHz. Referring to
Table 1, range “0, M” at 65 MHz will generate a modulation
profile that has a 1.7% peak to peak spread.
Figure 3 also demonstrates how to properly use the Tri-level
Logic employed in the SM561. Note that resistors R2 and R4
Document #: 38-07021 Rev. *C
Page 6 of 8
SM561
Ordering Information [2]
Part Number
IMISM561BZ
Package Type
Product Flow
Commercial, 0° to 70°C
Commercial, 0° to 70°C
8-pin SOIC
8-pin SOIC–Tape and Reel
IMISM561BZT
Package Drawing and Dimensions
Marking: Example:
IMI
SM561BS
Date Code, Lot#
SM561 B S
Package
S = SOIC
Revision
IMI Device Number
8-lead (150-Mil) SOIC S8
51-85066-A
All products and company names mentioned in this document are the trademarks of their respective holders.
Note:
2. The ordering part number differs from the marking on the actual device.
Document #: 38-07021 Rev. *C
Page 7 of 8
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
SM561
Document History Page
Document Title:SM561 Spread Spectrum Clock Generator
Document Number: 38-07021
Orig. of
REV.
ECN No. Issue Date
Description of Change
Convert from IMI to Cypress
Package suffix changed
Change
**
106949
113521
119446
122676
06/05/01
05/08/02
10/17/02
12/14/02
IKA
*A
*B
*C
DMG
RGL
Corrected the values in the Absolute Maximum Ratings to match the device.
Add power up requirements to operating conditions information.
RBI
Document #: 38-07021 Rev. *C
Page 8 of 8
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