IMISM560BZT [CYPRESS]
Spread Spectrum Clock Generator; 扩频时钟发生器
| 型号： | IMISM560BZT |
| 厂家： | 
CYPRESS |
| 描述： | Spread Spectrum Clock Generator |
| 文件： | 总8页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SM560
Spread Spectrum Clock Generator
Features
Applications
• 25- to 108-MHz operating frequency range
• Wide (9) range of spread selections
• Accepts clock and crystal inputs
• Low power dissipation
• VGA controllers
• LCD panels and monitors
• Printers and multi-function devices (MFP)
Benefits
• 3.3V = 85 mw (50 MHz)
• Frequency Spread disable function
• Center Spread modulation
• Low cycle-to cycle jitter
• Peak electromagnetic interference (EMI) reduction
by 8 to 16 dB
• Fast time to market
• Cost reduction
• Eight-pin SOIC package
Pin Configuration
Block Diagram
250 K
Xin/
CLK
REFERENCE
DIVIDER
1
8
Xin/CLK
VDD
1
2
3
4
8
7
6
5
Xout
S0
LF
4 pf
PD
CP
VSS
S1
MODULATION
CONTROL
SSCLK
SSCC
Xout
FEEDBACK
DIVIDER
8 pF
VCO
2
3
VDD
VSS
INPUT
DECODER
LOGIC
DIVIDER
AND MUX
4
SSCLK
5
6
7
SSCC
S1
S0
Cypress Semiconductor Corporation
Document #: 38-07020 Rev. *E
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised June 25, 2004
SM560
Pin Definitions
Pin
1
Name
Type
Description
Xin/CLK
VDD
I
P
P
O
I
Clock or Crystal connection input. Refer to Table 1 for input frequency range selection.
2
Positive power supply.
Power supply ground.
Modulated clock output.
3
GND
4
SSCLK
SSCC
5
Spread Spectrum Clock Control (Enable/Disable) function. SSCG function is enabled
when input is high and disabled when input is low. This pin is pulled high internally.
6
7
8
S1
S0
I
I
Tri-level Logic input control pin used to select frequency and bandwidth.
Frequency/bandwidth selection and Tri-level Logic programming. See Figure 1.
Tri-level Logic input control pin used to select frequency and bandwidth.
Frequency/bandwidth selection and Tri-level Logic programming. See Figure 1.
Xout
O
Oscillator output pin connected to crystal. Leave this pin unconnected If an external
clock drives Xin/CLK.
Functional Description
The Cypress SM560 is a Spread Spectrum Clock Generator
(SSCG) IC used for the purpose of reducing Electro Magnetic
Interference (EMI) found in today’s high-speed digital
electronic systems.
one of the nine available Frequency Modulation and Spread%
ranges. Refer to Table 1 for programming details.
The SM560 is optimized for SVGA (40 MHz) and XVGA (65
MHz) Controller clocks and also suitable for the applications
with the frequency range of 25 to 108 MHz.
The SM560 uses a Cypress-proprietary Phase-Locked Loop
(PLL) and Spread Spectrum Clock (SSC) technology to
synthesize and frequency modulate the input frequency of the
reference clock. By frequency modulating the clock, the
measured EMI at the fundamental and harmonic frequencies
of Clock (SSCLK1) is greatly reduced.
A wide range of digitally selectable spread percentages is
made possible by using three-level (High, Low and Middle)
logic at the S0 and S1 digital control inputs.
The output spread (frequency modulation) is symmetrically
centered on the input frequency.
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory requirements and time to
market without degrading the system performance.
Spread Spectrum Clock Control (SSCC) function enables or
disables the frequency spread and is provided for easy
comparison of system performance during EMI testing.
The SM560 is a very simple and versatile device to use. The
frequency and spread% range is selected by programming S0
and S1digital inputs. These inputs use three (3) logic states
including High (H), Low (L) and Middle (M) logic levels to select
The SM560 is available in an eight-pin SOIC package with a 0
to 70°C operating temperature range.
Table 1. Frequency and Spread% Selection (Center Spread)
25 – 54 M Hz (Low Range)
Input
Frequency
(M Hz)
25 – 35
35 – 40
40 – 45
45 – 50
50 – 54
S1=M
S0=M
(% )
3.8
3.5
3.2
S1=M
S0=0
(% )
3.2
3.0
2.8
S1=1
S0=0
(% )
2.8
2.5
2.4
S1=0
S0=0
(% )
2.3
2.1
1.9
S1=0
S0=M
(% )
1.9
1.7
1.6
Select the
Frequency and
Center Spread %
desired and then
set S1, S0 as
indicated.
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.7
1.5
1.4
50 – 108 M Hz (High Range)
Input
Frequency
(M Hz)
50 – 60
60 – 70
S1=1
S0=M
(% )
2.5
2.4
2.3
S1=0
S0=1
(% )
1.9
1.8
1.6
S1=1
S0=1
(% )
1.2
1.1
1.1
S1=M
S0=1
(% )
1.0
0.9
0.9
Select the
Frequency and
Center Spread %
desired and then
set S1, S0 as
indicated.
70 – 80
80 – 100
100 – 108
2.0
1.8
1.4
1.3
1.0
0.8
0.8
0.6
Document #: 38-07020 Rev. *E
Page 2 of 8
SM560
Tri-level Logic
With binary logic, four states can be programmed with two
control lines, whereas Tri-level Logic can program nine logic
states using two control lines. Tri-level Logic in the SM560 is
implemented by defining a third logic state in addition to the
standard logic “1” and “0.” Pins 6 and 7 of the SM560
recognize a logic state by the voltage applied to the respective
pin. These states are defined as “0” (Low), “M” (Middle), and
“1” (One). Each of these states has a defined voltage range
that is interpreted by the SM560 as a “0,” “M,” or “1” logic state.
Refer to Table 2 for voltage ranges for each logic state. By
using two equal value resistors (typically 20K) the “M” state
can be easily programmed. Pins 6 or 7 can be tied directly to
ground or VDD for Logic “0” or “1” respectively.
VDD = 3.3 VDC
VDD = 3.3 VDC
VDD = 3.3 VDC
SM560
SM560
SM560
20K
20K
7
6
5
1.65 VDC
0 VDC
7
6
5
7
6
5
EX. 1
EX. 2
EX. 3
Figure 1.
Document #: 38-07020 Rev. *E
Page 3 of 8
SM560
Absolute Maximum Ratings[1]
Supply Voltage (VDD):.................................... –0.5V to +6.0V
DC Input Voltage:..................................–0.5V to VDD + 0.5V
Junction Temperature .................................–40°C to +140°C
Operating Temperature:...................................... 0°C to 70°C
Storage Temperature.................................. –65°C to +150°C
Static Discharge Voltage (ESD).......................... 2,000V-Min.
Table 2. DC Electrical Characteristics: VDD = 3.3V, Temp. = 25°C and CL (Pin 4) = 15 pF, unless otherwise noted
Parameter
VDD
Description
Power Supply Range
Input High Voltage
Input Middle Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
Output Low Voltage
Output Low Voltage
Input Capacitance
Input Capacitance
Input Capacitance
Power Supply Current
Power Supply Current
Conditions
Min.
2.97
Typ.
3.3
Max.
3.63
VDD
Unit
V
±10%
VINH
VINM
VINL
VOH1
VOH2
VOL1
VOL2
Cin1
Cin2
Cin2
IDD1
S0 and S1 only
S0 and S1 only
S0 and S1 only
IOH = 6 mA
0.85VDD
VDD
V
0.40VDD 0.50VDD 0.60VDD
V
0.0
2.4
2.0
0.0
0.15VDD
V
V
IOH = 20 mA
V
IOH = 6 mA
0.4
1.2
5
V
IOH = 20 mA
V
Xin/CLK (Pin 1)
Xout (Pin 8)
3
6
3
4
8
pF
pF
pF
mA
mA
10
5
S0, S1, SSCC (Pins 7,6,5)
FIN = 40 MHz
FIN = 65 MHz
4
30
35
40
45
IDD2
Table 3. Electrical Timing Characteristics: VDD = 3.3V, T = 25°C and CL = 15 pF, unless otherwise noted
Parameter
ICLKFR
Trise
Description
Input Clock Frequency Range
Clock Rise Time (Pin 4)
Clock Fall Time (Pin 4)
Input Clock Duty Cycle
Output Clock Duty Cycle
Cycle-to-Cycle Jitter
Conditions
VDD = 3.30V
Min.
25
1.2
1.2
20
45
-
Typ.
Max.
108
1.6
1.6
80
Unit
MHz
ns
SSCLK1 @ 0.4 – 2.4V
SSCLK1 @ 0.4 – 2.4V
XIN/CLK (Pin 1)
1.4
1.4
50
Tfall
ns
DTYin
%
DTYout
JCC
SSCLK1 (Pin 4)
50
55
%
Fin = 25 – 108 MHz
125
175
ps
electronic equipment by the amount of peak energy radiated
from the equipment. By reducing the peak energy at the funda-
mental and harmonic frequencies, the equipment under test is
able to satisfy agency requirements for EMI. Conventional
methods of reducing EMI have been to use shielding, filtering,
multi-layer PCBs, etc. The SM560 uses the approach of
reducing the peak energy in the clock by increasing the clock
bandwidth, and lowering the Q.
SSCG Theory of Operation
The SM560 is a PLL-type clock generator using a proprietary
Cypress design. By precisely controlling the bandwidth of the
output clock, the SM560 becomes a Low EMI clock generator.
The theory and detailed operation of the SM560 will be
discussed in the following sections.
EMI
SSCG
All digital clocks generate unwanted energy in their harmonics.
Conventional digital clocks are square waves with a duty cycle
that is very close to 50%. Because of this 50/50-duty cycle,
digital clocks generate most of their harmonic energy in the
odd harmonics, i.e.; third, fifth, seventh, etc. It is possible to
reduce the amount of energy contained in the fundamental
and odd harmonics by increasing the bandwidth of the funda-
mental clock frequency. Conventional digital clocks have a
very high Q factor, which means that all of the energy at that
frequency is concentrated in a very narrow bandwidth, conse-
SSCG uses a patented technology of modulating the clock
over a very narrow bandwidth and controlled rate of change,
both peak and cycle to cycle. The SM560 takes a narrow band
digital reference clock in the range of 25–108 MHz and
produces a clock that sweeps between a controlled start and
stop frequency and precise rate of change. To understand
what happens to a clock when SSCG is applied, consider a
65-MHz clock with a 50% duty cycle. From a 65-MHz clock we
know the following:
quently, higher energy peaks. Regulatory agencies test
Note:
1. Single Power Supply: The Voltage on any input or I/O pin cannot exceed the power pin during power up.
Document #: 38-07020 Rev. *E
Page 4 of 8
SM560
can see a 6.48-dB reduction in the peak RF energy when using
the SSCG clock.
50 %
50 %
Clock Frequency = fc = 65MHz
Clock Period = Tc =1/65 MHz = 15.4 ns
Modulation Rate
Tc = 15.4 ns
Spectrum Spread Clock Generators utilize frequency
modulation (FM) to distribute energy over a specific band of
frequencies. The maximum frequency of the clock (Fmax) and
minimum frequency of the clock (Fmin) determine this band of
frequencies. The time required to transition from Fmin to Fmax
and back to Fmin is the period of the Modulation Rate, Tmr.
Modulation Rates of SSCG clocks are generally referred to in
terms of frequency or Fmod = 1/Tmod.
If this clock is applied to the Xin/CLK pin of the SM560, the
output clock at pin 4 (SSCLK) will be sweeping back and forth
between two frequencies. These two frequencies, F1 and F2,
are used to calculate to total amount of spread or bandwidth
applied to the reference clock at pin 1. As the clock is making
the transition from f1 to f2, the amount of time and sweep
waveform play a very important role in the amount of EMI
reduction realized from an SSCG clock.
The input clock frequency, Fin, and the internal divider count,
Cdiv, determine the Modulation Rate. In some SSCG clock
generators, the selected range determines the internal divider
count. In other SSCG clocks, the internal divider count is fixed
over the operating range of the part. The SM560 and SM561
have a fixed divider count, as listed below.
The modulation domain analyzer is used to visualize the
sweep waveform and sweep period. The left side of Figure 2
shows the modulation profile of a 65-MHz SSCG clock. Notice
that the actual sweep waveform is not a simple sine or
sawtooth waveform. The right side of Figure 2 is a scan of the
same SSCG clock using a spectrum analyzer. In this scan you
Device
Cdiv
SM560
SM561
1166 (All Ranges)
2332 (All Ranges)
Example:
Device =
Fin
SM560
65 MHz
=
Range =
S1 = 1, S0 = M
Then;
Modulation Rate = Fmod = 65 MHz/1166 = 55.8 kHz.
-6.58 dB
SMpoedBcutWrlua=tmio2An.4nP6ar%loyfzileer
Figure 2. SSCG Clock, SM560, Fin = 65 MHz
Document #: 38-07020 Rev. *E
Page 5 of 8
SM560
SM560 Application Schematic
3.3 uH.
L1
.
C2
Y1
C3
VDD
27 pF
40 MHz
27 pF
C4
.01 uF.
R2
1
2
8
7
20 K
Xin/CLK
VDD
Xout
S0
VDD
C5
22 uF.
C6
0.1 uF
R4
20 K
3
6
5
GND
S1
R5
4
VDD
SSCLK
SM560
SSCC
Application Load
22
Figure 3. Application Schematic[2]
The schematic in Figure 3 above demonstrates how the
SM560 is configured in a typical application. This application
is using a 40-MHz reference derived from a third overtone
crystal connected to pins 1 and 8. Since Y1 is a third overtone
crystal a notch filter is created with L1 and C3 to dampen the
gain of the oscillator at the fundamental frequency of this
crystal which is 13.33 MHz.
Figure 3 also demonstrates how to properly use the tri-level
logic employed in the SM560. Notice that resistors R2 and R4
create a voltage divider that places VDD/2 on pin 7 to satisfy
the voltage requirement for an “M” state.
With this configuration, the SM560 will produce an SSCG
clock that is at a center frequency of 40 MHz. Referring to
Table 2, range “0, M” at 40 MHz will generate a modulation
profile that has a 1.7% peak to peak spread.
Ordering Information[3]
Part Number
IMISM560BZ
Package Type
Product Flow
Commercial, 0° to 70°C
Commercial, 0° to 70°C
8-pin SOIC
IMISM560BZT
8-pin SOIC–Tape and Reel
Lead Free Devices
CYISM560BSXC
CYISM560BSXCT
8-pin SOIC
Commercial, 0° to 70°C
Commercial, 0° to 70°C
8-pin SOIC–Tape and Reel
Marking: Example:
IMI
SM560BS
Date Code, Lot#
SM560 B S
Package
S = SOIC
Revision
IMI Device Number
Note:
2. The value of L1 is calculated such that L1 and C3 are tuned to a frequency that is 130% higher than the fundamental frequency of the crystal.
ZC1 = 1/2πfC
ZC1 = 1/6.28 (17.33 MHz) (27 pF)
ZC1 = 340Ω
ZL1 = 2πFL
L = ZL1/2πf
L = 340/6.28(17.33 MHz)
L = 3.12 µH
3. The ordering part number differs from the marking on the actual device.
Document #: 38-07020 Rev. *E
Page 6 of 8
SM560
Package Drawing and Dimensions
8-lead (150-Mil) SOIC S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.150[3.810]
0.157[3.987]
3. REFERENCE JEDEC MS-012
4. PACKAGE WEIGHT 0.07gms
0.230[5.842]
0.244[6.197]
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
X 45°
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0138[0.350]
0.0192[0.487]
51-85066-*C
Document #: 38-07020 Rev. *E
Page 7 of 8
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
SM560
Document History Page
Document Title: SM560 Spread Spectrum Clock Generator
Document Number: 38-07020
Orig. of
Rev.
**
ECN No. Issue Date
Change
Description of Change
Convert from IMI to Cypress
Package suffix changed (per Cypress standard)
106948
113520
119445
122675
231055
237630
06/07/01
04/10/02
10/16/02
12/14/02
See ECN
See ECN
IKA
*A
DMG
RGL
RBI
*B
Corrected the values in the Absolute Maximum Ratings to match the device.
Added power up requirements to operating conditions information.
Added Lead Free Devices
*C
*D
*E
RGL
RGL
Minor Change: Added letter C in the ordering for Lead Free
Document #: 38-07020 Rev. *E
Page 8 of 8
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