MRF174 [TE]
N-CHANNEL MOS BROADBAND RF POWER FET; N沟道MOS宽带射频功率场效应管
| 型号： | MRF174 |
| 厂家： | 
TE CONNECTIVITY |
| 描述： | N-CHANNEL MOS BROADBAND RF POWER FET |
| 文件： | 总9页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SEMICONDUCTOR TECHNICAL DATA
by MRF174/D
The RF MOSFET Line
N–Channel Enhancement–Mode
Designed primarily for wideband large–signal output and driver stages up to
200 MHz frequency range.
•
Guaranteed Performance at 150 MHz, 28 Vdc
Output Power = 125 Watts
Minimum Gain = 9.0 dB
Efficiency = 50% (Min)
Excellent Thermal Stability, Ideally Suited For Class A
Operation
125 W, to 200 MHz
N–CHANNEL MOS
BROADBAND RF POWER
FET
•
•
•
•
Facilitates Manual Gain Control, ALC and Modulation
Techniques
100% Tested For Load Mismatch At All Phase Angles
With 30:1 VSWR
Low Noise Figure — 3.0 dB Typ at 2.0 A, 150 MHz
D
G
S
CASE 211–11, STYLE 2
MAXIMUM RATINGS
Rating
Symbol
Value
65
Unit
Vdc
Vdc
Drain–Source Voltage
Drain–Gate Voltage
V
DSS
V
DGR
65
(R
= 1.0 MΩ)
GS
Gate–Source Voltage
V
±40
Vdc
Adc
GS
Drain Current — Continuous
I
13
D
Total Device Dissipation @ T = 25°C
Derate above 25°C
P
D
270
1.54
Watts
W/°C
C
Storage Temperature Range
Operating Junction Temperature
THERMAL CHARACTERISTICS
T
–65 to +150
200
°C
°C
stg
T
J
Characteristic
Thermal Resistance, Junction to Case
Symbol
Max
Unit
R
0.65
°C/W
θJC
Handling and Packaging — MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and
packaging MOS devices should be observed.
REV 7
1
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted.)
C
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage (V
= 0, I = 50 mA)
V
(BR)DSS
65
—
—
—
—
—
—
10
Vdc
mAdc
µAdc
GS
D
Zero Gate Voltage Drain Current (V
= 28 V, V
= 0)
I
DS
GS
= 0)
DS
DSS
GSS
Gate–Source Leakage Current (V
= 20 V, V
I
1.0
GS
ON CHARACTERISTICS
Gate Threshold Voltage (V
DS
= 10 V, I = 100 mA)
V
1.0
3.0
2.5
6.0
—
Vdc
D
GS(th)
Forward Transconductance (V
DS
= 10 V, I = 3.0 A)
g
fs
1.75
mhos
D
DYNAMIC CHARACTERISTICS
Input Capacitance (V
DS
= 28 V, V
GS
= 0, f = 1.0 MHz)
= 0, f = 1.0 MHz)
= 0, f = 1.0 MHz)
C
—
—
—
175
190
40
—
—
—
pF
pF
pF
iss
Output Capacitance (V
= 28 V, V
C
oss
DS
GS
Reverse Transfer Capacitance (V
= 28 V, V
GS
C
rss
DS
FUNCTIONAL CHARACTERISTICS (Figure 1)
Noise Figure
NF
—
9.0
50
3.0
11.8
60
—
—
—
dB
dB
%
(V
DD
= 28 Vdc, I = 2.0 A, f = 150 MHz)
D
Common Source Power Gain
G
ps
(V
DD
= 28 Vdc, P
= 125 W, f = 150 MHz, I
= 125 W, f = 150 MHz, I
= 125 W, f = 150 MHz, I
= 100 mA)
= 100 mA)
= 100 mA,
out
DQ
DQ
DQ
Drain Efficiency
(V = 28 Vdc, P
η
DD
out
Electrical Ruggedness
(V = 28 Vdc, P
ψ
No Degradation in Output Power
DD
out
VSWR 30:1 at all Phase Angles)
L4
R2
C12
C13
+
BIAS
ADJUST
R1
V
–
= 28 V
DD
+
–
C9
C10
C14
C11
R3
D1
RFC1
R4
C3
C2
C8
RF INPUT
RF OUTPUT
L1
C4
L2
L3
C1
DUT
C6
C5
C7
C1 — 15 pF Unelco
L1 — #16 AWG, 1–1/4 Turns, 0.213″ ID
C2 — Arco 462, 5.0–80 pF
C3 — 100 pF Unelco
C4 — 25 pF Unelco
L2 — #16 AWG, Hairpin
0.25″
0.062″
0.47″
0.2″
L3 — #14 AWG, Hairpin
C6 — 40 pF Unelco
C7 — Arco 461, 2.7–30 pF
L4 — 10 Turns #16 AWG Enameled Wire on R1
C5, C8 — Arco 463, 9.0–180 pF
C9, C11, C14 — 0.1 µF Erie Redcap
C10 — 50 µF, 50 V
RFC1 — 18 Turns #16 AWG Enameled Wire, 0.3″ ID
R1 — 10 Ω, 2.0 W
R2 — 1.8 kΩ, 1/2 W
C12, C13 — 680 pF Feedthru
D1 — 1N5925A Motorola Zener
R3 — 10 kΩ, 10 Turn Bourns
R4 — 10 kΩ, 1/4 W
Figure 1. 150 MHz Test Circuit
REV 7
2
140
120
80
70
f = 100 MHz
150 MHz
f = 100 MHz
150 MHz
200 MHz
200 MHz
60
50
40
30
20
10
0
100
80
60
40
20
0
V
I
DQ
= 28 V
= 100 mA
V
I
DQ
= 13.5 V
DD
DD
= 100 mA
12
0
2
4
6
8
10
12
14
28
28
0
2
4
6
8
10
14
16
P , INPUT POWER (WATTS)
P , INPUT POWER (WATTS)
in
in
Figure 2. Output Power versus Input Power
Figure 3. Output Power versus Input Power
160
140
120
100
80
160
140
120
100
80
I
= 100 mA
I
= 100 mA
DQ
f = 100 MHz
DQ
f = 150 MHz
P
= 6 W
4 W
in
P
in
= 12 W
8 W
2 W
4 W
60
60
40
40
20
0
20
0
12
14
16
18
20
22
24
26
12
14
16
18
V , SUPPLY VOLTAGE (VOLTS)
DD
20
22
24
26
28
V
, SUPPLY VOLTAGE (VOLTS)
DD
Figure 4. Output Power versus Supply Voltage
Figure 5. Output Power versus Supply Voltage
160
140
120
100
80
22
20
18
16
14
12
10
8
I
= 100 mA
DQ
f = 200 MHz
P
= 125 W
= 28 V
= 100 mA
out
P
in
= 16 W
12 W
V
DD
DQ
I
8 W
60
40
6
20
0
4
2
12
14
16
18
20
22
24
26
20
40
60
80 100 120 140 160 180 200 220
f, FREQUENCY (MHz)
V
, SUPPLY VOLTAGE (VOLTS)
DD
Figure 6. Output Power versus Supply Voltage
Figure 7. Power Gain versus Frequency
REV 7
3
160
140
120
100
80
5
4
3
2
1
0
f = 150 MHz
= CONSTANT
P
in
V
= 10 V
DS
I
V
= 100 mA
DQ
= 28 V
DD
60
TYPICAL DEVICE SHOWN, V
GS(th)
= 3 V
40
20
0
TYPICAL DEVICE SHOWN, V
GS(th)
= 3 V
–14 –12 –10
–8
–6 –4
–2
0
2
4
6
1
2
3
4
5
6
V , GATE–SOURCE VOLTAGE (VOLTS)
GS
V , GATE–SOURCE VOLTAGE (VOLTS)
GS
Figure 8. Output Power versus Gate Voltage
Figure 9. Drain Current versus Gate Voltage
(Transfer Characteristics)
1000
900
800
700
600
1.2
1.1
V
= 0 V
GS
f = 1 MHz
V
= 28 V
3 A
DD
I = 4 A
D
1
500
400
300
200
100
0
2 A
100 mA
150
C
oss
0.9
C
iss
C
rss
0.8
0
4
8
12
16
20
24
28
–25
0
25
50
75
100
125
175
V , DRAIN–SOURCE VOLTAGE (VOLTS)
DS
T , CASE TEMPERATURE (°C)
C
Figure 10. Gate–Source Voltage versus
Case Temperature
Figure 11. Capacitance versus Drain Voltage
20
10
6
4
T = 25°C
C
2
1
0.6
0.4
0.2
1
2
4
6
10
20
40 60
100
V , DRAIN–SOURCE VOLTAGE (VOLTS)
DS
Figure 12. DC Safe Operating Area
REV 7
4
S
11
S
21
S
12
S
22
f
(MHz)
|S
11
|
φ
|S
21
|
φ
|S
12
|
φ
|S
22
|
φ
2.0
5.0
10
0.932
0.923
0.921
0.921
0.921
0.921
0.922
0.923
0.924
0.925
0.927
0.930
0.930
0.931
0.942
0.936
0.938
0.938
0.940
0.942
0.942
0.952
0.950
0.942
0.943
0.946
0.952
0.958
0.956
0.960
0.956
0.955
–133
74.0
31.6
112
0.011
0.011
0.011
0.011
0.011
0.012
0.012
0.012
0.013
0.013
0.014
0.016
0.018
0.019
0.019
0.021
0.021
0.022
0.023
0.024
0.026
0.027
0.029
0.030
0.032
0.033
0.035
0.036
0.038
0.039
0.042
0.043
23
0.835
0.886
0.896
0.899
0.900
0.901
0.902
0.903
0.904
0.906
0.907
0.910
0.912
0.914
0.919
0.921
0.922
0.923
0.923
0.924
0.928
0.929
0.934
0.933
0.939
0.941
0.943
0.946
0.943
0.946
0.944
0.947
–151
–160
–170
–175
–177
–177
–178
–178
–178
–178
–178
–178
–178
–178
–178
–178
–178
–178
–178
–178
–178
–178
–178
–178
–178
–177
–177
–177
–177
–177
–178
–178
98
93
88
86
83
81
79
77
75
73
71
70
68
67
66
65
64
63
61
60
59
57
56
56
55
54
53
52
52
51
50
12
10
12
16
21
26
30
34
39
43
45
46
47
49
50
53
53
54
56
59
58
61
61
62
64
64
65
67
68
68
68
–168
–174
–177
–178
–178
–178
–178
–178
–178
–178
–178
–178
–178
–178
–178
–178
–178
–177
–177
–177
–177
–177
–177
–177
–177
–177
–177
–177
–177
–177
–177
16.0
20
8.00
30
5.32
40
3.98
50
3.17
60
2.63
70
2.24
80
1.95
90
1.72
100
110
120
130
140
150
160
170
180
190
200
210
220
230
240
250
260
270
280
290
300
1.50
1.31
1.19
1.10
1.01
0.936
0.879
0.830
0.780
0.737
0.705
0.668
0.626
0.592
0.566
0.545
0.523
0.500
0.481
0.460
0.443
Table 1. Common Source Scattering Parameters
= 28 V, I = 3.0 A
V
DS
D
REV 7
5
+j50
+90°
+j25
+j100
+60°
+120°
300
250
+j150
+30°
+150°
+j10
200
150
100
50
f = 30 MHz
+j250
+j500
.05
10
25
50
100 150
250 500
300
.04
.03
.02
.01
0
180°
0°
f = 30 MHz
–j500
–j250
–j150
–j10
–30°
–150°
–j100
–j25
–60°
–120°
–90°
–j50
Figure 13. S , Input Reflection Coefficient
11
Figure 14. S , Reverse Transmission Coefficient
12
versus Frequency
versus Frequency
V
= 28 V, I = 3.0 A
V
= 28 V, I = 3.0 A
DS
D
DS
D
+j50
+90°
f = 30 MHz
+j25
+j100
+60°
+120°
+j150
50
+30°
+150°
+j10
0
+j250
+j500
100
150
300
25
50
100 150
250 500
f = 30 MHz
300
5
4
3
2
1
180°
0°
–j500
–j250
–j150
–j10
–30°
–150°
–j100
–j25
–60°
–120°
–j50
–90°
Figure 15. S , Forward Transmission Coefficient
21
Figure 16. S , Output Reflection Coefficient
22
versus Frequency
versus Frequency
V
= 28 V, I = 3.0 A
V
= 28 V, I = 3.0 A
DS D
DS
D
REV 7
6
150
30
f = 200 MHz
f = 200 MHz
100
150
100
P
out
= 125 W, V = 28 V
DD
DQ
Z
in
I
= 100 mA
Z
*
OL
f
Z
in
Ohms
Z *
OL
Ohms
MHz
30
Z = 10 Ω
o
30
2.90 – j3.95 2.95 – j3.90
1.25 – j2.90 1.85 – j1.05
1.18 – j1.40 1.72 – j0.05
1.30 – j0.90 1.70 + j0.25
100
150
200
Z
* = Conjugate of the optimum load impedance
* = into which the device output operates at a
* = given output power, voltage and frequency.
OL
Z
OL
Z
OL
Figure 17. Series Equivalent Input/Output Impedance, Z , Z
in OL
*
REV 7
7
DESIGN CONSIDERATIONS
terized at I
= 100 mA, which is the suggested minimum
. For special applications such as linear amplifi-
may have to be selected to optimize the critical
DQ
The MRF174 is a RF power N–Channel enhancement
mode field–effect transistor (FET) designed especially for
UHF power amplifier and oscillator applications. M/A-COM RF
MOSFETs feature a vertical structure with a planar design,
thus avoiding the processing difficulties associated with V–
groove vertical power FETs.
M/A-COM Application Note AN211A, FETs in Theory and
Practice, is suggested reading for those not familiar with the
construction and characteristics of FETs.
value of I
DQ
cation, I
DQ
parameters.
The gate is a dc open circuit and draws no current. There-
fore, the gate bias circuit may generally be just a simple re-
sistive divider network. Some special applications may
require a more elaborate bias system.
GAIN CONTROL
Power output of the MRF174 may be controlled from its
rated value down to zero (negative gain) by varying the dc
gate voltage. This feature facilitates the design of manual
gain control, AGC/ALC and modulation systems. (See
Figure 8.)
The major advantages of RF power FETs include high
gain, low noise, simple bias systems, relative immunity from
thermal runaway, and the ability to withstand severely mis-
matched loads without suffering damage. Power output can
be varied over a wide range with a low power dc control sig-
nal, thus facilitating manual gain control, ALC and modula-
tion.
AMPLIFIER DESIGN
Impedance matching networks similar to those used with
bipolar UHF transistors are suitable for MRF174. See
M/A-COM Application Note AN721, Impedance Matching Net-
works Applied to RF Power Transistors. The higher input
impedance of RF MOSFETs helps ease the task of broad-
band network design. Both small signal scattering parame-
ters and large signal impedances are provided. While the
s–parameters will not produce an exact design solution for
high power operation, they do yield a good first approxima-
tion. This is an additional advantage of RF MOS power FETs.
DC BIAS
The MRF174 is an enhancement mode FET and, there-
fore, does not conduct when drain voltage is applied. Drain
current flows when a positive voltage is applied to the gate.
See Figure 9 for a typical plot of drain current versus gate
voltage. RF power FETs require forward bias for optimum
performance. The value of quiescent drain current (I
not critical for many applications. The MRF174 was charac-
) is
DQ
REV 7
8
PACKAGE DIMENSIONS
A
U
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
M
1
INCHES
DIM MIN MAX
0.990 24.39
MILLIMETERS
M
Q
MIN
MAX
25.14
12.95
6.98
5.96
2.79
4.52
0.17
–––
4
A
B
C
D
E
0.960
0.465
0.229
0.216
0.084
0.144
0.003
0.435
0.510
0.275
0.235
0.110
0.178
0.007
–––
11.82
5.82
5.49
2.14
3.66
0.08
11.05
R
B
H
J
2
3
K
M
Q
R
U
D
45 NOM
45 NOM
K
0.115
0.246
0.720
0.130
0.255
0.730 18.29
2.93
6.25
3.30
6.47
18.54
J
STYLE 2:
PIN 1. SOURCE
C
H
E
SEATING
PLANE
2. GATE
3. SOURCE
4. DRAIN
CASE 211–11
ISSUE N
Specifications subject to change without notice.
n North America: Tel. (800) 366-2266, Fax (800) 618-8883
n Asia/Pacific: Tel.+81-44-844-8296, Fax +81-44-844-8298
n Europe: Tel. +44 (1344) 869 595, Fax+44 (1344) 300 020
Visit www.macom.com for additional data sheets and product information.
REV 7
9
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