MRF175GU1111 [TE]
N-CHANNEL MOS BROADBAND RF POWER FETs; N沟道MOS宽带射频功率FET
| 型号： | MRF175GU1111 |
| 厂家： | 
TE CONNECTIVITY |
| 描述： | N-CHANNEL MOS BROADBAND RF POWER FETs |
| 文件： | 总10页 (文件大小：209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SEMICONDUCTOR TECHNICAL DATA
by MRF176GU/D
The RF MOSFET Line
R
F
P
o
w
e
r
M
R
F
1
7
6
G
U
F
i
e
l
d
-
E
f
f
e
c
t
T
r
a
n
s
i
s
t
o
r
s
M
R
F
1
7
6
G
V
N–Channel Enhancement–Mode
Designed for broadband commercial and military applications using push pull
circuits at frequencies to 500 MHz. The high power, high gain and broadband
performance of these devices makes possible solid state transmitters for FM
broadcast or TV channel frequency bands.
200/150 W, 50 V, 500 MHz
N–CHANNEL MOS
BROADBAND
•
Electrical Performance
RF POWER FETs
MRF176GU @ 50 V, 400 MHz (“U” Suffix)
Output Power — 150 Watts
Power Gain — 14 dB Typ
D
Efficiency — 50% Typ
MRF176GV @ 50 V, 225 MHz (“V” Suffix)
Output Power — 200 Watts
Power Gain — 17 dB Typ
G
G
S
Efficiency — 55% Typ
(
F
L
A
N
G
E
)
•
•
•
100% Ruggedness Tested At Rated Output Power
Low Thermal Resistance
D
Low Crss — 7.0 pF Typ @ VDS = 50 V
CASE 375–04, STYLE 2
MAXIMUM RATINGS
Rating
Symbol
Value
125
±40
16
Unit
Vdc
Vdc
Adc
Drain–Source Voltage
Gate–Source Voltage
V
DSS
V
GS
Drain Current — Continuous
I
D
Total Device Dissipation @ T = 25°C
P
D
400
Watts
C
Derate above 25°C
2.27
W/°C
Storage Temperature Range
Operating Junction Temperature
THERMAL CHARACTERISTICS
T
–65 to +150
200
°C
°C
stg
T
J
Characteristic
Thermal Resistance, Junction to Case
Symbol
Max
Unit
R
0.44
°C/W
θ
JC
Handling and Packaging — MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and
packaging MOS devices should be observed.
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
C
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS (1)
Drain–Source Breakdown Voltage
(V = 0, I = 100 mA)
V
125
—
—
—
—
—
Vdc
mAdc
µAdc
(BR)DSS
GS
D
Zero Gate Voltage Drain Current
(V = 50 V, V = 0)
I
2.5
1.0
DSS
DS
GS
Gate–Body Leakage Current
(V = 20 V, V = 0)
I
—
GSS
GS
DS
NOTE:
1. Each side of device measured separately.
REV 9
1
ELECTRICAL CHARACTERISTICS — continued (T = 25°C unless otherwise noted)
C
Characteristic
Symbol
Min
Typ
Max
Unit
ON CHARACTERISTICS (1)
Gate Threshold Voltage (V = 10 V, I = 100 mA)
V
1.0
1.0
2.0
3.0
3.0
3.0
6.0
5.0
—
Vdc
Vdc
DS
D
GS(th)
Drain–Source On–Voltage (V = 10 V, I = 5.0 A)
V
DS(on)
GS
D
Forward Transconductance (V = 10 V, I = 2.5 A)
g
fs
mhos
DS
D
DYNAMIC CHARACTERISTICS (1)
Input Capacitance (V = 50 V, V = 0, f = 1.0 MHz)
C
—
—
—
180
100
6.0
—
—
—
pF
pF
pF
DS
GS
iss
Output Capacitance (V = 50 V, V = 0, f = 1.0 MHz)
C
oss
DS
GS
Reverse Transfer Capacitance (V = 50 V, V = 0, f = 1.0 MHz)
C
rss
DS
GS
FUNCTIONAL CHARACTERISTICS — MRF176GV (2) (Figure 1)
Common Source Power Gain
G
15
50
17
55
—
—
dB
%
ps
(V = 50 Vdc, P = 200 W, f = 225 MHz, I = 2.0 x 100 mA)
DD
out
DQ
Drain Efficiency
η
(V = 50 Vdc, P = 200 W, f = 225 MHz, I = 2.0 x 100 mA)
DD
out
DQ
Electrical Ruggedness
(V = 50 Vdc, P = 200 W, f = 225 MHz, I = 2.0 x 100 mA,
ψ
No Degradation in Output Power
DD
out
DQ
VSWR 10:1 at all Phase Angles)
NOTES:
1. Each side of device measured separately.
2. Measured in push–pull configuration.
R
1
+
C
1
0
5
0
V
B
I
A
S
0
-
6
V
C
8
C
9
-
C
3
C
4
D
.
U
.
T
.
R
2
T
2
T
1
C
5
C
1
C
2
C
6
C
7
C1 — Arco 404, 8.0ā –ā 60 pF
C2, C3, C6, C8 — 1000 pF Chip
C4, C9 — 0.1 µF Chip
L2 — Ferrite Beads of Suitable Material
L2 — for 1.5ā –ā 2.0 µH, Total Inductance
R1 — 100 Ohms, 1/2 W
C5 — 180 pF Chip
R2 — 1.0 kOhms, 1/2 W
C7 — Arco 403, 3.0ā –ā 35 pF
T1 — 4:1 Impedance Ratio RF Transformer.
T1 — Can Be Made of 25 Ohm Semirigid
T1 — Co–Ax, 47ā –ā 62 Mils O.D.
T2 — 1:4 Impedance Ratio RF Transformer.
T2 — Can Be Made of 25 Ohm Semirigid
T2 — Co–Ax, 62ā –ā 90 Mils O.D.
C10 — 0.47 µF Chip, Kemet 1215 or Equivalent
L1 — 10 Turns AWG #16 Enameled Wire,
L1 — Close Wound, 1/4″ I.D.
Board material — .062″ fiberglass (G10),
Two sided, 1 oz. copper, ε ^ 5
r
NOTE: For stability, the input transformer T1 should be loaded
NOTE: with ferrite toroids or beads to increase the common
NOTE: mode inductance. For operation below 100 MHz. The
NOTE: same is required for the output transformer.
Unless otherwise noted, all chip capacitors
are ATC Type 100 or Equivalent
Figure 1. 225 MHz Test Circuit
REV 9
2
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
C
Characteristic
Symbol
Min
Typ
Max
Unit
FUNCTIONAL CHARACTERISTICS — MRF176GU (1) (Figure 2)
Common Source Power Gain
G
12
45
14
50
—
—
dB
%
ps
(V = 50 Vdc, P = 150 W, f = 400 MHz, I = 2.0 x 100 mA)
DD
out
DQ
Drain Efficiency
η
(V = 50 Vdc, P = 150 W, f = 400 MHz, I = 2.0 x 100 mA)
DD
out
DQ
Electrical Ruggedness
(V = 50 Vdc, P = 150 W, f = 400 MHz, I = 2.0 x 100 mA,
ψ
No Degradation in Output Power
DD
out
DQ
VSWR 10:1 at all Phase Angles)
NOTE:
1. Measured in push–pull configuration.
A
B
L
7
L 8
C
1
7
C1 8
BIA S
C1 9
5
0
V
C
1
3
C
1
5
C
11
C1 2
R
1
R
2
C
9
L
L
1
2
Z
1
2
Z
3
4
L
L
3
4
C
1
C
C
6
7
B
1
C
3
C
5
C
4
C8
B
2
C1 0
Z
Z
C
2
D. U. T.
L
6
R
3
A
B
C
1
4
C1 6
B1 — Balun, 50 Ω Semirigid Coax .086 OD 2″ Long
B2 — Balun, 50 Ω Semirigid Coax .141 OD 2″ Long
C1, C2, C9, C10 — 270 pF ATC Chip Capacitor
C3 — 15 pF ATC Chip Cap
C4, C8 — 1.0ā –ā 20 pF Piston Trimmer Cap
C5 — 27 pF ATC Chip Cap
L5, L6 — 13T #18 W .250 ID
L7 — Ferroxcube VK–200 20/4B
L8 — 3T #18 W .340 ID
R1 — 1.0 kΩ 1/4 W Resistor
R2, R3 — 10 kΩ 1/4 W Resistor
C6, C7 — 22 pF Mini Unelco Capacitor
C11, C13, C14, C15, C16 — 0.01 µF Ceramic Capacitor
C12 — 1.0 µF 50 V Tantalum Cap
.
4
0
0″
0″
C17, C18 — 680 pF Feedthru Capacitor
.
2
0
0
C19 — 10 µF 100 V Tantalum Cap
L1, L2 — Hairpin Inductor #18 W
L3, L4 — Hairpin Inductor #18 W
Z1, Z2 — Microstrip Line .400L x .250W
Z3, Z4 — Microstrip Line .450L x .250W
.
2
0
.
2
0
0
″
Ckt Board Material — .060″ teflon–fiberglass, copper clad both sides, 2 oz. copper,
ε = 2.55
r
Figure 2. 400 MHz Test Circuit
REV 9
3
TYPICAL CHARACTERISTICS
4
3
2
1
00 0
00 0
00 0
00 0
0
1
0
0
0
1
V
=
3
0
V
D S
1
5
V
1
T
=
°
C
2
5
C
0
1
2
3
4
5
6
7
8
9
1
0
2
1
0
5
0
2 0 0
I
D
,
D
R
A
IN
C
U
R
R
E
N
T
(
AM
P
S
)
V
D S
,
D
R
A
I
N
-
S
O
U
R
C
E
V
O
L
T
A
G
E
(V O LTS)
Figure 3. Common Source Unity Current Gain*
Gain–Frequency versus Drain Current
Figure 4. DC Safe Operating Area
* Data shown applies to each half of MRF176GU/GV
I
N
f
P
U
T
A
N
D
O
U
T
P
U
T
I
M
x
P
E
D
A
0
N
C
E
M
R
F
1
7
6
G
U
/
G
V
V
=
5
0
V,
=
I
2
1
0
mA
D D
D Q
Z
Z *
O L
O HM S
Z
i n
i
n
M
H
z
O
H
M
S
4 00
3
00
(
P
=
=
1
5
0
W
)
ou t
22 5
2
3
4
5
2
0
0
0
5
2
2
.
0
0
8
6
5
-
j
2
1
.
.
5
0
6
4
3
.
.
.
5
0
0
0
0
-
j
j
j
3
3
1
.
5
1
9
0
0
0
0
f =
MH z
5
0
0
M
H
z
f
=
5
00
0
0
0
.
0
5
0
-
+
+
j
j
j
1
0
5
0
8
0
6
-
-
+
.
.
4
0
0
1
1
.
.
0
2
.
7
7
1
5
0
.
2
.
j0 . 1
Z
*
O L
(
P
2
00
W
)
ou t
3
0
0
22 5
10 0
3
0
7
5
3
2
2
.
.
.
.
.
5
5
2
5
0
0
-
-
-
-
-
j
j
j
j
j
6
.
.
.
.
.
5
0
1
7
.
.
0
0
0
-
j
j
4
5
.
.
0 0
0
5
0
0
7
6
4
2
0
0
8
5
0
1
4
0
-
-
-
-
0
2
25
1
0
0
0
5
0
0
5
0
1
1
.
0
0
j5 .2
0
1
2
5
2
0
ă
8
.
.
2
0
0
j
j
5
4
.
.
0
0
0
5
0
1 50
Z
0
*
0
ă
5
0
2
O L
3
0
1
0
0
Z
*
O L
=
C
o
n
j
u
g
a
t
e
o
f
t
h
e
o
p
t
i
m
u
m
l
o
a
d
i
m
pe
d
a
n
c
e
i
n
t
o
w
h
i
c
h
t
he
d
e
v
i
c
e
o u tp u t
a
5
Z
= Ω10
o
o
a
p
e
d
r
a
t
e
s
a
t
a
g
i
v
e
n
o
u
t
p
u
t
p
o
w
e
r,
v
o
l
t
g
e
r
3
0
n
f
r
e
q
u
e
n
c
y
.
N
O
T
E
:
I
n
p
u
t
a
n
d
o
u
t
p
u
t
i
m
p
e
d
a
n
c
e
v
a
l
u
e
s
g
i
v
e
n
a
r
e
m
e
a
s
u
r
e
d
f
r
o
m
g
a
t
e
t
o
g
a
t
e
a
n
d
d
r
a
i
n
t
o
d
r
a
i
n
e
s
p
e
c
t
i
v
e
l
y
.
Figure 5. Series Equivalent Input/Output Impedance
REV 9
4
TYPICAL CHARACTERISTICS
5
0
0
3 0
2 5
2 0
1 5
1 0
5
C
C
is s
2
0
0
5
0
0
0
P
ou t
=
2
0
0
W
os s
1
V
f
=
0
V
z
G S
=
1
MH
1
5
0
W
2
0
V
I
=
5
0
V
D S
=
2
x
1
00
m
A
D Q
C
r s s
1
0
5
0
1
0
2
0
3
0
4
0
5
0
5
1
0
2
0
5
0
1
00
2
00
5 0 0
V
D S
,
D
R
A
IN
-
SO
U
R
C
E
V
O
L
T
A
GE
(
V
O
LT
S
)
f
,
F
R
E
Q
U
E
N
C
Y
(M Hz)
Figure 6. Capacitance versus Drain–Source Voltage*
Figure 7. Power Gain versus Frequency
* Data shown applies to each half of MRF176GU/GV
MRF176GV
3
2
1
0
0
0
0
0
0
3
2
2
2
1
1
2
8
4
0
6
2
8
4
0
0
0
0
0
0
0
I
f
=
2
5
x
1
0
0
mA
D Q
V
=
5
0
V
D D
=
2
2
M
H
z
P
=
6
W
i n
4
0
V
=
4
W
2
W
I
f
2
5
x
1
0
0
2
m
A
D Q
=
2
2
M
H z
0
0
0
0
6
1
3
0
3
2
3
4
3
6
3
8
4
0
4
2
4
4
4
6
4
8
5 0
P ,
in
P
O
W
E
R
I
N
P
U
T
(
WAT
T
S)
V
D S
,
S
U
P
PLY
V
O
L
T
A
G
E
(
V
O
L
T
S
)
Figure 9. Output Power versus Supply Voltage
Figure 8. Power Input versus Power Output
REV 9
5
TYPICAL CHARACTERISTICS
MRF176GU
2 00
1 80
1 60
1 40
1 20
2 00
1 80
1 60
1 40
1 20
f
=
4
0
0
M
H
z
f
=
4
0
0
M
H
z
5
0
0
MH z
5
0
0
M
H
z
1
00
8 0
6 0
4 0
2 0
0
1
00
8 0
6 0
4 0
2 0
0
V
=
4
0
V
V
D D
=
5
0
V
D
D
I
=
2
x
1
0
0
m
A
I
=
2
x
1
0
0
m
A
D Q
D Q
0
2
4
6
8
10
12
1
4
1
6
0
2
4
6
8
1
0
1
2
1
4
1 6
P ,
in
I
N
P
U
T
P
OW
E
R
(
WAT
T
S)
P ,
i n
I
N
P
U
T
P
O
WE
R
(WATTS )
Figure 10. Output Power versus Input Power
Figure 11. Output Power versus Input Power
2
1
1
1
1
0
8
6
4
2
0
0
0
0
0
P
i n
=
1
2
W
8
W
W
4
1
0 0
80
60
40
20
0
I
f
=
2
x 1
MH z
00
mA
D Q
=
4
0
0
2
0
3
0
4
0
5 0
V
D D
,
S
U
P
P
LY
V
O
L
T
A
G
E
(
V
O
L
T
S
)
Figure 12. Output Power versus Supply Voltage
REV 9
6
NOTE: S–Parameter data represents measurements taken from one chip only.
Table 1. Common Source S–Parameters (VDS = 50 V, ID = 0.35 A)
S
11
S
21
S
12
S
22
f
|S
|
φ
–159
–163
–166
–167
–168
–169
–170
–171
–171
–172
–172
–173
–173
–174
–174
–175
–175
–176
–176
–176
–177
–177
–178
–178
–178
–179
–179
–180
–180
180
|S
|
φ
|S
|
φ
|S |
22
φ
MHz
11
21
12
30
0.804
0.851
0.846
0.842
0.846
0.858
0.875
0.890
0.902
0.909
0.915
0.920
0.924
0.928
0.934
0.940
0.945
0.950
0.953
0.955
0.956
0.958
0.960
0.963
0.965
0.967
0.968
0.969
0.970
0.971
0.973
0.973
0.974
0.975
0.975
0.976
0.976
0.976
0.977
0.978
17.80
12.50
10.40
8.45
7.28
6.13
5.36
4.61
4.04
3.41
2.92
2.61
2.41
2.24
2.10
1.96
1.78
1.56
1.36
1.22
1.14
1.08
1.05
1.01
0.96
0.87
0.78
0.72
0.68
0.65
0.61
0.61
0.58
0.55
0.50
0.47
0.44
0.42
0.40
0.39
87
0.018
0.018
0.018
0.017
0.017
0.016
0.015
0.014
0.013
0.012
0.011
0.010
0.009
0.008
0.007
0.008
0.007
0.006
0.005
0.004
0.004
0.004
0.005
0.006
0.005
0.005
0.005
0.006
0.008
0.009
0.009
0.008
0.008
0.010
0.013
0.013
0.012
0.010
0.011
0.015
–1
0.602
0.606
0.610
0.652
0.708
0.786
0.883
0.916
0.919
0.857
0.819
0.816
0.858
0.951
1.046
1.130
1.120
1.030
0.940
0.900
0.940
0.940
1.010
1.120
1.160
1.150
1.030
0.964
0.926
0.940
0.980
1.053
1.095
1.135
1.086
1.045
0.979
0.940
1.015
1.038
–149
–147
–149
–154
–157
–159
–158
–157
–158
–156
–157
–160
–162
–164
–164
–163
–165
–165
–165
–164
–167
–170
–169
–170
–172
–172
–171
–170
–169
–172
–173
–175
–174
–173
–175
–175
–174
–174
–175
–177
40
77
70
67
65
63
59
53
46
41
39
38
38
38
35
30
24
22
20
21
21
22
21
18
13
10
8
–9
–14
–16
–15
–15
–17
–22
–29
–31
–29
–24
–20
–21
–24
–23
–18
–8
50
60
70
80
90
100
110
120
130
140
150
160
170
180
190
200
210
220
230
240
250
260
270
280
290
300
310
320
330
340
350
360
370
380
390
400
410
420
2
7
6
13
29
44
55
57
47
8
46
11
11
10
11
7
58
72
179
83
179
82
179
70
178
3
61
178
1
65
178
–1
1
74
177
84
177
4
84
177
4
71
176
4
67
REV 9
7
Table 1. Common Source S–Parameters (VDS = 50 V, ID = 0.35 A) continued
S
11
S
21
S
12
S
22
f
|S
|
φ
176
176
176
175
175
175
174
174
172
169
166
164
161
|S
|
φ
|S
|
φ
|S |
22
φ
–178
–178
–177
–178
–178
–176
–178
–179
178
MHz
11
21
12
430
440
450
460
470
480
490
500
600
700
800
900
1000
0.978
0.979
0.979
0.979
0.979
0.979
0.980
0.981
0.972
0.971
0.971
0.972
0.972
0.38
0.37
0.37
0.32
0.30
0.30
0.29
0.28
0.24
0.15
0.13
0.10
0.08
3
0
0.017
0.017
0.015
0.013
0.015
0.019
0.021
0.021
0.012
0.027
0.022
0.032
0.030
74
1.073
1.091
1.107
1.118
1.003
0.975
0.963
0.993
0.943
0.999
0.977
0.972
0.999
83
86
71
60
66
80
92
93
75
70
73
83
–2
–6
–5
–3
–1
0
–5
–8
–9
–5
–9
176
174
172
169
RF POWER MOSFET CONSIDERATIONS
MOSFET CAPACITANCES
the small signal unity current gain frequency at a given drain
current level. This is equivalent to fT for bipolar transistors.
Since this test is performed at a fast sweep speed, heating of
the device does not occur. Thus, in normal use, the higher
temperatures may degrade these characteristics to some ex-
tent.
The physical structure of a MOSFET results in capacitors
between the terminals. The metal oxide gate structure deter-
mines the capacitors from gate–to–drain (Cgd), and gate–to–
source (Cgs). The PN junction formed during the fabrication
of the MOSFET results in a junction capacitance from drain–
to–source (Cds).
These capacitances are characterized as input (Ciss), out-
put (Coss) and reverse transfer (Crss) capacitances on data
sheets. The relationships between the inter–terminal capaci-
tances and those given on data sheets are shown below. The
DRAIN CHARACTERISTICS
One figure of merit for a FET is its static resistance in the
full–on condition. This on–resistance, VDS(on), occurs in the
linear region of the output characteristic and is specified un-
der specific test conditions for gate–source voltage and drain
current. For MOSFETs, VDS(on) has a positive temperature
coefficient and constitutes an important design consideration
at high temperatures, because it contributes to the power
dissipation within the device.
C
iss can be specified in two ways:
1. Drain shorted to source and positive voltage at the gate.
2. Positive voltage of the drain in respect to source and zero
volts at the gate. In the latter case the numbers are lower.
However, neither method represents the actual operat-
ing conditions in RF applications.
GATE CHARACTERISTICS
The gate of the MOSFET is a polysilicon material, and is
electrically isolated from the source by a layer of oxide. The
input resistance is very high — on the order of 109 ohms —
resulting in a leakage current of a few nanoamperes.
Gate control is achieved by applying a positive voltage
slightly in excess of the gate–to–source threshold voltage,
D
R
A
IN
C
g d
G
AT
E
C
C
C
=
C
+
C
gs
is s
g d
C
=
C
+
C
ds
d
s
os s
r s s
g d
=
C
g d
VGS(th)
.
C
Gate Voltage Rating — Never exceed the gate voltage
rating (or any of the maximum ratings on the front page). Ex-
ceeding the rated VGS can result in permanent damage to
the oxide layer in the gate region.
Gate Termination — The gates of this device are essen-
tially capacitors. Circuits that leave the gate open–circuited
or floating should be avoided. These conditions can result in
turn–on of the devices due to voltage build–up on the input
capacitor due to leakage currents or pickup.
g s
S
O
U
R
C
E
The Ciss given in the electrical characteristics table was
measured using method 2 above. It should be noted that
iss, Coss, Crss are measured at zero drain current and are
provided for general information about the device. They are
not RF design parameters and no attempt should be made to
use them as such.
C
Gate Protection — This device does not have an internal
monolithic zener diode from gate–to–source. The addition of
an internal zener diode may result in detrimental effects on
the reliability of a power MOSFET. If gate protection is re-
quired, an external zener diode is recommended.
LINEARITY AND GAIN CHARACTERISTICS
In addition to the typical IMD and power gain, data pre-
sented in Figure 3 may give the designer additional informa-
tion on the capabilities of this device. The graph represents
REV 9
8
HANDLING CONSIDERATIONS
DESIGN CONSIDERATIONS
The gate of the MOSFET, which is electrically isolated
from the rest of the die by a very thin layer of SiO2, may be
damaged if the power MOSFET is handled or installed im-
properly. Exceeding the 40 V maximum gate–to–source volt-
age rating, VGS(max), can rupture the gate insulation and
destroy the FET. RF Power MOSFETs are not nearly as sus-
ceptible as CMOS devices to damage due to static discharge
because the input capacitances of power MOSFETs are
much larger and absorb more energy before being charged
to the gate breakdown voltage. However, once breakdown
begins, there is enough energy stored in the gate–source ca-
pacitance to ensure the complete perforation of the gate ox-
ide. To avoid the possibility of device failure caused by static
discharge, precautions similar to those taken with small–sig-
nal MOSFET and CMOS devices apply to power MOSFETs.
When shipping, the devices should be transported only in
antistatic bags or conductive foam. Upon removal from the
packaging, careful handling procedures should be adhered
to. Those handling the devices should wear grounding straps
and devices not in the antistatic packaging should be kept in
metal tote bins. MOSFETs should be handled by the case
and not by the leads, and when testing the device, all leads
should make good electrical contact before voltage is ap-
plied. As a final note, when placing the FET into the system it
is designed for, soldering should be done with grounded
equipment.
The gate of the power MOSFET could still be in danger af-
ter the device is placed in the intended circuit. If the gate may
see voltage transients which exceed VGS(max), the circuit de-
signer should place a 40 V zener across the gate and source
terminals to clamp any potentially destructive spikes. Using a
resistor to keep the gate–to–source impedance low also
helps damp transients and serves another important func-
tion. Voltage transients on the drain can be coupled to the
gate through the parasitic gate–drain capacitance. If the
gate–to–source impedance and the rate of voltage change
on the drain are both high, then the signal coupled to the gate
may be large enough to exceed the gate–threshold voltage
and turn the device on.
The MRF176G is a RF power N–channel enhancement
mode field–effect transistor (FETs) designed for VHF and
UHF power amplifier applications. M/A-COM RF MOSFETs
feature a vertical structure with a planar design, thus avoid-
ing the processing difficulties associated with V–groove
MOS power FETs.
M/A-COM Application Note AN211A, FETs in Theory and
Practice, is suggested reading for those not familiar with the
construction and characteristics of FETs.
The major advantages of RF power FETs include high
gain, low noise, simple bias systems, relative immunity from
thermal runaway, and the ability to withstand severely mis-
matched loads without suffering damage. Power output can
be varied over a wide range with a low power dc control sig-
nal, thus facilitating manual gain control, ALC and modula-
tion.
DC BIAS
The MRF176G is an enhancement mode FET and, there-
fore, does not conduct when drain voltage is applied. Drain
current flows when a positive voltage is applied to the gate.
RF power FETs require forward bias for optimum perfor-
mance. The value of quiescent drain current (IDQ) is not criti-
cal for many applications. The MRF176G was characterized
at IDQ = 100 mA, each side, which is the suggested minimum
value of IDQ. For special applications such as linear amplifi-
cation, IDQ may have to be selected to optimize the critical
parameters.
The gate is a dc open circuit and draws no current. There-
fore, the gate bias circuit may be just a simple resistive divid-
er network. Some applications may require a more elaborate
bias system.
GAIN CONTROL
Power output of the MRF176G may be controlled from its
rated value down to zero (negative gain) by varying the dc
gate voltage. This feature facilitates the design of manual
gain control, AGC/ALC and modulation systems.
REV 9
9
PACKAGE DIMENSIONS
N O TE S :
1. D I MEN S IO N I N G A ND TO LE R A N C IN G PE R AN S I
Y 14. 5M, 198 2.
U
G
Q RADIUS 2 PL
M
M
M
B
0
.2
5
ꢀ
(
0
.
01
0
)
T
A
2. C O N TR O LL IN G D I MEN S I ON : I N C H .
1
2
INCHES
DIM MIN MAX
MILLIMETERS
MIN
33. 79
9. 40
4. 83
5. 47
1. 27
10. 92
2. 59
0. 11
4. 83
21. 46
1. 52
9. 91
MAX
3 4. 29
1 0. 41
5 .8 4
5 .9 6
1 .7 7
11 .1 8
2 .8 4
0 .1 5
5 .3 3
A
B
C
D
E
G
H
J
1. 330
0. 370
0. 190
0. 215
0. 050
0. 430
0. 102
0. 004
0. 185
0. 845
0. 060
0. 390
1. 350
0. 410
0. 230
0. 235
0. 070
0. 440
0. 112
0. 006
0. 215
0. 875
0. 070
0. 410
–B–
R
5
3
4
K
D
K
N
Q
R
U
2 2. 23
1 .7 8
1 0. 41
J
N
E
1. 100 ꢀB SC
27. 94ꢀ BSC
S
T
Y
L
E
2
:
H
P IN 1. D R AI N
2. D R AI N
3. G AT E
4. G AT E
5. S OU R C E
SEATING
PLANE
–T–
–A–
C
CASE 375–04
ISSUE D
Specifications subject to change without notice.
n North America: Tel. (800) 366-2266, Fax (800) 618-8883
n Asia/Pacific: Tel.+81-44-844-8296, Fax +81-44-844-8298
n Europe: Tel. +44 (1344) 869 595, Fax+44 (1344) 300 020
Visit www.macom.com for additional data sheets and product information.
REV 9
10
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