TDA7345D [STMICROELECTRONICS]
DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX; 环绕声矩阵数字控制音频处理器
| 型号： | TDA7345D |
| 厂家： | 
ST |
| 描述： | DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX |
| 文件： | 总18页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDA7345
DIGITALLY CONTROLLED AUDIO PROCESSOR
WITH SURROUND SOUND MATRIX
1 STEREO INPUT
VOLUMECONTROL IN 1.25dB STEP
TREBLE AND BASS CONTROL
THREE SURROUND MODES ARE AVAIL-
ABLE:
– MOVIE, MUSIC AND SIMULATED
FOUR SPEAKER ATTENUATORS:
– 4 INDEPENDENT SPEAKERSCONTROL
IN 1.25dBSTEPS FOR BALANCE FACILITY
– INDEPENDENTMUTE FUNCTION
SO28
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL BUS
ORDERING NUMBER:
TDA7345D
DESCRIPTION
The TDA7345 is a volume tone (bass and treble)
balance (Left/Right) processor for quality audio
applications in car radio and Hi-Fi systems.
works and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOSTechnology,
Low Distortion, Low Noise and DC stepping are
obtained.
It reproduces surround sound by using phase
shifters and a signal matrix. Control of all the
functionsis accomplished by serial bus.
The AC signal setting is obtained by resistor net-
PIN CONNECTION
CREF
PS2
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vs
2
PS3
PS1
3
PS4
LP1
4
LP
HP1
5
REAR IN
REAR OUT
R-in
HP2
6
L-in
7
BASS-LA
BASS-LB
TREBLE-L
REC_OUT_L
REC_OUT_R
Lout
8
BASS-RA
BASS-RB
TREBLE-R
DIG GND
SDA
9
10
11
12
13
14
SCL
Rout
AGND
D94AU191A
1/18
November 1999
TDA7345
BLOCK DIAGRAM
4DU19A2
B A S S - L B
B A S S - R B
2/18
TDA7345
TEST CIRCUIT
5.6nF C15 100nF C14 100nF C13 22µF C3
10µF C1 100nF C2 22nF C4 22nF C5
LP1
PS1
PS2
CREF
V
PS3
PS4
S
4
3
2
1
28
27
26
25
HP1
LP
5
6
7
680nF
C16
1.2nF
C6
REAR IN
HP2
L-in
24
0.47µF
C17
2.2µF
REAR OUT
23
22
0.47µF C7
R-in
TDA7345
C20 100nF
C10 100nF
8
9
21
20
BASS-LA
C21 100nF
BASS-RA
C11 100nF
BASS-LB
BASS-RB
R2
R1
5.6K
5.6K
TREBLE-L
5.6nF
C22
TREBLE-R
10
19
5.6nF
C12
11
12
13
14
15
16
17
SDA
18
D94AU193A
REC OUT L REC OUT R LOUT
ROUT AGND
SCL
DIG GND
THERMAL DATA
Symbol
Description
Value
Unit
Rth j-pins
Thermal Resistance Junction-pins
Max.
85
C/W
°
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
VS
Tamb
Tstg
Operating Supply Voltage
11
Operating Ambient Temperature
Storage Temperature Range
-10 to 85
°C
°C
-55 to +150
QUICK REFERENCE DATA
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
VS
VCL
THD
S/N
SC
Supply Voltage
7
2
9
10.5
Max. input signal handling
Vrms
%
Total Harmonic Distortion V = 1Vrms f = 1KHz
Signal to Noise Ratio V out = 1Vrms (made = OFF)
Channel Separation f = 1KHz
0.02
106
70
0.1
dB
dB
dB
dB
dB
dB
dB
dB
Volume Control 1.25dB step
-78.75
-14
0
+14
+14
0
Treble Control (2db step)
Bass Control (2db step)
-14
Balance Control 1.25dB step REC-OUT L & R
-38.75
-78.75
Balance Control 1.25dB step (LOUT, ROUT
)
0
Mute Attenuation
90
3/18
TDA7345
ELECTRICAL CHARACTERISTICS
RG = 600 , all controls flat (G = 0),Effect Ctrl = -6dB, MODE = OFF; f = 1KHz
unless otherwise specified)
Ω
(refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10K ,
Ω
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY
VS
IS
Supply Voltage
7
9
10.5
35
V
Supply Current
Ripple Rejection
20
60
25
80
mA
dB
SVR
LCH / RCH out, Mode = OFF
INPUT STAGE
RII
Input Resistance
35
2
50
2.5
65
KΩ
Vrms
Vrms
dB
VCL
Clipping Level
THD = 0.3%; Lin or Rin
THD = 0.3%; Rin + Lin (2)
3.0
CRANGE
AVMIN
AVMAX
ASTEP
VDC
Control Range
Min. Attenuation
Max. Attenuation
Step Resolution
DC Steps
19.68
0
-1
18.68
0.11
-3
1
20.68
0.51
3
dB
19.68
0.31
0
dB
dB
adjacent att. step
mV
VOLUME CONTROL
CRANGE
AVMIN
AVMAX
ASTEP
EA
Control Range
70
-1
75
0
dB
dB
dB
dB
Min. Attenuation
Max. Attenuation
Step Resolution
1
70
0.5
75
1.25
0
Av = 0 to -40dB
1.75
Attenuation Set Error
Av = 0 to -20dB
Av = -20 to -60dB
-1.5
-3
1.5
2
dB
dB
ET
Tracking Error
DC Steps
2
3
dB
VDC
adjacent attenuation steps
Max. Boost/cut
-3
0
mV
BASS CONTROL (1)
Gb
BSTEP
RB
Control Range
+11.5
1
+14.0
2
+16.0
3
dB
dB
KΩ
Step Resolution
Internal Feedback Resistance
32
44
56
TREBLE CONTROL (1)
Gt
Control Range
Max. Boost/cut
+13
1
+14
2
+15
3
dB
dB
TSTEP
Step Resolution
EFFECT CONTROL
CRANGE
SSTEP
Control Range
Step Resolution
- 21
0.5
- 6
dB
dB
1
1.5
4/18
TDA7345
ELECTRICAL CHARACTERISTICS
(continued)
SURROUND SOUND MATRIX
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
GOFF
In-phase Gain (OFF)
Mode OFF, Input signal of
1kHz, 1.4 Vp-p, Rin → Rout
Lin → Lout
-1.5
0
1.5
dB
DGOFF
GMOV1
GMOV2
DGMOV
GMUS1
GMUS2
DGMUS
LMON1
LMON2
LMON3
RMON1
RMON2
RMON3
LR In-phase Gain Difference
(OFF)
Mode OFF, Input signal of
1kHz, 1.4 Vp-p
-1.5
0
7
1.5
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
(Rin → Rout), (L → Lout
)
in
In-phase Gain (Movie 1)
In-phase Gain (Movie 2)
Movie mode, Effect Ctrl = -6dB
Input signal of 1kHz, 1.4 Vp-p
R
in → Rout, Lin → Lout
Movie mode, Effect Ctrl = -6dB
Input signal of 1kHz, 1.4 Vp-p
8
Rin
Rout, Lin
L
→
out
→
LR In-phase Gain Diffrence
(Movie)
Movie mode, Effect Ctrl = -6dB
Input signal of 1kHz, 1.4 Vp-p
0
(Rin → Rout) – (L → Lout
)
in
In-phase Gain (Music 1)
In-phase Gain (Music 2)
Music mode, Effect Ctrl = -6dB
Input signal of 1kHz, 1.4 Vp-p
6
(Rin → Rout) – (L → Lout
)
in
Music mode, Effect Ctrl = -6dB
Input signal of 1kHz, 1.4 Vp-p
7.5
0
R
in → Rout, Lin → Lout
LR In-phase Gain Difference
(Music)
Music mode, Effect Ctrl = -6dB
Input signal of 1kHz, 1.4 Vp-p
(Rin
R
out) – (L
L )
→
out
→
in
Simulated L Output 1
Simulated L Output 2
Simulated L Output 3
Simulated R Output 1
Simulated R Output 2
Simulated R Output 3
Simulated Mode, EffectCtrl= -6dB
Input signal of 250Hz,
4.5
– 4.0
7.0
– 4.5
3.8
– 20
1.4 Vp-p, R and Lin
L
out
→
in
Simulated Mode, EffectCtrl= -6dB
Input signal of 1kHz,
1.4 Vp-p, R and Lin → Lout
in
Simulated Mode, EffectCtrl= -6dB
Input signal of 3.6kHz,
1.4 Vp-p, R and Lin → Lout
in
Simulated Mode, EffectCtrl= -6dB
Input signal of 250Hz,
1.4 Vp-p, R and Lin →Rout
in
Simulated Mode, EffectCtrl= -6dB
Input signal of 1kHz,
1.4 Vp-p, R and Lin
R
→
in
out
Simulated Mode, EffectCtrl= -6dB
Input signal of 3.6kHz,
1.4 Vp-p, R and Lin → Rout
in
RLP1
RPS1
RPS2
RPS3
RPS2
RHPI
RLPF
Low Pass Filter Resistance
Phase Shifter 1 Resistance
Phase Shifter 2 Resistance
Phase Shifter 3 Resistance
Phase Shifter 4 Resistance
High Pass Filter Resistance
LP Pin Impedance
7.5
13.5
0.30
13.6
13.6
45
10
17.95
0.40
18.08
18.08
60
12.5
22.5
0.50
22.6
22.6
75
K
Ω
k
Ω
KΩ
KΩ
KΩ
KΩ
7.5
10
12.5
K
Ω
5/18
TDA7345
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SPEAKER ATTENUATORS (REC_OUT_L, REC_OUT_R)
Crange
SSTEP
EA
Control Range
35
0.5
-1.5
80
37.5
1.25
40
1.75
1.5
dB
dB
dB
dB
mV
Step Resolution
Attenuation set error
Output Mute Attenuation
DC Steps
AMUTE
VDC
90
0
adjacent att. steps
-3
3
SPEAKER ATTENUATORS (LOUT, ROUT)
Crange
SSTEP
EA
Control Range
70
0.5
-1.5
-3
75
1.25
0
dB
dB
dB
dB
mV
dB
Step Resolution
Attenuation set error
Av = 0 to -40dB
Av = 0 to 20dB
1.75
1.5
2
Av = -20 to -60dB
adjacent att. steps
0
VDC
DC Steps
-3
0
3
AMUTE
Output Mute Attenuation
80
90
AUDIO OUTPUTS (LOUT, ROUT, REC_OUT_L, REC_OUT_R)
VOCL
ROUT
VOUT
Clipping Level
d = 0.3%
2
2.5
200
4.5
Vrms
Ω
Output resistance
DC Voltage Level
100
4.2
300
4.8
V
GENERAL
NO(OFF)
Output Noise (OFF)
BW = 20Hz to 20KHz
Output LOUT, ROUT,
Output: REC-OUT-L,
REC-OUT-R
8
8
15
15
µVrms
Vrms
µ
NO(MOV)
NO(MUS)
NO(MON)
Output Noise (Movie)
Output Noise (Music)
Output Noise (Simulated)
Mode =Movie ,
BW = 20Hz to 20KHz
30
30
30
µVrms
µVrms
Rout and Lout measurement
Mode = Music ,
BW = 20Hz to 20KHz,
Rout and Lout measurement
Mode = Simulated,
Vrms
µ
BW = 20Hz to 20KHz
Rout and Lout measurement
d
Distorsion
Av = 0 ; Vin = 1Vrms
0.02
70
0.1
1
%
SC
Channel Separation
60
dB
BUS INPUTS
VIL
VIH
IIN
Input Low Voltage
Input High Voltage
Input Current
V
V
3
-5
+5
µA
V
VO
Output Voltage SDA
Acknowledge
IO = 1.6mA
0.4
0.8
Note:
(1) Bass and Treble response: The center frequency and the resonance quality can be choosen by
the external circuitry. A standard first order bass response can be realized by a standard feedback network.
VS
2
(2) The peack voltage of the two input signals must be less then
VS
:
•
(Lin + Rin) peak
AVin <
2
6/18
TDA7345
2C BUS INTERFACE
knowledge bit. The MSB is transferredfirst.
Acknowledge
I
Data transmission from microprocessor to the
TDA7345 and viceversa takes place through the
2 wires I2C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be connected).
The master (µP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDAline is stable LOWduringthis clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the µP can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging,and sends the new data.
Byte Format
This approach of course is less protected from
misworking and decreases the noise immunity.
Every byte transferred on the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
2
Figure 3:
Data Validity on the I CBUS
2
Figure 4:
Timing Diagram of I CBUS
Figure 5: Acknowledge on the I2CBUS
7/18
TDA7345
the end of each transmitted byte.
A subaddress(function) bytes (identified by the
MSB = 0)
A sequence of dates and subaddresses (N
bytes + achnowledge. The dates are identified
by MSB = 1, subaddressesby MSB = 0)
A stop condition (P)
SOFTWARE SPECIFICATION
InterfaceProtocol
The interface protocol comprises:
A start condition (s)
A chip address byte, containing the TDA7345
address (the 8th bit of the byte must be 0).
The TDA7345 must always acknowledge at
TDA7345 ADDRESS
MSB
1
LSB
0
MSB
LSB
MSB
LSB
S
0
0
0
0
0
1
ACK
DATA
ACK
DATA
ACK
S
D94AU194
Data Transferred (N-bytes + Acknowledge)
ACK = Achnowledge
S = Start
P = Stop
chip address, a subaddress with the LSB = 0 (no
incremental bus), N-datas (all these datas con-
cern the subaddress selected), a new subad-
dress, N-data, a stop condition.
So it can receive in a single transmission how
many subaddress are necessary, and for each
subaddresshow many data are necessary.
INTERFACE FEATURES
- Due to the fact that the MSB is used to select
if the byte transmitted is a subaddress (func-
tion) or a data (value), between a start and
stop condition, is possible to receive, how
many subaddressesand datas as wanted.
- The subaddress (function) is fixed until a new
subaddress is transmitted, so the TDA7345
can receive how many data as wanted for the
selected subaddress (without the need for a
new start condition)
2) INCREMENTAL BUS
TDA7345 receives a start condition, the correct
chip address a subaddress with the LSB = 1 (in-
cremental bus): now it is in a loop condition with
an autoincreaseof the subaddress.
The first data that it receives doesn’t concern the
subaddress sended but the next one, the second
one concerns the subaddress sended plus two in
the loop etc, and at the end it receives the stop
condition.
- If TDA7345 receives a subaddress with the
LSB = 1 the incremental bus is selected, so it
enters in a loop condition that means that
every acknowledge will increase automat-
ically the subaddress (function) and it re-
ceives the data related to the new subad-
dress.
In the pictures there are some examples:
S = start
EXAMPLES
ACK = acknowledge
1) NO INCREMENTAL BUS
TDA7345 receives a start condition, the correct
B = 1 incremental bus, B = 0 no incremental bus
P = stop
1) one subaddress, with n data concerning that subaddress(no incremental bus)
CHIP ADDRESS
SUBADDRESS
DATA 1 ... DATA n
DATA
MSB
1
LSB
0
MSB
0
LSB
0
MSB
1
LSB
S
0
0
0
0
0
1
ACK
A0 A1 A2 A3
X
X
ACK
ACK
P
D94AU195
8/18
TDA7345
2) one subaddress, (with incremental bus) , with n data (data1 that concerns subaddress+1, data 2
that concernssubaddress+ 2 etc.)
CHIP ADDRESS
SUBADDRESS
DATA 1 ... DATA n
DATA
MSB
1
LSB
0
MSB
0
LSB
1
MSB
1
LSB
S
0
0
0
0
0
1
ACK
A0 A1 A2 A3
X
X
ACK
ACK
P
D94AU196
3) moresubaddress with more data
CHIP ADDRESS
SUBADDRESS
DATA 1 ... DATA n
DATA
SUBADDRESS
DATA 1 ... DATA n
DATA
MSB
1
LSB
0
MSB
0
LSB
MSB
1
LSB
MSB
0
LSB
0
MSB
1
LSB
S
0
0
0
0
0
1
ACK
A0 A1 A2 A3
X
X
0
ACK
ACK
A0 A1 A2 A3
X
X
ACK
ACK
1
D94AU197
DATA BYTES
FUNCTION SELECTION
FIRST BYTE (subaddress)
The first byte select the function, it is identified by the MSB = 0
MSB
LSB
SUBADDRESS
A0
A1
A2
A3
B
0
0
0
0
0
X
X
X
X
X
B
VOLUME ATTENUATION &
LOUDNESS
1
0
0
X
B
SURROUND & OUT &
EFFECT CONTROL
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B
B
B
B
B
B
B
BASS
TREBLE
REC-OUT-R
REC-OUT-L
ROUT
LOUT
1
INPUT STAGE CONTROL
B = 1 yes incremental bus;
B = 0 no incremental bus;
X = indifferent 0,1
9/18
TDA7345
VALUE SELECTION
The second byte select the value, it is identified by the MSB = 1
VOLUME ATTENUATION
MSB
LSB
1.25 dB STEPS
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
-1.25
-2.50
-3.75
-5.00
-6.25
-7.50
-8.75
10 dB STEPS
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-10
-20
-30
-40
-50
-60
-70
ATT SPEAKER L AND R
MSB
LSB
1.25 dB STEPS
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
-1.25
-2.50
-3.75
-5.00
-6.25
-7.50
-8.75
10 dB STEPS
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-10
-20
-30
-40
-50
-60
-70
MUTE
OFF
ON
1
1
0
1
10/18
TDA7345
ATT REC-OUT L AND R
MSB
LSB
1.25 dB STEPS
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
-1.25
-2.50
-3.75
-5.00
-6.25
-7.50
-8.75
10 dB STEPS
0
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
0
0
1
1
1
0
1
0
1
1
-10
-20
-30
1
1
1
MUTE
TREBLE/ BASS
MSB
LSB
2 dB STEPS
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
14
12
10
8
6
4
2
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
-2
-4
-6
-8
-10
-12
-14
11/18
TDA7345
SURROUND & OUT & EFFECT CONTROL
LSB
MSB
SELECTION
SURROUND
SELECTION
1
1
1
1
0
0
1
1
0
1
0
1
SIMULATED
MUSIC
MOVIE
OFF
SELECTION
EFFECT CONTROL
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
-6
-7
-8
-9
-10
-11
-12
-13
-14
-15
-16
-17
-18
-19
-20
-21
For example to select the music mode, out fix, effect control =-9dB:
1 0 0 1 1 1 0 1
12/18
TDA7345
INPUT CONTROL RANGE (0 TO -19.68dB)
LSB
MSB
0.3125 dB STEPS
1
1
1
1
1
1
1
1
X
Xx
X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
-0.3125
-0.625
-0.9375
-1.25
X
X
X
-1.5625
-1.875
-2.1875
X
X
2.5 dB STEPS
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
-2.5
-5.0
-7.5
-10
-12.5
-15
-17.5
POWER ON RESET
VOLUME ATTENUATION
TREBLE
MAX ATTENUATION,
-14dB
BASS
-14dB
SURROUND + EFFECT CONTROL
ATT SPEAKER R
ATT SPEAKER L
ATT REC-OUT L
ATT REC-OUT R
OFF + MAX ATTENUATION
MUTE
MUTE
MUTE
MUTE
13/18
TDA7345
PIN:
PIN:
HP2
HP1
LP1
VS
VS
10K
60K
20µA
5.5K
60K
GND
GND
5.5K
HP1
HP2
D94AU199
D94AU198
PIN:
BASS - LA, BASS - RA
PIN:
Lin, Rin
VS
VS
20µA
20µA
50K
48K
GND
GND
BASS-LB
VREF
D94AU200
BASS-RB
D94AU201
PIN: BASS - LB, BASS - RB
PIN: TREBLE - L, TREBLE - R
VS
VS
20µA
20µA
GND
BASS-LA
48K
25K
D94AU203
BASS-RA
D94AU202
14/18
TDA7345
PIN:
PIN:
PIN:
,
PIN:
PIN:
PIN:
LOUT ROUT, REC-OUT-1 REC-OUT-R
SCL, SDA
VS
20µA
20µA
100Ω
D94AU205
D94AU204
LP
PS3, PS2
VS
VS
20µA
20µA
10K
18.08K
PS3A
PS4A
GND
D94AU206
D94AU207
CREF
PS2
VS
VS
20µA
20µA
50K
50K
398Ω
PS2A
D94AU208
D94AU209
15/18
TDA7345
PIN:
PIN:
LP1
PS1
VS
VS
20µA
20µA
17.95K
10K
PS1A
HP1
D94AU211
D94AU210
PIN:
REAR OUT
VS
PIN:
REAR IN
VS
20µA
20µA
20K
20K
D94AU214
D94AU215
16/18
TDA7345
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN. TYP. MAX.
A
a1
b
2.65
0.3
0.104
0.012
0.019
0.013
0.1
0.004
0.35
0.23
0.49 0.014
0.32 0.009
b1
C
c1
D
E
0.5
0.020
45° (typ.)
17.7
10
18.1 0.697
10.65 0.394
0.713
0.419
e
1.27
0.050
0.65
e3
F
16.51
7.4
0.4
7.6
0.291
0.299
0.050
L
1.27 0.016
SO28
S
8 ° (max.)
17/18
TDA7345
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1999 STMicroelectronics – Printed in Italy – AllRights Reserved
STMicroelectronics GROUP OF COMPANIES
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Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
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18/18
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