TDA7348D [STMICROELECTRONICS]
DIGITALLY CONTROLLED AUDIO PROCESSOR; 数字控制音频处理器
| 型号： | TDA7348D |
| 厂家： | 
ST |
| 描述： | DIGITALLY CONTROLLED AUDIO PROCESSOR |
| 文件： | 总14页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDA7348
DIGITALLY CONTROLLED AUDIO PROCESSOR
PRODUCT PREVIEW
INPUT MULTIPLEXER
- THREE STEREO AND ONE MONO INPUTS
- SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES
VOLUME CONTROL IN 0.3dB STEPS IN-
CLUDING GAIN UP TO 20dB
ZERO CROSSING MUTE AND DIRECT
MUTE
PAUSE DETECTOR WITH PROGRAMMABLE
THRESHOLD
DIP28
SO28
SOFT MUTE CONTROLLED BY SOFTWARE
OR HARDWARE PIN
ORDERING NUMBER: TDA7348 (DIP28)
TDA7348D (SO28)
BASS AND TREBLE CONTROL
FOUR SPEAKER ATTENUATORS
- FOUR INDEPENDENT SPEAKERS
CONTROL IN 1.25dBSTEPS FOR
BALANCE AND FADER FACILITIES
- INDEPENDENT MUTE FUNCTION
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL I2 CBUS
Due to a highly linear signal processing, using
CMOS-switching techniques instead of standard
bipolar multipliers, very low distortion and very
low noise are obtained Several new features like
softmute, zero-crossing mute and pause detector
are implemented.
The Soft Mute function can be activated in two
ways:
DESCRIPTION
The TDA7348 is an upgrade of the TDA7318
audioprocessor.
Thanks to the used BIPOLAR/CMOS technology,
very low distortion, low noise and DC-stepping
are obtained.
1 Via serial bus (bit D0, Mute Byte)
2 Directly on pin 22 through an I/O line of the
microcontroller
Very low DC stepping is obtained by use of a
BICMOS technology.
1/14
November 1994
This is advanced information on a new product now in developmentor undergoing evaluation. Details are subject to change without notice.
TDA7348
BLOCK DIAGRAM
9D3U1A0
2/14
TDA7348
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
10.5
Unit
V
VS
Tamb
Tstg
Operating Supply Voltage
Operating Ambient Temperature
Storage Temperature Range
-40 to 85
-55 to 150
°C
°C
PIN CONNECTION
CREF
VS
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SCL
BUS
INPUTS
2
SDA
GND
L
3
OUT LF
OUT RF
OUT LR
OUT RR
SM
4
TREBLE
R
5
IN(R)
OUT(R)
IN R3
IN R2
IN R1
6
7
8
BOUT(R)
BIN(R)
BOUT(L)
BIN(L)
OUT(L)
IN(L)
9
BASS
10
11
12
13
14
AM MONO
IN L3
IN L2
IN L1
CSM
D94AU099
THERMAL DATA
Symbol
Parameter
Thermal Resistance Junction-pins
DIP28
SO28
Unit
Rth j-amb
85
65
°C/W
QUICK REFERENCE DATA
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
VS
VCL
THD
S/N
SC
Supply Voltage
6
9
10.2
Max. input signal handling
2.1
2.6
Vrms
%
Total Harmonic Distortion V = 1Vrms f = 1KHz
Signal to Noise Ratio
0.01
106
100
0.08
dB
dB
dB
dB
dB
dB
Channel Separation f = 1KHz
Volume Control
-78.45
-14
20
+14
+18
0
Treble Control 2dB step
Bass Control 2dB step
-10
Fader and Balance Control 1.25dB step
Input Gain 3.75dB step
-38.75
0
11.25
dB
dB
Mute Attenuation
100
3/14
TDA7348
ELECTRICAL CHARACTERISTICS (VS = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C; all controls flat
(G = 0.3dB step 0dB); f = 1KHz. Refer to the test circuit, unless otherwise specified.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
INPUT SELECTOR
RI
VCL
SI
Input Resistance
Clipping Level
70
2.1
100
2.6
130
KΩ
VRMS
dB
d ≤ 0.3%
Input Separation
Output Load Resistance
Minimum Input Gain
Maximum Input Gain
Step Resolution
Input Noise
80
100
RL
2
KΩ
dB
GI MIN
GI MAX
Gstep
eN
-0.75
10.25
2.75
0
11.25
3.75
2.3
0.75
12.25
4.75
dB
dB
20Hz to 20 KHz unweighted
Adiacent Gain Steps
GIMIN to GIMAX
µV
VDC
DC Steps
1.5
10
mV
mV
3
VOLUME CONTROL (1 + 2)
RI
Input Resistance
Maximum Gain
35
50
20
KΩ
dB
dB
dB
GMAX
AMAX
ASTEPC
18.75
21.25
2.0
Maximum Attenuation
78.45
1.25
Step Resolution Coarse
Attenuation
0.5
ASTEPF
EA
Step Resolution Fine Attenuation (Only Volume 1)
0.11
-1.25
-3
0.31
0
0.51
1.25
2
dB
dB
dB
dB
mV
mV
Attenuation Set Error
G = 20 to -20dB
G = -20 to -58dB
Et
Tracking Error
DC Steps
2
VDC
Adiacent Attenuation Steps
From 0dB to AMAX
-3
0
3
0.5
5
ZERO CROSSING MUTE
VTH
Zero Crossing Threshold
(note 1)
WIN = 11
WIN = 10
WIN = 01
WIN = 00
20
40
mV
mV
mV
mV
dB
80
160
100
0
AMUTE
VDC
Mute Attenuation
DC Step
80
0dB to Mute
3
mV
SOFT MUTE
AMUTE
Mute Attenuation
ON Delay Time
45
0.7
20
25
60
1
dB
ms
ms
µA
µA
V
TDON
CCSM = 22nF; 0 to -20dB; I = IMAX
CCSM = 22nF; 0 to -20dB; I = IMIN
VCSM = 0V; I = IMAX
1.7
55
75
35
50
1
TDOFF
OFF Current
VCSM = 0V; I = IMIN
VTHSM
RINT
Soft Mute Threshold
Pullup Resistor (pin 22)
(pin 22) Level High
(pin 22) Level Low
1.5
35
2.5
50
3.5
65
(note 2)
KΩ
V
VSMH
VSML
Soft Mute Active
3.5
1
V
4/14
TDA7348
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
BASS CONTROL
BBOOST
BCUT
Astep
Rg
Max Bass Boost
Max Bass Cut
15
-8.5
1
18
-10
2
20
-11.5
3
dB
dB
dB
KΩ
Step Resolution
Internal Feedback Resistance
45
65
85
TREBLE CONTROL
CRANGE
Control Range
±13
±14
±15
dB
dB
Astep
Step Resolution
1
2
3
SPEAKER ATTENUATORS
CRANGE
Astep
AMUTE
EA
Control Range
35
0.5
80
37.5
1.25
100
40
dB
dB
dB
dB
mV
Step Resolution
Output Mute Attenuation
Attenuation Set Error
DC Steps
2.0
Data Word = XXX11111
1.25
3
VDC
Adjacent Attenuation Steps
0
AUDIO OUTPUT
Vclip
Clipping Level
d = 0.3%
2.1
2
2.6
Vrms
KΩ
Ω
RL
Output Load Resistance
Output Impedance
DC Voltage Level
RO
30
100
4.1
VDC
3.5
3.8
V
GENERAL
VCC
Supply Voltage
6
9
10
80
65
2.5
5
10.2
15
V
ICC
Supply Current
mA
dB
dB
µV
µV
dB
dB
dB
dB
%
PSRR
Power Supply Rejection Ratio
f = 1KHz
60
B = 20 to 20kHz ”A” weighted
OutputMuted (B = 20to20kHz flat)
All Gains 0dB (B = 20 to 20kHz flat)
AV = 0 to -20dB
eNO
Et
Output Noise
15
1
Total Tracking Error
0
AV = -20 to -60dB
0
2
S/N
SC
d
Signal to Noise Ratio
Channel Separation
Distortion
All Gains = 0dB; VO = 1Vrms
106
100
0.01
80
VIN = 1V
0.08
1
BUS INPUTS
VIL
VlN
IlN
Input Low Voltage
V
V
Input High Voltage
Input Current
3
VIN = 0.4V
IO = 1.6mA
-5
5
µA
V
VO
Output Voltage SDA
Acknowledge
0.4
0.8
Note 1: WIN represents the MUTE programming bit pair D6, D5 for the zero crossing window threshold
Note 2: Internal pullup resistor to Vs/2; ”LOW” = softmuteactive
r
5/14
TDA7348
I2C BUS INTERFACE
knowledge bit. The MSB is transferredfirst.
Acknowledge
Data transmission from microprocessor to the
TDA7348 and viceversa takes place thru the 2
wires I2C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).
The master (µP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stableLOW during this clock pulse.
Data Validity
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
A STOP conditions must be sent before each
START condition.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the µP can use a simplier transmis-
sion: simply it waits one clock without checking
the slave acknowledging, and sends the new
data.
Byte Format
Every byte transferred to the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
This approach of course is less protected from
misworking and decreases the noise immunity.
Figure 3: Data Validity on the I2CBUS
Figure 4: Timing Diagram of I2CBUS
Figure 5: Acknowledge on the I2CBUS
6/14
TDA7348
read/write transmission)
A subaddress byte.
A sequence of data (N-bytes + acknowledge)
A stop condition (P)
SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises:
A start condition (s)
A chip address byte,(the LSB bit determines
CHIP ADDRESS
SUBADDRESS
DATA 1 to DATA n
MSB
1
LSB
MSB
LSB
MSB
LSB
ACK P
S
0
0
0
1
0
0
R/W ACK X
X
X
I
A3 A2 A1 A0 ACK
DATA
ACK = Acknowledge
S = Start
P = Stop
I = Auto Increment
X = Not used
MAX CLOCK SPEED 500kbits/s
AUTO INCREMENT
If bit I in the subaddressbyte is set to ”1”, the autoincrementof the subaddress is enabled
SUBADDRESS (receive mode)
MSB
LSB
A0
0
FUNCTION
Input Selector
X
X
X
I
A3
0
A2
0
A1
0
0
0
0
1
Volume 2
0
0
1
0
Volume 1
0
0
1
1
Bass, Treble
0
1
0
0
Speaker Attenuator LF
Speaker Attenuator LR
Speaker Attenuator RF
Speaker Attenuator RR
Mute
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
TRANSMITTED DATA
Send Mode
MSB
LSB
X
X
X
X
X
X
SM
ZM
ZM = Zero crossing muted (HIGHactive)
SM = Soft mute activated (HIGH active)
X = Not used
The transmitted data is automatically updated after each ACK.
Transmission can be repeated without new chipaddress.
7/14
TDA7348
DATA BYTE SPECIFICATION
X = not relevant;set to ”1” during testing
Input Selector
MSB
LSB
D0
0
FUNCTION
D7
X
X
X
X
X
X
X
X
X
X
X
X
D6
X
X
X
X
X
X
X
X
X
X
X
X
D5
1
1
1
1
1
1
1
1
1
1
1
1
D4
D3
D2
0
D1
0
not used
IN 2
0
0
1
0
1
0
IN 1
0
1
1
AM mono
not used
IN 3
1
0
0
1
0
1
1
1
0
not allowed
not allowed
11.25dB gain
7.5dB gain
3.75dB gain
0dB gain
1
1
1
0
0
1
1
0
1
0
1
For example to select the IN 2 input with a gain of 7.5dB the Data Byte is: X X 1 0 1 0 0 1
Volume 2
MSB
D7
X
LSB
D0
0
FUNCTION
D6
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0dB
X
1
-1.25dB
-2.5dB
X
0
X
1
-3.75dB
-5dB
X
0
X
1
-6.25dB
-7.5dB
X
0
X
1
-8.75dB
-10dB
X
0
X
1
-11.25dB
-12.5dB
-13.75dB
-15dB
X
0
X
1
X
0
X
1
-16.25dB
-17.5dB
-18.75dB
X
0
X
1
For example to select -17.5dB attenuation the Data Byte is: X X X1 1 1 1 0
8/14
TDA7348
Mute
MSB
D7
LSB
D0
1
FUNCTION
D6
D5
D4
D3
D2
D1
Soft Mute On
Soft Mute with fast slope (I = IMAX
Soft Mute with slow slope (I = IMIN
0
1
1
)
1
)
1
Direct Mute
0
0
1
1
0
Zero Crossing Mute On
Zero Crossing Mute Off (delayed until next
zerocrossing)
Zero Crossing Mute and Pause Detector Reset
160mV ZC Window Threshold (WIN = 00)
80mV ZC Window Threshold (WIN = 01)
40mV ZC Window Threshold (WIN = 10)
20mV ZC Window Threshold (WIN = 11)
Nonsymmetrical Bass Cut (note 4)
0
0
1
1
0
1
0
1
0
1
Symmetrical Bass Cut
An additional direct mute function is included in the Speaker Attenuators.
Note 4: Bass cut for very low frequencies; should not be used at +16 and +18dB bass boost (DC gain)
Speaker Attenuators
MSB
D7
LSB
D0
SPEAKER ATTENUATOR LF, LR, RF, RR
D6
D5
D4
D3
D2
D1
1.25dB step
0dB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-1.25dB
-2.5dB
-3.75dB
-5dB
-6.25dB
-7.5dB
-8.75dB
10dB step
0dB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
1
0
1
0
1
1
-10dB
-20dB
-30dB
1
1
1
Speaker Mute
For example an attenuationof 25dB on a selected output is given by: X X X1 0 1 0 0
9/14
TDA7348
Bass/Treble
MSB
D7
LSB
D0
FUNCTION
D6
D5
D4
D3
D2
D1
TREBLE STEP
-14dB
-12dB
-10dB
-8dB
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
-6dB
-4dB
-2dB
0dB
0dB
2dB
4dB
6dB
8dB
10dB
12dB
14dB
BASS STEPS
-10dB
-8dB
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
-6dB
-4dB
-2dB
-0dB
-0dB
2dB
4dB
6dB
8dB
10dB
12dB
14dB
146B
18dB
For example 12dB Treble and -8dB Bass give the followingDATA BYTE: 0 0 1 1 1 0 0 1
10/14
TDA7348
Volume 1
MSB
D7
LSB
D0
FUNCTION
D6
D5
D4
D3
D2
D1
0.31dB Fine Attenuation Steps
0
0
1
1
0
1
0
1
0dB
-0.31dB
-0.62dB
-0.94dB
1.25dB Coarse Attenuation Steps
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0dB
-1.25dB
-2.5dB
-3.75dB
-5dB
-6.25dB
-7.5dB
-8.75dB
10dB Gain / Attenuation Steps
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
20dB
10dB
0dB
-10dB
-20dB
-30dB
-40dB
-50dB
For example to select -47.81dB Volume the Data Byte is: 1 1 0 1 1 0 0 1
Power on RESET: All Bytes Set to 1 1 1 1 1 1 1 0
Purchase of I2C Componentsof SGS-THOMSON Microlectronics, conveysa license under the Philips
I2C Patent Rights to use these components in an I2C system, provided that the system conforms to
the I2C Standard Specifications as defined by Philips.
11/14
TDA7348
DIP28 PACKAGE MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
0.23
15.2
TYP.
0.63
0.45
MAX.
MIN.
0.009
0.598
MAX.
a1
b
0.025
0.018
b1
b2
D
E
0.31
0.012
1.27
0.050
37.34
16.68
1.470
0.657
e
2.54
0.100
1.300
e3
F
33.02
14.1
0.555
I
4.445
3.3
0.175
0.130
L
12/14
TDA7348
SO28 PACKAGE MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
2.65
0.3
MIN.
MAX.
0.104
0.012
0.019
0.013
A
a1
b
0.1
0.004
0.014
0.009
0.35
0.23
0.49
0.32
b1
C
0.5
0.020
c1
D
45° (typ.)
17.7
10
18.1
0.697
0.394
0.713
0.419
E
10.65
e
1.27
0.050
0.65
e3
F
16.51
7.4
0.4
7.6
0.291
0.016
0.299
0.050
L
1.27
S
8° (max.)
13/14
TDA7348
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men-
tioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex-
press written approval of SGS-THOMSON Microelectronics.
1995 SGS-THOMSON Microelectronics - All RightsReserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore -
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14/14
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