TDA7350 [STMICROELECTRONICS]
22W BRIDGE-STEREO AMPLIFIER FOR CAR RADIO; BRIDGE 22W立体声放大器，用于汽车收音机
| 型号： | TDA7350 |
| 厂家： | 
ST |
| 描述： | 22W BRIDGE-STEREO AMPLIFIER FOR CAR RADIO |
| 文件： | 总43页 (文件大小：638K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
D OR P PACKAGE
Available in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V
Fixed-Output and Adjustable Versions
(TOP VIEW)
Integrated Precision Supply-Voltage
Supervisor Monitoring Regulator Output
Voltage
GND
EN
IN
RESET
1
2
3
4
8
7
6
5
†
‡
SENSE /FB
OUT
Active-Low Reset Signal with 200-ms Pulse
Width
IN
OUT
Very Low Dropout Voltage . . . Maximum of
PW PACKAGE
(TOP VIEW)
35 mV at I = 100 mA (TPS7350)
O
Low Quiescent Current – Independent of
Load . . . 340 µA Typ
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
GND
GND
NC
NC
EN
RESET
NC
Extremely Low Sleep-State Current,
NC
0.5 µA Max
‡
FB
2% Tolerance Over Full Range of Load,
Line, and Temperature for Fixed-Output
NC
†
SENSE
§
Versions
NC
IN
OUT
OUT
NC
Output Current Range of 0 mA to 500 mA
TSSOP Package Option Offers Reduced
Component Height For Critical Applications
IN
IN
NC
NC – No internal connection
description
†
SENSE – Fixed voltage options only
(TPS7325, TPS7330, TPS7333, TPS7348, and TPS7350)
The TPS73xx devices are members of a family of
micropower low-dropout (LDO) voltage regulators.
‡
FB – Adjustable version only (TPS7301)
They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset
¶
function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.
AVAILABLE OPTIONS
OUTPUT VOLTAGE
(V)
NEGATIVE-GOING RESET
THRESHOLD VOLTAGE (V)
PACKAGED DEVICES
CHIP FORM
(Y)
T
J
SMALL
OUTLINE
(D)
PLASTIC DIP
(P)
TSSOP
(PW)
MIN
TYP
MAX
MIN
TYP
MAX
4.9
4.75
5
4.85
3.3
3
5.1
4.95
3.37
3.06
4.55
4.5
4.65
4.6
4.75 TPS7350QD
4.7 TPS7348QD
TPS7350QP
TPS7348QP
TPS7333QP
TPS7330QP
TPS7325QP
TPS7350QPW
TPS7348QPW
TPS7333QPW
TPS7330QPW
TPS7325QPW
TPS7350Y
TPS7348Y
TPS7333Y
TPS7330Y
TPS7325Y
3.23
2.868
2.58
2.23
2.934
2.64
2.32
3
TPS7333QD
–40°C to
125°C
2.94
2.7 TPS7330QD
2.39 TPS7325QD
2.425
2.5 2.575
Adjustable
1.2 V to 9.75 V
1.101
1.123
1.145
TPS7301QD
TPS7301QP
TPS7301QPW
TPS7301Y
The D and PW packages are available taped and reeled. Add an R suffix to device type (e.g., TPS7350QDR). The TPS7301Q is programmable
using an external resistor divider (see application information). The chip form is tested at 25°C.
§
¶
The TPS7325 has a tolerance of ±3% over the full temperature range.
The TPS71xx and the TPS72xx are 500-mA and 250-mA output regulators respectively, offering performance similar to that of the TPS73xx but
without the delayed-reset function. The TPS72xx devices are further differentiated by availability in 8-pin thin-shrink small-outline packages
(TSSOP) for applications requiring minimum package size.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
description (continued)
The RESET output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event
ofanundervoltagecondition. AninternalcomparatorintheTPS73xxmonitorstheoutputvoltageoftheregulator
to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET output (open-drain NMOS) turns on, taking the RESET signal low. RESET stays low
for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out
begins. At the completion of the 200-ms delay, RESET goes high.
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance
is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35 mV
at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure 1).
Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains
constant, independent of output loading (typically 340 µA over the full range of output current, 0 mA to 500 mA).
These two key specifications yield a significant improvement in operating life for battery-powered systems.
TheLDOfamilyalsofeaturesasleepmode;applyingalogichighsignaltoEN(enable)shutsdowntheregulator,
reducing the quiescent current to 0.5 µA maximum at T = 25°C.
J
The TPS73xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version
(programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2%
over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is
available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of
1.2 mm.
0.3
†
TPS73xxPW
T
A
= 25°C
TPS7330
TPS7333
0.25
8
20
15
14
13
To System
Reset
V
I
IN
RESET
9
250 kΩ
IN
IN
SENSE
OUT
0.2
TPS7325
10
V
O
6
0.1 µF
EN
OUT
‡
0.15
C
O
TPS7348
TPS7350
+
10 µF
GND
0.1
0.05
0
1
2
3
CSR = 1 Ω
†
‡
TPS7325, TPS7330, TPS7333, TPS7348, TPS7350 (fixed-voltage
options)
Capacitor selection is nontrivial. See application information
section for details.
0
50 100 150 200 250 300 350 400 450 500
– Output Current – mA
I
O
Figure 2. Typical Application Configuration
Figure 1. Dropout Voltage Versus Output Current
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TPS73xxY chip information
These chips, when properly assembled, display characteristics similar to those of the TPS73xxQ. Thermal
compression or ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted
with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(5)
(6)
†
SENSE
(3)
(2)
IN
‡
FB
(5)
(6)
(4)
TPS73xx
(4)
(7)
OUT
EN
RESET
(1)
(7)
GND
CHIP THICKNESS: 15 TYPICAL
80
BONDING PADS: 4 × 4 MINIMUM
T max = 150°C
J
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
†
‡
SENSE – Fixed voltage options only (TPS7325, TPS7330,
TPS7333, TPS7348, and TPS7350)
FB – Adjustable version only (TPS7301)
(3)
(2)
(1)
NOTE A. For most applications, OUT and SENSE should
betiedtogetherascloseaspossibletothedevice;
for other implementations, refer to SENSE-pin
connection discussion in the applications
information section of this data sheet.
92
functional block diagram
IN
RESISTOR DIVIDER OPTIONS
DEVICE
R1
R2
UNIT
¶
¶
¶
EN
TPS7301
TPS7325
TPS7330
TPS7333
TPS7348
TPS7350
0
∞
Ω
260
358
420
726
756
233
233
233
233
233
kΩ
kΩ
kΩ
kΩ
kΩ
RESET
_
+
OUT
NOTE A. Resistors are nominal values only.
§
SENSE /FB
+
_
Delayed
Reset
V
ref
R1
R2
COMPONENT COUNT
MOS transistors
Bilpolar transistors
Diodes
464
41
4
Capacitors
Resistors
17
76
GND
§
¶
For most applications, SENSE should be externally connected to OUT as close as possible to the device. For other implementations, refer to
SENSE-pin connection discussion in applications information section.
Switch positions are shown with EN low (active).
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
timing diagram
V
I
†
V
res
V
res
t
V
O
V
IT+
V
IT+
Threshold
Voltage
V
IT–
V
IT–
t
RESET
Output
200 ms
Delay
200 ms
Delay
Output
Undefined
Output
Undefined
t
†
V
is the minimum input voltage for a valid RESET. The symbol V is not currently listed within EIA or JEDEC standards
res
res
for semiconductor symbology.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
§
Input voltage range , V , RESET, SENSE, EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 11 V
I
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A
O
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Tables 1 and 2
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
‡
§
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network terminal ground.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURE (SEE FIGURE 3)
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 125°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
D
P
725 mW
5.8 mW/°C
9.4 mW/°C
5.6 mW/°C
464 mW
752 mW
448 mW
145 mW
235 mW
140 mW
1175 mW
†
PW
700 mW
DISSIPATION RATING TABLE 2 – CASE TEMPERATURE (SEE FIGURE 4)
≤ 25°C DERATING FACTOR = 70°C = 125°C
T
C
T
C
T
C
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
C
D
P
2188 mW
9.4 mW/°C
21.9 mW/°C
32.2 mW/°C
1765 mW
1752 mW
2576 mW
1248 mW
548 mW
805 mW
2738 mW
†
PW
4025 mW
†
Refer to Thermal Information section for detailed power dissipation considerations when using the
TSSOP package.
MAXIMUM CONTINUOUS DISSIPATION
MAXIMUM CONTINUOUS DISSIPATION
vs
vs
CASE TEMPERATURE
FREE-AIR TEMPERATURE
4800
4400
1400
1200
4000
3600
3200
2800
2400
2000
1600
1200
800
PW Package
R
= 37°C/W
θJC
1000
800
P Package
R
= 106°C/W
θJA
P Package
R
= 46°C/W
θJC
D Package
600
R
= 172°C/W
θJA
400
200
0
PW Package
D Package
= 57°C/W
R
= 178°C/W
θJA
R
θJC
400
0
25
50
75
100
125
150
25
50
75
100
125
150
T – Case Temperature – °C
C
T
A
– Free-Air Temperature – °C
Figure 3
Figure 4
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
recommended operating conditions
MIN
2.47
3.1
MAX
10
UNIT
V
TPS7301Q
TPS7325Q
TPS7330Q
10
3.5
10
V
†
Input voltage, V
I
TPS7333Q
TPS7348Q
TPS7350Q
3.77
5.2
10
10
V
5.33
2
10
High-level input voltage at EN, V
V
V
IH
Low-level input voltage at EN, V
0.5
500
125
IL
Output current range, I
0
mA
°C
O
Operating virtual junction temperature range, T
–40
J
†
Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage, V
DO
,
at the maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads.
To calculate the minimum input voltage for the maximum load current used in a given application, use the following equation:
V
V
V
I(min)
O(max)
DO(max load)
BecausetheTPS7301isprogrammable,r
shouldbeusedtocalculateV beforeapplyingtheaboveequation.Theequationforcalculating
DO
DS(on)
is given in Note 2 in the TPS7301 electrical characteristics table. The minimum value of 2.97 V is the absolute lower limit for
V
from r
DS(on)
DO
the recommended input voltage range for the TPS7301.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
‡
electrical characteristics at I = 10 mA, EN = 0 V, C = 4.7 µF (CSR = 1 Ω), SENSE/FB shorted to
OUT (unless otherwise noted)
O
o
§
PARAMETER
MIN
TYP
MAX
400
550
0.5
2
T
TEST CONDITIONS
UNIT
J
25°C
–40°C to 125°C
25°C
340
EN ≤ 0.5 V,
V = V + 1 V,
I O
Ground current (active mode)
µA
0 mA ≤ I ≤ 500 mA
O
0.01
1.2
Input current (standby mode)
Output current limit
µA
A
EN = V ,
2.7 V ≤ V ≤ 10 V
I
I
–40°C to 125°C
25°C
2
V
O
= 0 V,
V = 10 V
I
–40°C to 125°C
25°C
2
0.01
0.02
0.5
1
Pass-element leakage current in standby
mode
µA
µA
EN = V ,
2.7 V ≤ V ≤ 10 V
I
I
–40°C to 125°C
25°C
0.5
0.5
RESET leakage current
Normal operation, V at RESET = 10 V
–40°C to 125°C
–40°C to 125°C
Output voltage temperature coefficient
Thermal shutdown junction temperature
61
75 ppm/°C
°C
165
2.5 V ≤ V ≤ 6 V
2
I
–40°C to 125°C
V
EN logic high (standby mode)
6 V ≤ V ≤ 10 V
2.7
I
25°C
–40°C to 125°C
25°C
0.5
V
2.7 V ≤ V ≤ 10 V
EN logic low (active mode)
EN hysteresis voltage
I
0.5
50
mV
25°C
–0.5 0.001
–0.5
0.5
µA
0.5
0 V ≤ V ≤ 10 V
EN input current
I
–40°C to 125°C
25°C
2.05
2.5
V
Minimum V for active pass element
I
–40°C to 125°C
25°C
2.5
1
1.5
V
Minimum V for valid RESET
I
= –300 µA
I
O(RESET)
–40°C to 125°C
1.9
‡
§
CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any
series resistance added externally, and PWB trace resistance to C .
o
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
†
TPS7301Q electrical characteristics at I = 10 mA, V = 3.5 V, EN = 0 V, C = 4.7 µF (CSR = 1 Ω), FB
shorted to OUT at device leads (unless otherwise noted)
O
I
o
‡
PARAMETER
MIN
TYP
MAX
T
J
TEST CONDITIONS
UNIT
25°C
1.182
V
Reference voltage (measured at FB)
2.5 V ≤ V ≤ 10 V,
See Note 1
5 mA ≤ I ≤ 500 mA,
O
I
–40°C to 125°C 1.147
–40°C to 125°C
1.217
V
Reference voltage temperature
coefficient
61
75 ppm/°C
25°C
–40°C to 125°C
25°C
0.7
1
1
V = 2.4 V,
50 µA ≤ I ≤ 150 mA
O
I
0.83
0.52
1.3
V = 2.4 V,
I
150 mA ≤ I ≤ 500 mA
O
–40°C to 125°C
25°C
1.3
Pass-element series resistance
(See Note 2)
Ω
0.85
V = 2.9 V,
I
50 µA ≤ I ≤ 500 mA
O
–40°C to 125°C
25°C
0.85
V = 3.9 V,
I
50 µA ≤ I ≤ 500 mA
0.32
0.23
3
O
V = 5.9 V,
I
50 µA ≤ I ≤ 500 mA
25°C
O
25°C
18
25
14
25
22
54
V = 2.5 V to 10 V,
I
See Note 1
50 µA ≤ I ≤ 500 mA,
O
Input regulation
mV
mV
mV
–40°C to 125°C
25°C
5
7
2.5 V ≤ V ≤ 10 V,
I
= 5 mA to 500 mA,
I
O
O
See Note 1
–40°C to 125°C
25°C
Output regulation
2.5 V ≤ V ≤ 10 V,
I
= 50 µA to 500 mA,
I
See Note 1
–40°C to 125°C
25°C
–40°C to 125°C
25°C
48
44
45
44
59
54
I
I
= 50 µA
O
Ripple rejection
f = 120 Hz
dB
= 500 mA,
O
See Note 1
–40°C to 125°C
25°C
Output noise-spectral density
Output noise voltage
f = 120 Hz
2
95
89
74
µV/√Hz
µVrms
C
C
C
= 4.7 µF
= 10 µF
= 100 µF
25°C
o
o
o
10 Hz ≤ f ≤ 100 kHz
25°C
25°C
§
V
decreasing
–40°C to 125°C 1.101
1.145
V
RESET trip-threshold voltage
O(FB)
§
25°C
25°C
12
mV
Measured at V
RESET hysteresis voltage
O(FB)
0.1
0.4
0.4
10
§
V = 2.13 V,
I
I
= 400 µA
V
RESET output low voltage
O(RESET)
–40°C to 125°C
25°C
–10
–20
0.1
FB input current
nA
–40°C to 125°C
20
†
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to C .
o
‡
§
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
Output voltage programmed to 2.5 V with closed-loop configuration (see application information).
NOTES: 1. When V < 2.9 V and I > 150 mA simultaneously, pass element r
DS(on)
increases (see Figure 33) to a point where the resulting
dropout voltage prevents the regulator from maintaining the specified tolerance range.
2. To calculate dropout voltage, use equation: V = I
I
O
r
DS(on)
DO
O
r
is a function of both output current and input voltage. This parametric table lists r
for V = 2.4 V, 2.9 V, 3.9 V, and
I
DS(on)
DS(on)
5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V respectively. For other
programmed values, refer to Figure 33.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
†
TPS7325QelectricalcharacteristicsatI =10mA, V =3.5V,EN=0V,C =10µF(CSR =1Ω),SENSE
shorted to OUT (unless otherwise noted)
O
I
o
‡
PARAMETER
MIN
TYP
MAX
2.55
T
TEST CONDITIONS
UNIT
J
25°C
2.45
2.5
Output voltage
V
3.5 V ≤ V ≤ 10 V,
5 mA ≤ I ≤ 500 mA
–40°C to 125°C 2.425
25°C
2.575
I
O
5
50
270
0.5
6
I
I
I
= 10 mA,
= 100 mA,
= 500 mA,
V = 2.97 V
I
O
O
O
–40°C to 125°C
25°C
14
80
§
V = 2.97 V
I
mV
Dropout voltage
–40°C to 125°C
25°C
150
400
600
0.7
1.4
20
V = 2.97 V
I
–40°C to 125°C
25°C
(2.97 V – V )/I ,
V = 2.97 V,
I
O
O
§
Pass-element series resistance
Ω
I
O
= 500 mA
–40°C to 125°C
25°C
Input regulation
V = 3.5 V to 10 V,
50 µA ≤ I ≤ 500 mA
mV
mV
mV
I
O
–40°C to 125°C
25°C
25
20
28
53
53
32
I
I
= 5 mA to 500 mA, 3.5 V ≤ V ≤ 10 V
I
O
–40°C to 125°C
25°C
50
Output regulation
Ripple rejection
60
= 50 µA to 500 mA, 3.5 V ≤ V ≤ 10 V
O
I
–40°C to 125°C
100
25°C
–40°C to 125°C
25°C
50
49
49
32
I
= 50 µA
O
O
f = 120 Hz
dB
I
= 500 mA
–40°C to 125°C
25°C
Output noise-spectral density
Output noise voltage
f = 120 Hz
2
274
228
159
2.32
0.14
µV/√Hz
µVrms
25°C
C
C
C
= 4.7 µF
= 10 µF
= 100 µF
o
o
o
25°C
10 Hz ≤ f ≤ 100 kHz
25°C
V
decreasing
–40°C to 125°C
25°C
2.23
2.39
0.4
V
V
RESET trip-threshold voltage
RESET output low voltage
O
V = 2.1 V,
I
= –0.8 mA
I
O(RESET)
–40°C to 125°C
0.4
†
‡
§
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to C .
o
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
Dropout test and pass-element series resistance test are not production tested. Test method requires SENSE terminal to be disconnected from
output voltage.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
†
TPS7330Q electrical characteristics at I = 10 mA, V = 4 V, EN = 0 V, C = 4.7 µF (CSR = 1 Ω), SENSE
shorted to OUT (unless otherwise noted)
O
I
o
‡
PARAMETER
MIN
TYP
MAX
T
J
TEST CONDITIONS
UNIT
25°C
–40°C to 125°C
25°C
3
Output voltage
V
4 V ≤ V ≤ 10 V,
5 mA ≤ I ≤ 500 mA
2.94
3.06
7
I
O
5.2
52
267
0.5
6
I
O
I
O
I
O
= 10 mA,
= 100 mA,
= 500 mA,
V = 2.94 V
I
–40°C to 125°C
25°C
10
75
V = 2.94 V
I
mV
Dropout voltage
–40°C to 125°C
25°C
100
450
500
0.7
1
V = 2.94 V
I
–40°C to 125°C
25°C
(2.94 V – V )/I ,
V = 2.94 V,
I
O
O
Pass-element series resistance
Input regulation
Ω
I
O
= 500 mA
–40°C to 125°C
25°C
23
V = 4 V to 10 V,
I
50 µA ≤ I ≤ 500 mA
mV
mV
mV
O
–40°C to 125°C
25°C
29
20
28
53
53
32
I
I
= 5 mA to 500 mA, 4 V ≤ V ≤ 10 V
I
O
–40°C to 125°C
25°C
60
Output regulation
Ripple rejection
60
= 50 µA to 500 mA, 4 V ≤ V ≤ 10 V
O
I
–40°C to 125°C
25°C
120
43
40
39
36
I
= 50 µA
O
O
–40°C to 125°C
25°C
f = 120 Hz
dB
I
= 500 mA
–40°C to 125°C
25°C
Output noise-spectral density
Output noise voltage
f = 120 Hz
2
274
228
159
2.64
0.14
µV/√Hz
µVrms
25°C
C
C
C
= 4.7 µF
= 10 µF
= 100 µF
o
o
o
25°C
10 Hz ≤ f ≤ 100 kHz
25°C
V
O
decreasing
–40°C to 125°C
25°C
2.58
2.7
0.4
0.4
V
V
RESET trip-threshold voltage
RESET output low voltage
V = 2.6 V,
I
I
= –0.8 mA
O(RESET)
–40°C to 125°C
†
‡
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to C .
o
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
†
TPS7333Q electrical characteristics at I = 10 mA, V = 4.3 V, EN = 0 V, C = 4.7 µF (CSR = 1 Ω),
SENSE shorted to OUT (unless otherwise noted)
O
I
o
‡
PARAMETER
MIN
TYP
MAX
T
J
TEST CONDITIONS
UNIT
25°C
3.3
Output voltage
V
4.3 V ≤ V ≤ 10 V,
5 mA ≤ I ≤ 500 mA –40°C to 125°C
3.23
3.37
7
I
O
25°C
4.5
44
I
O
I
O
I
O
= 10 mA,
= 100 mA,
= 500 mA,
V = 3.23 V
I
–40°C to 125°C
25°C
8
60
V = 3.23 V
I
mV
Dropout voltage
–40°C to 125°C
25°C
80
235
0.44
6
300
400
0.6
0.8
23
V = 3.23 V
I
–40°C to 125°C
25°C
(3.23 V – V )/I ,
V = 3.23 V,
I
O
O
Pass-element series resistance
Input regulation
Ω
I
O
= 500 mA
–40°C to 125°C
25°C
V = 4.3 V to 10 V,
I
50 µA ≤ I ≤ 500 mA
mV
mV
mV
O
–40°C to 125°C
25°C
29
21
38
I
I
= 5 mA to 500 mA, 4.3 V ≤ V ≤ 10 V
I
O
–40°C to 125°C
25°C
75
Output regulation
Ripple rejection
31
60
= 50 µA to 500 mA, 4.3 V ≤ V ≤ 10 V
O
I
–40°C to 125°C
25°C
120
43
40
39
36
51
I
= 50 µA
O
O
–40°C to 125°C
25°C
f = 120 Hz
dB
49
I
= 500 mA
–40°C to 125°C
25°C
Output noise-spectral density
Output noise voltage
f = 120 Hz
2
274
228
159
µV/√Hz
µVrms
25°C
C
C
C
= 4.7 µF
= 10 µF
= 100 µF
o
o
o
25°C
10 Hz ≤ f ≤ 100 kHz
25°C
V
O
decreasing
–40°C to 125°C 2.868
25°C
V
RESET trip-threshold voltage
RESET hysteresis voltage
18
mV
25°C
0.17
0.4
0.4
RESET output low voltage
V = 2.8 V,
I
I
= –1 mA
V
O(RESET)
–40°C to 125°C
†
‡
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to C .
o
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
†
TPS7348Q electrical characteristics at I = 10 mA, V = 5.85 V, EN = 0 V, C = 4.7 µF (CSR = 1 Ω),
SENSE shorted to OUT (unless otherwise noted)
O
I
o
‡
PARAMETER
MIN
TYP
MAX
T
J
TEST CONDITIONS
UNIT
25°C
4.85
Output voltage
V
5.85 V ≤ V ≤ 10 V,
5 mA ≤ I ≤ 500 mA –40°C to 125°C
4.75
4.95
6
I
O
25°C
2.9
28
I
O
I
O
I
O
= 10 mA,
= 100 mA,
= 500 mA,
V = 4.75 V
I
–40°C to 125°C
25°C
8
37
V = 4.75 V
I
mV
Dropout voltage
–40°C to 125°C
25°C
54
150
0.28
9
180
250
0.37
0.52
35
V = 4.75 V
I
–40°C to 125°C
25°C
(4.75 V – V )/I ,
V = 4.75 V,
I
O
O
Pass-element series resistance
Input regulation
Ω
I
O
= 500 mA
–40°C to 125°C
25°C
V = 5.85 V to 10 V,
I
50 µA ≤ I ≤ 500 mA
mV
mV
mV
O
–40°C to 125°C
25°C
37
28
42
I
I
= 5 mA to 500 mA, 5.85 V ≤ V ≤ 10 V
I
O
–40°C to 125°C
25°C
80
Output regulation
Ripple rejection
42
65
= 50 µA to 500 mA, 5.85 V ≤ V ≤ 10 V
O
I
–40°C to 125°C
25°C
130
42
39
39
35
53
I
= 50 µA
O
O
–40°C to 125°C
25°C
f = 120 Hz
dB
50
I
= 500 mA
–40°C to 125°C
25°C
Output noise-spectral density
Output noise voltage
f = 120 Hz
2
410
328
212
µV/√Hz
µVrms
25°C
C
C
C
= 4.7 µF
= 10 µF
= 100 µF
o
o
o
25°C
10 Hz ≤ f ≤ 100 kHz
25°C
V
O
decreasing
–40°C to 125°C
25°C
4.5
4.7
V
RESET trip-threshold voltage
RESET hysteresis voltage
26
mV
25°C
0.2
0.4
0.4
RESET output low voltage
I
= –1.2 mA,V = 4.12 V
V
O(RESET)
I
–40°C to 125°C
†
‡
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to C .
o
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
†
TPS7350Q electrical characteristics at I = 10 mA, V = 6 V, EN = 0 V, C = 4.7 µF (CSR = 1 Ω), SENSE
shorted to OUT (unless otherwise noted)
O
I
o
‡
PARAMETER
MIN
TYP
MAX
T
J
TEST CONDITIONS
UNIT
25°C
5
Output voltage
V
6 V ≤ V ≤ 10 V,
5 mA ≤ I ≤ 500 mA –40°C to 125°C
4.9
5.1
6
I
O
25°C
2.9
27
I
O
I
O
I
O
= 10 mA,
= 100 mA,
= 500 mA,
V = 4.88 V
I
–40°C to 125°C
25°C
8
35
V = 4.88 V
I
mV
Dropout voltage
–40°C to 125°C
25°C
50
146
0.27
4
170
230
0.35
0.5
25
V = 4.88 V
I
–40°C to 125°C
25°C
(4.88 V – V )/I ,
V = 4.88 V,
I
O
O
Pass-element series resistance
Input regulation
Ω
I
O
= 500 mA
–40°C to 125°C
25°C
V = 6 V to 10 V,
I
50 µA ≤ I ≤ 500 mA
mV
mV
mV
O
–40°C to 125°C
25°C
45
30
45
I
I
= 5 mA to 500 mA, 6 V ≤ V ≤ 10 V
I
O
–40°C to 125°C
25°C
86
Output regulation
Ripple rejection
45
65
= 50 µA to 500 mA, 6 V ≤ V ≤ 10 V
O
I
–40°C to 125°C
25°C
140
43
38
41
36
53
I
= 50 µA
O
O
–40°C to 125°C
25°C
f = 120 Hz
dB
51
I
= 500 mA
–40°C to 125°C
25°C
Output noise-spectral density
Output noise voltage
f = 120 Hz
2
430
345
220
µV/√Hz
µVrms
25°C
C
C
C
= 4.7 µF
= 10 µF
= 100 µF
o
o
o
25°C
10 Hz ≤ f ≤ 100 kHz
25°C
V
decreasing
–40°C to 125°C
4.55
4.75
V
RESET trip-threshold voltage
RESET hysteresis voltage
O
25°C
25°C
28
mV
0.15
0.4
0.4
RESET output low voltage
I
= –1.2 mA, V = 4.25 V
V
O(RESET)
I
–40°C to 125°C
†
‡
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to C .
o
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
switching characteristics
TPS7301Q, TPS7333Q
TPS7348Q, TPS7350Q
T
J
PARAMETER
TEST CONDITIONS
UNIT
MIN
140
100
TYP
MAX
260
25°C
200
RESET time-out delay
See Figure 5
ms
–40°C to 125°C
300
†
electrical characteristics at I = 10 mA, EN = 0 V, C = 4.7 µF (CSR = 1 Ω), T = 25°C, SENSE/FB
O
o
J
shorted to OUT (unless otherwise noted)
TPS7301Y, TPS7333Y
TPS7348Y, TPS7350Y
‡
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
EN ≤ 0.5 V,
0 mA ≤ I ≤ 500 mA
V = V + 1 V,
I O
Ground current (active mode)
340
µA
O
Input current (standby mode)
Output current limit
0.01
1.2
µA
A
EN = V ,
2.7 V ≤ V ≤ 10 V
I
I
V
O
= 0 V,
V = 10 V
I
Pass-element leakage current in standby mode
RESET leakage current
0.01
0.02
165
µA
µA
°C
V
EN = V ,
I
2.7 V ≤ V ≤ 10 V
I
Normal operation,
V at RESET = 10 V
Thermal shutdown junction temperature
EN logic low (active mode)
EN hysteresis voltage
2.7 V ≤ V ≤ 10 V
0.5
I
50
0.001
2.05
1
mV
µA
V
0 V ≤ V ≤ 10 V
EN input current
I
Minimum V for active pass element
I
I
= –300 µA
V
Minimum V for valid RESET
I
O(RESET)
†
CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any
series resistance added externally, and PWB trace resistance to C .
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
o
‡
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
†
TPS7301Y electrical characteristics at I = 10 mA, V = 3.5 V, EN = 0 V, C = 4.7 µF (CSR = 1 Ω),
O
I
o
T = 25°C, FB shorted to OUT at device leads (unless otherwise noted)
J
‡
PARAMETER
MIN
TYP
1.182
0.7
MAX
TEST CONDITIONS
UNIT
Reference voltage (measured at FB)
V
V = 2.4 V,
I
50 µA ≤ I ≤ 150 mA
O
V = 2.4 V,
I
150 mA ≤ I ≤ 500 mA
0.83
0.52
0.32
0.23
O
V = 2.9 V,
I
50 µA ≤ I ≤ 500 mA
Ω
Pass-element series resistance (See Note 2)
O
V = 3.9 V,
I
50 µA ≤ I ≤ 500 mA
O
V = 5.9 V,
I
50 µA ≤ I ≤ 500 mA
O
V = 2.5 V to 10 V,
I
50 µA ≤ I ≤ 500 mA,
O
Input regulation
3
5
mV
mV
mV
See Note 1
2.5 V ≤ V ≤ 10 V,
I
= 5 mA to 500 mA,
I
O
O
See Note 1
Output regulation
2.5 V ≤ V ≤ 10 V,
I
= 50 µA to 500 mA,
I
7
59
54
See Note 1
f = 120 Hz
f = 120 Hz
I
I
= 50 µA
O
Ripple rejection
dB
= 500 mA,
O
See Note 1
Output noise-spectral density
2
95
89
74
12
µV/√Hz
C
C
C
= 4.7 µF
= 10 µF
= 100 µF
o
o
o
Output noise voltage
10 Hz ≤ f ≤ 100 kHz
µVrms
§
mV
V
Measured at V
O(FB)
RESET hysteresis voltage
§
V = 2.13 V,
I
I
= 400 µA
0.1
0.1
RESET output low voltage
O(RESET)
FB input current
nA
†
‡
§
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to C .
o
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
Output voltage programmed to 2.5 V with closed-loop configuration (see application information).
NOTES: 1. When V < 2.9 V and I > 150 mA simultaneously, pass element r
DS(on)
increases (see Figure 33) to a point where the resulting
I
O
dropout voltage prevents the regulator from maintaining the specified tolerance range.
2. To calculate dropout voltage, use equation: = I
is a function of both output current and input voltage. The parametric table lists r
V
DO
r
DS(on)
O
r
for V = 2.4 V, 2.9 V, 3.9 V, and
I
DS(on)
DS(on)
5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V respectively. For other
programmed values, refer to Figure 33.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
†
TPS7325Y electrical characteristics at I = 10 mA, V = 3.5 V, EN = 0 V, C = 10 µF (CSR = 1 Ω),
O
I
o
T = 25°C, SENSE shorted to OUT (unless otherwise noted)
J
‡
PARAMETER
MIN
TYP
2.5
5
MAX
TEST CONDITIONS
UNIT
Output voltage
Dropout voltage
V
I
O
I
O
I
O
= 10 mA,
= 100 mA,
= 500 mA,
V = 2.97 V
I
§
V = 2.97 V
I
50
mV
V = 2.97 V
270
I
(2.97 V – V )/I ,
V = 2.97 V,
I
O
O
§
Pass-element series resistance
0.5
Ω
I
O
= 500 mA
Input regulation
V = 3.5 V to 10 V,
50 µA ≤ I ≤ 500 mA
6
20
mV
mV
mV
I
O
I
= 5 mA to 500 mA, 3.5 V ≤ V ≤ 10 V
I
O
O
Output regulation
I
= 50 µA to 500 mA, 3.5 V ≤ V ≤ 10 V
28
I
I
I
= 50 µA
53
O
Ripple rejection
f = 120 Hz
f = 120 Hz
dB
= 500 mA
53
O
Output noise-spectral density
2
µV/√Hz
274
228
159
0.14
C
C
C
I
= 4.7 µF
= 10 µF
= 100 µF
o
o
o
Output noise voltage
10 Hz ≤ f ≤ 100 kHz
µVrms
V = 2.1 V,
I
= –0.8 mA
V
RESET output low voltage
O(RESET)
†
‡
§
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to C .
o
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
Dropout test and pass-element series resistance test are not production tested. Test method requires SENSE terminal to be disconnected from
output voltage.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
†
TPS7330Y electrical characteristics at I = 10 mA, V = 4 V, EN = 0 V, C = 4.7 µF (CSR = 1 Ω),
O
I
o
T = 25°C, SENSE shorted to OUT (unless otherwise noted)
J
‡
PARAMETER
MIN
TYP
3
MAX
TEST CONDITIONS
UNIT
Output voltage
Dropout voltage
V
I
O
I
O
I
O
= 10 mA,
= 100 mA,
= 500 mA,
V = 2.94 V
I
5.2
52
V = 2.94 V
I
mV
V = 2.94 V
I
267
(2.94 V – V )/I ,
V = 2.94 V,
I
O
O
Pass-element series resistance
Input regulation
0.5
Ω
I
O
= 500 mA
V = 4 V to 10 V,
I
50 µA ≤ I ≤ 500 mA
6
20
mV
mV
mV
O
I
= 5 mA to 500 mA, 4 V ≤ V ≤ 10 V
I
O
O
Output regulation
I
= 50 µA to 500 mA, 4 V ≤ V ≤ 10 V
28
I
I
I
= 50 µA
53
O
Ripple rejection
f = 120 Hz
f = 120 Hz
dB
= 500 mA
53
O
Output noise-spectral density
2
µV/√Hz
274
228
159
0.14
C
C
C
I
= 4.7 µF
= 10 µF
= 100 µF
o
o
o
Output noise voltage
10 Hz ≤ f ≤ 100 kHz
µVrms
V = 2.6 V,
I
= –0.8 mA
V
RESET output low voltage
O(RESET)
†
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to C .
o
‡
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
†
TPS7333Y electrical characteristics at I = 10 mA, V = 4.3 V, EN = 0 V, C = 4.7 µF (CSR = 1 Ω),
O
I
o
T = 25°C, SENSE shorted to OUT (unless otherwise noted)
J
‡
PARAMETER
MIN
TYP
3.3
4.5
44
MAX
TEST CONDITIONS
UNIT
Output voltage
Dropout voltage
V
I
O
I
O
I
O
= 10 mA,
= 100 mA,
= 500 mA,
V = 3.23 V
I
V = 3.23 V
I
mV
V = 3.23 V
235
I
(3.23 V – V )/I ,
V = 3.23 V,
I
O
O
Pass-element series resistance
Input regulation
0.44
Ω
I
O
= 500 mA
V = 4.3 V to 10 V,
I
50 µA ≤ I ≤ 500 mA
6
21
mV
mV
mV
O
I
I
= 5 mA to 500 mA, 4.3 V ≤ V ≤ 10 V
I
O
Output regulation
= 50 µA to 500 mA, 4.3 V ≤ V ≤ 10 V
31
O
I
I
= 50 µA
51
O
O
Ripple rejection
f = 120 Hz
f = 120 Hz
dB
I
= 500 mA
49
Output noise-spectral density
2
µV/√Hz
274
228
159
18
C
C
C
= 4.7 µF
= 10 µF
= 100 µF
o
o
o
Output noise voltage
10 Hz ≤ f ≤ 100 kHz
µVrms
mV
V
RESET hysteresis voltage
RESET output low voltage
V = 2.8 V,
I
I
= –1 mA
0.17
O(RESET)
†
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to C .
o
‡
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
†
TPS7348Y electrical characteristics at I = 10 mA, V = 5.85 V, EN = 0 V, C = 4.7 µF (CSR = 1 Ω),
O
I
o
T = 25°C, SENSE shorted to OUT (unless otherwise noted)
J
‡
PARAMETER
MIN
TYP
4.85
2.9
MAX
TEST CONDITIONS
UNIT
Output voltage
Dropout voltage
V
I
O
I
O
I
O
= 10 mA,
= 100 mA,
= 500 mA,
V = 4.75 V
I
V = 4.75 V
I
28
mV
V = 4.75 V
150
I
(4.75 V – V )/I ,
V = 4.75 V,
I
O
O
Pass-element series resistance
Input regulation
0.28
Ω
I
O
= 500 mA
V = 5.85 V to 10 V,
I
50 µA ≤ I ≤ 500 mA
9
28
mV
mV
mV
O
I
= 5 mA to 500 mA,
5.85 V ≤ V ≤ 10 V
I
O
O
Output regulation
I
= 50 µA to 500 mA, 5.85 V ≤ V ≤ 10 V
42
I
I
I
= 50 µA
53
O
Ripple rejection
f = 120 Hz
f = 120 Hz
dB
= 500 mA
50
O
Output noise-spectral density
2
µV/√Hz
410
328
212
26
C
C
C
= 4.7 µF
= 10 µF
= 100 µF
o
o
o
Output noise voltage
10 Hz ≤ f ≤ 100 kHz
µVrms
mV
V
RESET hysteresis voltage
RESET output low voltage
I
= –1.2 mA, V = 4.12 V
0.2
O(RESET)
I
†
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to C .
o
‡
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
†
TPS7350Y electrical characteristics at I = 10 mA, V = 6 V, EN = 0 V, C = 4.7 µF (CSR = 1 Ω),
O
I
o
T = 25°C, SENSE shorted to OUT (unless otherwise noted)
J
‡
PARAMETER
MIN
TYP
5
MAX
TEST CONDITIONS
UNIT
Output voltage
Dropout voltage
V
I
O
I
O
I
O
= 10 mA,
= 100 mA,
= 500 mA,
V = 4.88 V
I
2.9
27
6
35
V = 4.88 V
I
mV
V = 4.88 V
I
146
170
(4.88 V – V )/I ,
V = 4.88 V,
I
O
O
Pass-element series resistance
Input regulation
0.27
0.35
Ω
I
O
= 500 mA
V = 6 V to 10 V,
I
50 µA ≤ I ≤ 500 mA
4
28
25
75
mV
mV
mV
O
I
= 5 mA to 500 mA,
6 V ≤ V ≤ 10 V
I
O
O
Output regulation
I
= 50 µA to 500 mA, 6 V ≤ V ≤ 10 V
41
I
I
I
= 50 µA
53
O
Ripple rejection
f = 120 Hz
f = 120 Hz
dB
= 500 mA
51
O
Output noise-spectral density
2
µV/√Hz
430
345
220
28
C
C
C
= 4.7 µF
= 10 µF
= 100 µF
o
o
o
Output noise voltage
10 Hz ≤ f ≤ 100 kHz
µVrms
mV
V
RESET hysteresis voltage
RESET output low voltage
I
= –1.2 mA, V = 4.25 V
0.15
0.4
O(RESET)
I
†
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to C .
o
‡
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
V
O
V
IT+
t
V
I
IN
Reset
RESET
EN
SENSE
OUT
V
RESET
O
+
RESET
Timeout Delay
0.1 µF
10 µF
GND
CSR
t
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 5. Test Circuit and Voltage Waveforms
To Load
IN
V
I
OUT
+
SENSE
C
†
O
C
cer
R
EN
L
GND
CSR
†
Ceramic capacitor
Figure 6. Test Circuit for Typical Regions of Stability (Refer to Figures 29 through 32)
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
Table of Graphs
vs Output current
vs Input voltage
7
8
I
I
I
Quiescent current
Quiescent current
Quiescent current
Q
Q
Q
TPS7348
TPS7325
vs Free-air temperature
vs Input voltage
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
vs Free-air temperature
vs Output current
vs Free-air temperature
vs Output current
vs Free-air temperature
vs Input voltage
V
Dropout voltage
DO
∆V
Change in dropout voltage
Dropout voltage
DO
V
TPS7301
TPS7325
DO
∆V
Change in output voltage
Output voltage
O
V
V
O
Output voltage
vs Input voltage
O
Line regulation
TPS7301
TPS7325
TPS7330
TPS7333
TPS7348
TPS7350
vs Output current
vs Output current
vs Output current
vs Output current
vs Output current
vs Output current
V
Output voltage
O
Output voltage response from enable (EN)
TPS7301 or TPS7333
TPS7325
TPS7348 or TPS7350
TPS7301
Load transient response
TPS7333
TPS7348 or TPS7350
Ripple rejection
vs Frequency
Output spectral noise density
vs Frequency
vs Output current
C
C
= 4.7 µF
= 10 µF
o
o
vs Added ceramic capacitance
vs Output current
Compensation series resistance
(CSR)
vs Added ceramic capacitance
r
Pass-element resistance
vs Input voltage
38
39
40
41
42
43
DS(on)
V
V
Minimum input voltage for valid RESET
Negative-going reset threshold
RESET output current
vs Free-air temperature
vs Free-air temperature
vs Input voltage
I
IT–
I
t
t
OL(RESET)
Reset time delay
vs Free-air temperature
d
d
Distribution for reset delay
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
QUIESCENT CURRENT
QUIESCENT CURRENT
vs
OUTPUT CURRENT
vs
INPUT VOLTAGE
500
450
425
400
375
350
T
= 25°C
= 500 mA
T
= 25°C
A
A
I
O
450
400
TPS73xx, V = 10 V
I
TPS7333
350
300
250
200
150
100
50
TPS7348
TPS7350
TPS7350, V = 6 V
I
TPS7301 With V
O
Programmed to 2.5 V
325
300
275
TPS7348, V = 5.85 V
I
TPS7333, V = 4.3 V
I
TPS7330, V = 4 V
I
TPS7325, V = 3.5 V
I
0
0
50
100
150
200
250
0
1
2
3
4
5
6
7
8
9
10
V – Input Voltage – V
I
I
O
– Output Current – mA
Figure 7
Figure 8
TPS7348
TPS7325
QUIESCENT CURRENT
vs
QUIESCENT CURRENT
vs
FREE-AIR TEMPERATURE
INPUT VOLTAGE
500
500
V = 5.85 V
I
O
I
= 500 mA
450
400
450
400
T
A
= 125°C
T
A
= 85°C
350
300
350
300
T
A
= 25°C
T
= 0°C
A
250
200
250
200
T
= –40°C
A
–50
–25
0
25
50
75
100
125
3
4
5
6
7
8
9
10
T
A
– Free-Air Temperature – °C
V – Input Voltage – V
I
Figure 9
Figure 10
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
TPS7325
QUIESCENT CURRENT
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
500
450
0.3
I
L
= 750 mA
T
A
= 25°C
TPS7330
TPS7333
0.25
400
V = 10 V
I
0.2
TPS7325
350
300
0.15
TPS7348
V = 3.5 V
I
0.1
0.05
0
TPS7350
250
200
–50
–25
0
25
50
75
100
125
0
50 100 150 200 250 300 350 400 450 500
T
A
– Free-Air Temperature – °C
I
O
– Output Current – mA
Figure 11
Figure 12
TPS7301
CHANGE IN DROPOUT VOLTAGE
vs
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
FREE-AIR TEMPERATURE
10
8
1.6
1.4
1.2
I
O
= 100 mA
T
A
= 25°C
V = 2.4 V
I
6
4
2
0
V = 2.6 V
I
V = 2.9 V
I
1
0.8
0.6
0.4
V = 3.2 V
I
V = 3.9 V
I
V = 5.9 V
I
–2
–4
V = 9.65 V
I
–6
0.2
0
–8
–10
–50
–25
0
25
50
75
100
125
0
50
100
150
200
250
T
A
– Free-Air Temperature – °C
I
O
– Output Current – mA
Figure 13
Figure 14
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
CHANGE IN OUTPUT VOLTAGE
vs
vs
INPUT VOLTAGE
FREE-AIR TEMPERATURE
6
5
4
3
2
1
20
15
10
5
T
= 25°C
= 500 mA
V = V
+ 1 V
A
I
O(nom)
TPS7350
I
O
I
O
= 100 mA
TPS7348
0
TPS7333
–5
TPS7301 With V
O
Programmed to 2.5 V
–10
–15
–20
and TPS7325
0
0
1
2
3
4
5
6
7
8
9
10
–50
–25
0
25
50
75
100
125
V – Input Voltage – V
I
T
A
– Free-Air Temperature – °C
Figure 15
Figure 16
TPS7325
OUTPUT VOLTAGE
vs
LINE REGULATION
INPUT VOLTAGE
3
2.5
2
20
15
T
= 25°C
= 250 mA
T
A
= 25°C
A
100 mA
500 mA
I
O
10
5
TPS7350
TPS7348
1.5
1
0
–5
TPS7333
TPS7325
–10
0.5
–15
–20
0
0
1
2
3
4
5
6
7
8
9
10
4
5
6
7
8
9
10
V – Input Voltage – V
I
V – Input Voltage – V
I
Figure 17
Figure 18
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
TPS7301
OUTPUT VOLTAGE
TPS7325
OUTPUT VOLTAGE
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
2.52
2.515
2.51
2.52
T
V
= 25°C
Programmed to 2.5 V
A
O
2.515
2.51
2.505
2.5
V = 10 V
I
2.505
2.5
V = 3.5 V
I
2.495
2.49
2.495
2.49
V = 10 V
I
V = 3.5 V
I
2.485
2.48
2.485
2.48
0
100
200
300
400
500
0
100
200
300
400
500
I
O
– Output Current – mA
I
O
– Output Current – mA
Figure 19
Figure 20
TPS7333
TPS7330
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.34
3.33
3.32
3.31
3.3
3.15
3.12
T
A
= 25°C
T
A
= 25°C
3.09
3.06
3.03
V = 10 V
I
3
2.97
2.94
2.91
2.88
V = 4.3 V
I
3.29
3.28
3.27
3.26
2.85
0
100
200
300
400
500
0
100
I
200
300
400
500
– Output Current – mA
I
O
– Output Current – mA
O
Figure 21
Figure 22
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
TPS7350
TPS7348
OUTPUT VOLTAGE
vs
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT CURRENT
5.06
5.05
5.04
5.03
5.02
5.01
5
4.92
4.91
4.9
T
A
= 25°C
T
A
= 25°C
4.89
4.88
4.87
4.86
4.85
4.84
V = 6 V
I
V = 5.85 V
I
4.99
4.98
V = 10 V
I
V = 10 V
I
4.97
4.96
4.95
4.94
4.83
4.82
4.81
4.8
0
100
200
300
400
500
0
100
200
300
400
500
I
O
– Output Current – mA
I
O
– Output Current – mA
Figure 23
Figure 24
OUTPUT VOLTAGE RESPONSE FROM
ENABLE (EN)
6
4
V
O(nom)
2
0
T
R
C
= 25°C
= 500 Ω
= 4.7 µF (CSR = 1Ω)
A
L
o
6
4
No Input Capacitance
2
0
–2
0
20 40 60 80 100 120 140
Time – µs
Figure 25
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
TPS7301 (WITH V PROGRAMMED TO 2.5 V) OR TPS7333
O
LOAD TRANSIENT RESPONSE
200
100
0
T
= 25°C
A
I
I
o
–100
–200
V = 6 V
C = 0
C
= 4.7 µF (CSR = 1 Ω)
105
55
5
–45
0
100
200
300
400
500
t – Time – µs
Figure 26
TPS7325
LOAD TRANSIENT RESPONSE
150
100
50
0
–50
–100
–150
–200
–250
∆I = 100 mA
O
V = 6 V
I
C = 0
I
o
A
C
T
= 10 µF
= 25°C
–300 –200 –100
0
100 200 300 400 500 600
t – Time – µs
Figure 27
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
TPS7348 OR TPS7350
LOAD TRANSIENT RESPONSE
200
100
0
V = 6 V
I
–100
–200
C = 0
I
o
C
= 4.7 µF
CSR = 1 Ω
T
A
= 25°C
105
55
5
–45
500
0
100
200
300
400
t – Time – µs
Figure 28
TPS7301 WITH V PROGRAMMED TO 2.5 V
O
LINE TRANSIENT RESPONSE
100
50
0
T
= 25°C
A
I
o
–50
–100
C = 0
C
= 4.7 µF (CSR = 1 Ω)
6.5
6.25
6
5.75
400
0
100
200
300
t – Time – µs
Figure 29
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
TPS7333
LINE TRANSIENT RESPONSE
200
100
0
–50
T
= 25°C
A
I
o
C = 0
C
= 4.7 µF (CSR = 1 Ω)
–100
6.5
6.25
6
5.75
0
100
200
300
400
500
t – Time – µs
Figure 30
TPS7348 OR TPS7350
LINE TRANSIENT RESPONSE
100
50
0
–50
–100
T
= 25°C
A
I
o
C = 0
C
= 4.7 µF (CSR = 1 Ω)
6.5
6.25
6
5.75
0
100
200
300
400
500
t – Time – µs
Figure 31
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
RIPPLE REJECTION
vs
OUTPUT SPECTRAL-NOISE DENSITY
vs
FREQUENCY
FREQUENCY
60
50
10
TPS7333
T
= 25°C
A
T
= 25°C
A
No Input
Capacitance Added
V = V + 1 V
No Input Capacitance Added
V = V + 1 V
I
O
I
O
I
C
= 100 mA
O
C
= 4.7 µF (CSR = 1 Ω)
o
= 4.7 µF (CSR = 1)
o
40
30
20
1
TPS7348/
TPS7350
TPS7301 With
C
= 10 µF (CSR = 1 Ω)
o
V
Programmed
O
to 2.5 V
0.1
10
0
C
= 100 µF (CSR = 1 Ω)
o
0.01
10
100
1 K
10 K
100 K
1 M
10 M
10
100
1 k
10 k
100 k
f – Frequency – Hz
f – Frequency – Hz
Figure 32
Figure 33
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY
†
†
COMPENSATION SERIES RESISTANCE (CSR)
COMPENSATION SERIES RESISTANCE (CSR)
vs
vs
OUTPUT CURRENT
ADDED CERAMIC CAPACITANCE
100
100
10
T
= 25°C
Region of
Instability
A
I
Region of Instability
V = V + 1 V
O
I
C
= 500 mA
O
= 4.7 µF
o
10
1
No Input Capacitor Added
1
T
= 25°C
A
I
o
V = V + 1 V
C
O
0.1
0.1
= 4.7 µF
Region of Instability
No Added Ceramic Capacitance
No Input Capacitance Added
Region of Instability
50 100
0.01
0.01
0
150
200
250
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
I
O
– Output Current – mA
Added Ceramic Capacitance – µF
Figure 34
Figure 35
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TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE (CSR)
vs
†
†
COMPENSATION SERIES RESISTANCE (CSR)
vs
OUTPUT CURRENT
ADDED CERAMIC CAPACITANCE
100
100
T
= 25°C
Region of
Instability
A
I
Region of Instability
V = V + 1 V
O
I
C
= 500 mA
O
= 10 µF
o
10
1
10
No Input Capacitor Added
T
= 25°C
A
I
C
V = V + 1 V
O
1
= 10 µF
o
No Added Ceramic Capacitance
No Input Capacitor Added
0.1
0.1
Region of Instability
Region of Instability
0.01
0.01
0
50
100
150
200
250
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
I
O
– Output Current – mA
Added Ceramic Capacitance – µF
Figure 36
Figure 37
MINIMUM INPUT VOLTAGE FOR VALID RESET
PASS-ELEMENT RESISTANCE
vs
vs
FREE-AIR TEMPERATURE
INPUT VOLTAGE
1.1
1.1
1
T
V
= 25°C
A
= 1.12 V
I(FB)
0.9
0.8
0.7
1.09
I
= 500 mA
O
1.08
1.07
0.6
0.5
0.4
I
= 100 mA
O
1.06
1.05
0.3
0.2
0.1
–50
–25
0
25
50
75
100
125
2
3
4
5
6
7
8
9
10
T
A
– Free-Air Temperature – °C
V – Input Voltage – V
I
Figure 38
Figure 39
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LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
NEGATIVE-GOING RESET THRESHOLD
RESET OUTPUT CURRENT
vs
vs
FREE-AIR TEMPERATURE
INPUT VOLTAGE
4
3.5
3
15
I
V
T
= 10 mA
L
≤ 0.4 V
= 25°C
OL
A
10
5
2.5
2
0
TPS7350
1.5
1
–5
–10
–15
TPS7348
TPS7333
0.5
0
–50
–25
0
25
50
75
100
125
0
1
2
3
4
5
6
7
8
9
10
T
A
– Free-Air Temperature – °C
V – Input Voltage – V
I
Figure 40
Figure 41
RESET DELAY TIME
vs
FREE-AIR TEMPERATURE
DISTRIBUTION FOR RESET DELAY
50
197
196
195
194
193
192
T
= 25°C
A
45
40
35
30
25
20
15
10
5
197 Devices
191
190
0
180
185
190
195
200
205
210
–50
–25
0
25
50
75
100
125
t
– Reset Delay Time – ms
d
T
A
– Free-Air Temperature –°C
Figure 42
Figure 43
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LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
THERMAL INFORMATION
In response to system-miniaturization trends, integrated circuits are being offered in low-profile and fine-pitch
surface-mount packages. Implementation of many of today’s high-performance devices in these packages requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat
sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation
limits of a given component.
Three basic approaches for enhancing thermal performance are illustrated in this discussion:
Improving the power-dissipation capability of the PWB design
Improving the thermal coupling of the component to the PWB
Introducing airflow in the system
Figure 44 is an example of a thermally enhanced PWB layout for the 20-lead TSSOP package. This layout involves
adding copper on the PWB to conduct heat away from the device. The R
(thermal resistance, junction-to-ambient)
θJA
for this component/board system is illustrated in Figure 45. The family of curves illustrates the effect of increasing
the size of the copper-heat-sink surface area. The PWB is a standard FR4 board (L × W × H = 3.2 inch × 3.2 inch
× 0.062 inch); the board traces and heat sink area are 1-oz (per square foot) copper.
Figure 46 shows the thermal resistance for the same system with the addition of a thermally-conductive compound
between the body of the TSSOP package and the PWB copper routed directly beneath the device. The thermal
conductivity for the compound used in this analysis is 0.815 W/m × °C.
Using these figures to determine the system R
the equation:
allows the maximum power-dissipation limit to be calculated with
θJA
T
T
J(max)
A
P
D(max)
R
JA(system)
Where
T
is the maximum allowable junction temperature; 150°C absolute maximum and 125°C
J(max)
maximum recommended operating temperature for specified operation.
This limit should then be applied to the internal power dissipated by the TPS73xx regulator. The equation for
calculating total internal power dissipation of the TPS73xx is:
P
V
V
I
V
I
D(total)
I
O
O
I
Q
Because the quiescent current of the TPS73xx family is very low, the second term is negligible, further simplifying
the equation to:
P
V
V
I
D(total)
I
O
O
For a 20-lead TSSOP/FR4 board system with thermally conductive compound between the board and the device
2
body, where T = 55°C, airflow = 100 ft/min, and copper heat sink area = 1 cm , the maximum power-dissipation limit
A
can be calculated. As indicated in Figure 46, the system R
limit is:
is 94°C/W; therefore, the maximum power-dissipation
θJA
T
T
J(max)
A
°
°
125 C 55 C
P
745 mW
D(max)
°
R
94 C W
JA(system)
If the system implements a TPS7348 regulator where V = 6 V and I = 150 mA, the internal power dissipation is:
I
O
P
V
V
I
(6 4.85)
0.150
173 mW
D(total)
I
O
O
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LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
THERMAL INFORMATION
Comparing P
with P
reveals that the power dissipation in this example does not exceed the maximum
D(total)
D(max)
limit. When it does, one of two corrective actions can be taken. The power-dissipation limit can be raised by increasing
either the airflow or the heat-sink area. Alternatively, the internal power dissipation of the regulator can be lowered
by reducing either the input voltage or the load current. In either case, the above calculations should be repeated with
the new system parameters.
Copper Heat Sink
1 oz Cu
Figure 44. Thermally Enhanced PWB Layout (not to scale) for the 20-Pin TSSOP
THERMAL RESISTANCE, JUNCTION-TO-AMBIENT
THERMAL RESISTANCE, JUNCTION-TO-AMBIENT
vs
vs
AIR FLOW
AIR FLOW
190
190
Component/Board System
Component/Board System
20-Lead TSSOP
Includes Thermally Conductive
Compound Between Body and Board
20-Lead TSSOP
170
170
2
0 cm
2
1 cm
150
150
130
110
90
2
2 cm
2
0 cm
130
110
90
2
8 cm
2
4 cm
2
2 cm
2
1 cm
2
4 cm
2
8 cm
70
70
50
50
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Air Flow – ft/min
Air Flow – ft/min
Figure 45
Figure 46
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LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
APPLICATION INFORMATION
The TPS73xx series of low-dropout (LDO) regulators overcome many of the shortcomings of earlier generation
LDOs, while adding features such as a power-saving shutdown mode and a supply-voltage supervisor. The
TPS73xx family includes five fixed-output voltage regulators: the TPS7325 (2.5 V), TPS7330 (3 V), TPS7333
(3.3 V), the TPS7348 (4.85 V), and the TPS7350 (5 V). The family also offers an adjustable device, the TPS7301
(adjustable from 1.2 V to 9.75 V).
device operation
The TPS73xx, unlike many other LDOs, features very low quiescent currents that remain virtually constant even
with varying loads. Conventional LDO regulators use a pnp-pass element, the base current of which is directly
proportional to the load current through the regulator (I = I /β). Close examination of the data sheets reveals
B
C
that such devices are typically specified under near no-load conditions; actual operating currents are much
higher as evidenced by typical quiescent current versus load current curves (see Figure 7). The TPS73xx uses
a PMOS transistor to pass current; because the gate of the PMOS element is voltage driven, operating currents
are low and invariable over the full load range. The TPS73xx specifications reflect actual performance under
load.
Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into
dropout. The resulting drop in β forces an increase in I to maintain the load. During power-up, this translates
B
to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems,
it means rapid battery discharge when the voltage decays below the minimum required for regulation. The
TPS73xx quiescent current remains low even when the regulator drops out, thus eliminating both problems.
Included in the TPS73xx family is a 4.85-V regulator, the TPS7348. Designed specifically for 5-V cellular
systems, its 4.85-V output, regulated to within ± 2%, allows for operation within the low-end limit of 5-V systems
specified to ± 5% tolerance; therefore, maximum regulated operating lifetime is obtained from a battery pack
before the device drops out, adding crucial talk minutes between charges.
The TPS73xx family also features a shutdown mode that places the output in the high-impedance state
(essentially equal to the feedback-divider resistance) and reduces quiescent current to under 0.5 µA. When the
shutdown feature is not used, EN should be tied to ground. Response to an enable transition is quick; regulated
output voltage is reestablished in typically 120 µs.
minimum load requirements
The TPS73xx family is stable even at zero load; no minimum load is required for operation.
SENSE connection
The SENSE terminal of fixed-output devices must be connected to the regulator output for proper functioning
of the regulator. Normally, this connection should be as short as possible; however, the connection can be made
near a critical circuit (remote sense) to improve performance at that point. Internally, SENSE connects to a
high-impedance wide-bandwidth amplifier through a resistor-divider network, and noise pickup feeds through
to the regulator output. It is essential to route the SENSE connection in such a way as to minimize/avoid noise
pickup. Adding an RC network between SENSE and OUT to filter noise is not recommended because it can
cause the regulator to oscillate.
external capacitor requirements
An input capacitor is not required; however, a ceramic bypass capacitor (0.047 pF to 0.1 µF) improves load
transient response and noise rejection when the TPS73xx is located more than a few inches from the power
supply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load
transients with fast rise times are anticipated.
35
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LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
APPLICATION INFORMATION
external capacitor requirements (continued)
As with most LDO regulators, the TPS73xx family requires an output capacitor for stability. A low-ESR 10-µF
solid-tantalum capacitor connected from the regulator output to ground is sufficient to ensure stability over the
full load range (see Figure 42). Adding high-frequency ceramic or film capacitors (such as power-supply bypass
capacitors for digital or analog ICs) can cause the regulator to become unstable unless the ESR of the tantalum
capacitor is less than 1.2 Ω over temperature. Capacitors with published ESR specifications such as the
AVX TPSD106M035R0300 and the Sprague 593D106X0035D2W work well because the maximum ESR at
25°C is 300 mΩ (typically, the ESR in solid-tantalum capacitors increases by a factor of 2 or less when the
temperature drops from 25°C to –40°C). Where component height and/or mounting area is a problem,
physically smaller, 10-µF devices can be screened for ESR. Figures 29 through 32 show the stable regions of
operation using different values of output capacitance with various values of ceramic load capacitance.
In applications with little or no high-frequency bypass capacitance (< 0.2 µF), the output capacitance can be
reduced to 4.7 µF, provided ESR is maintained between 0.7 and 2.5 Ω. Because capacitor minimum ESR is
seldom if ever specified, it may be necessary to add a 0.5-Ω to 1-Ω resistor in series with the capacitor and limit
ESR to 1.5 Ω maximum. As shown in the CSR graphs (Figures 29 through 32), minimum ESR is not a problem
when using 10-µF or larger output capacitors.
Below is a partial listing of surface-mount capacitors usable with the TPS73xx family. This information, along
with the CSR graphs, is included to assist in selection of suitable capacitance for the user’s application. When
necessary to achieve low height requirements along with high output current and/or high ceramic load
capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above.
All load and temperature conditions with up to 1 µF of added ceramic load capacitance:
†
†
†
†
PART NO.
MFR.
VALUE
MAX ESR
0.5
SIZE (H × L × W)
2.8 × 6 × 3.2
T421C226M010AS
593D156X0025D2W
593D106X0035D2W
Kemet
22 µF, 10 V
Sprague 15 µF, 25 V
Sprague 10 µF, 35 V
0.3
2.8 × 7.3 × 4.3
2.8 × 7.3 × 4.3
2.8 × 7.3 × 4.3
0.3
TPSD106M035R0300 AVX
10 µF, 35 V
0.3
Load < 200 mA, ceramic load capacitance < 0.2 µF, full temperature range:
†
PART NO.
MFR.
VALUE
MAX ESR
SIZE (H × L × W)
1.2 × 7.2 × 6
592D156X0020R2T
595D156X0025C2T
595D106X0025C2T
293D226X0016D2W
Sprague 15 µF, 20 V
Sprague 15 µF, 25 V
Sprague 10 µF, 25 V
Sprague 22 µF, 16 V
1.1
1
2.5 × 7.1 × 3.2
2.5 × 7.1 × 3.2
2.8 × 7.3 × 4.3
1.2
1.1
Load < 100 mA, ceramic load capacitance < 0.2 µF, full temperature range:
†
PART NO.
MFR.
VALUE
MAX ESR
1.5
SIZE (H × L × W)
1.3 × 3.5 × 2.7
1.3 × 7 × 2.7
195D106X06R3V2T
195D106X0016X2T
595D156X0016B2T
695D226X0015F2T
695D156X0020F2T
695D106X0035G2T
Sprague 10 µF, 6.3 V
Sprague 10 µF, 16 V
Sprague 15 µF, 16 V
Sprague 22 µF, 15 V
Sprague 15 µF, 20 V
Sprague 10 µF, 35 V
1.5
1.8
1.6 × 3.8 × 2.6
1.8 × 6.5 × 3.4
1.8 × 6.5 × 3.4
2.5 × 7.6 × 2.5
1.4
1.5
1.3
†
Size is in mm. ESR is maximum resistance at 100 kHz and T = 25°C. Listings are sorted by height.
A
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LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
APPLICATION INFORMATION
external capacitor requirements (continued)
†
TPS73xxPW
8
20
15
14
13
To System
Reset
V
IN
RESET
I
9
250 kΩ
IN
IN
SENSE
OUT
10
V
O
6
0.1 µF
EN
OUT
+
10 µF
GND
1
2
3
CSR = 1 Ω
†
TPS7333, TPS7348, TPS7350 (fixed-voltage options)
Figure 47. Typical Application Circuit
programming the TPS7301 adjustable LDO regulator
Programming the adjustable regulators is accomplished using an external resistor divider as shown in
Figure 43. The equation governing the output voltage is:
R1
R2
V
V
1
O
ref
Where
V
= reference voltage, 1.182 V typ
ref
37
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WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
APPLICATION INFORMATION
Resistors R1 and R2 should be chosen for approximately 7-µA divider current. A recommended value for R2
is 169 kΩ with R1 adjusted for the desired output voltage. Smaller resistors can be used, but offer no inherent
advantage and consume more power. Larger values of R1 and R2 should be avoided as leakage currents at
FB will introduce an error. Solving for R1 yields a more useful equation for choosing the appropriate resistance:
V
O
R1
1
R2
V
ref
OUTPUT VOLTAGE
PROGRAMMING GUIDE
TPS7301
OUTPUT
VOLTAGE
R1
R2
UNIT
To System
Reset
V
IN
RESET
OUT
FB
I
0.1 µF
2.5 V
3.3 V
3.6 V
4 V
191
309
348
402
549
750
169
169
169
169
169
169
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
250 kΩ
>2.7 V
EN
V
O
<0.5 V
+
R1
R2
10 µF
5 V
CSR = 1 Ω
GND
6.4 V
Figure 48. TPS7301 Adjustable LDO Regulator Programming
undervoltage supervisor function
The RESET output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event
ofanundervoltagecondition. AninternalcomparatorintheTPS73xxmonitorstheoutputvoltageoftheregulator
to detect the undervoltage condition. When that occurs, the RESET output transistor turns on taking the RESET
signal low.
On power up, the output voltage tracks the input voltage. The RESET output becomes active (low) as V
approaches the minimum required for a valid RESET signal (specified at 1.5 V for 25°C and 1.9 V over full
I
recommended operating temperature range). When the output voltage reaches the appropriate positive-going
input threshold (V ), a 200-ms (typical) timeout period begins during which the RESET output remains low.
IT+
Once the timeout has expired, the RESET output becomes inactive. Since the RESET output is an open-drain
NMOS, a pullup resistor should be used to ensure that a logic-high signal is indicated.
The supply-voltage-supervisor function is also activated during power-down. As the input voltage decays and
after the dropout voltage is reached, the output voltage tracks linearly with the decaying input voltage. When
the output voltage drops below the specified negative-going input threshold (V
— see electrical
IT–
characteristics tables), the RESET output becomes active (low). It is important to note that if the input voltage
decays below the minimum required for a valid RESET, the RESET is undefined.
Since the circuit is monitoring the regulator output voltage, the RESET output can also be triggered by disabling
the regulator or by any fault condition that causes the output to drop below V . Examples of fault conditions
IT–
include a short circuit on the output and a low input voltage. Once the output voltage is reestablished, either by
reenabling the regulator or removing the fault condition, then the internal timer is initiated, which holds the
RESET signal active during the 200-ms (typical) timeout period.
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WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
APPLICATION INFORMATION
undervoltage supervisor function (continued)
Transient loads or line pulses can also cause a reset to occur if proper care is not taken in selecting the input
and output capacitors. Load transients that are faster than 5 µs can cause a reset if high-ESR output capacitors
(greater than approximately 7 Ω) are used. A 1-µs transient causes a reset when using an output capacitor with
greater than 3.5 Ω of ESR. Note that the output-voltage spike during the transient can drop well below the reset
threshold and still not trip if the transient duration is short. A 1-µs transient must drop at least 500 mV below the
threshold before tripping the reset circuit. A 2-µs transient trips RESET at just 400 mV below the threshold.
Lower-ESR output capacitors help by reducing the drop in output voltage during a transient and should be used
when fast transients are expected.
NOTE:
V
= V
+Hysteresis
IT+
IT–
output noise
The TPS73xx has very low output noise, with a spectral noise density < 2 µV/√Hz. This is important when
noise-susceptible systems, such as audio amplifiers, are powered by the regulator.
regulator protection
The TPS73xx PMOS-pass transistor has a built-in back diode that safely conducts reverse currents when the
input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output
to the input and is not internally limited. If extended reverse voltage is anticipated, external limiting might be
appropriate.
The TPS73xx also features internal current limiting and thermal protection. During normal operation, the
TPS73xx limits output current to approximately 1 A. When current limiting engages, the output voltage scales
back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device
failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of
the device exceeds 165°C, thermal-protection circuitry shuts it down. Once the device has cooled, regulator
operation resumes.
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°–8°
0.044 (1,12)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
40
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TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
MECHANICAL DATA
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE PACKAGE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
4040082/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,30
0,19
0,65
M
0,10
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
0,75
0,50
A
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/E 08/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
42
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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