TDA7348_07 [STMICROELECTRONICS]
Digitally controlled audio processor; 数字控制音频处理器
| 型号： | TDA7348_07 |
| 厂家： | 
ST |
| 描述： | Digitally controlled audio processor |
| 文件： | 总20页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDA7348
Digitally controlled audio processor
Features
●
Input multiplexer
–
–
Three stereo and one mono inputs
Selectable input gain for optimal
adaptation to different sources
●
Volume control in 0.3db steps including gain
up to 20dB
●
●
●
Zero crossing mute and direct mute
Pause detector with programmable threshold
SO-28
Soft mute controlled by software or hardware
PIN
●
●
Bass and treble control
Four speaker attenuators
–
Four independent speakers control in
1.25dB steps for balance and fader
facilities
instead of standard bipolar multipliers, very low
distortion and very low noise are obtained Several
new features like softmute, zero-crossing mute
and pause detector are implemented.
–
Independent mute function
●
All functions programmable via serial I2C bus
The Soft Mute function can be activated in two
ways, either via the serial bus (bit D0, Mute Byte),
or directly on pin 22 through an I/O line of the
microcontroller
Description
The TDA7348 is an upgrade of the TDA7318
audioprocessor.
Very low DC stepping is obtained by use of a
BICMOS technology.
Thanks to the used BIPOLAR/CMOS technology,
very low distortion, low noise and DC-stepping
are obtained. Due to a highly linear signal
processing, using CMOS-switching techniques
Order codes
Part number
Package
Packing
TDA7348D
TDA7348D013TR
E-TDA7348D (1)
SO-28
SO-28
SO-28
SO-28
Tube
Tape and reel
Tube
E-TDA7348D013TR (1)
Tape and reel
1. This device is Pb-free Ecopack , see Chapter 5 Package information.
January 2007
Rev 3
1/20
www.st.com
1
Contents
TDA7348
Contents
1
2
3
Block diagram and PIN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
I C BUS interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
3.2
3.3
3.4
3.5
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Transmission without acknowledgement . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Software specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
4.2
4.3
4.4
Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Auto increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Transmitted data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20
TDA7348
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Send mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Loudness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Speaker attenuators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bass/Treble. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3/20
List of figures
TDA7348
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PIN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Data validity on the I C BUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2
Timing diagram of I C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2
Acknowledge on the I C BUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SO-28 mechanical, data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4/20
TDA7348
1
Block diagram and PIN connections
Block diagram and PIN connections
Figure 1.
Block diagram
R2
4.7K
C10 2.2μF
C14
C16
2.7nF
C15
100nF
100nF
OUT(L)
17
IN(L)
16
SM BOUT(L)
19
BIN(L)
18
TREBLE(L)
22
4
SPKR
ATT
3 x
1μF
RB
26
24
L1
L2
L3
14
13
12
L1
L2
L3
L4
OUT
LEFT FRONT
C1
MUTE
LEFT
ZERO
CROSS +
MUTE
VOL
1, 2
INPUTS
C2
C3
BASS
TREBLE
SPKR
ATT
OUT
LEFT REAR
MUTE
C4
28
27
11
INPUT
SELECTOR
+ GAIN
SCL
SDA
SOFT
MUTE
SERIAL BUS DECODER + LATCHES
BUS
SPKR
ATT
R4
R3
R2
R1
3 x
1μF
25
OUT
R3
R2
R1
8
ZERO
CROSS +
MUTE
RIGHT FRONT
C7
C6
C5
MUTE
VOL
1, 2
9
BASS
TREBLE
RIGHT
INPUTS
10
SPKR
ATT
23
RB
2
OUT
RIGHT REAR
VS
SUPPLY
MUTE
3
1
7
6
15
21
20
BOUT(R)
5
AGND
CREF
C8
OUT(R)
IN(R)
CSM
BIN(R)
TREBLE(R)
D93AU100B
10μF
CSM
47nF
C11
100nF
C12
C13
2.7nF
100nF
C9 2.2μF
R1
4.7K
Figure 2.
PIN connections
CREF
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SCL
SDA
BUS
INPUTS
VS
GND
L
2
3
OUT LF
OUT RF
OUT LR
OUT RR
SM
4
TREBLE
R
5
IN(R)
OUT(R)
IN R3
IN R2
IN R1
6
7
8
BOUT(R)
BIN(R)
BOUT(L)
BIN(L)
9
BASS
10
11
12
13
14
AM MONO
IN L3
OUT(L)
IN(L)
IN L2
IN L1
CSM
D94AU099
5/20
Electrical characteristics
TDA7348
2
Electrical characteristics
Table 1.
Electrical characteristics
VS = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C; all controls flat (G = 0.3dB step
0dB); f = 1KHz. Refer to the test circuit, unless otherwise specified.
Symbol
Parameter
Test Condition
Min. Typ. Max. Unit
Input selector
RI
VCL
SI
Input resistance
Clipping level
70
2.1
80
100
2.6
130
KΩ
VRMS
dB
d ≤ 0.3%
Input separation
100
RL
Output load resistance
2
KΩ
GI MIN Minimum input gain
GI MAX Maximum input gain
-0.75
0
0.75
dB
10.25 11.25 12.25 dB
Gstep
eN
Step resolution
Input noise
2.75 3.75 4.75
2.3
dB
μV
20Hz to 20 KHz unweighted
Adiacent gain steps
1.5
3
10
mV
mV
VDC
DC steps
G
IMIN to GIMAX
Volume control (1 + 2)
RI
Input resistance
Maximum gain
35
50
KΩ
GMAX
AMAX
18.75 20 21.25 dB
Maximum attenuation
78.45
1.25
dB
dB
Step resolution coarse
attenuation
ASTEPC
0.5
2.0
Step resolution fine
attenuation
ASTEPF
0.11 0.31 0.51
dB
G = 20 to -20dB
G = -20 to -58dB
-1.25
-3
0
1.25
dB
dB
EA
Et
Attenuation set error
Tracking error
DC steps
2
2
3
5
dB
Adiacent attenuation steps
From 0dB to AMAX
-3
0
mV
mV
VDC
0.5
Zero crossing mute
WIN = 11
WIN = 10
WIN = 01
WIN = 00
20
40
mV
mV
mV
mV
dB
Zero crossing threshold
VTH
80
160
100
0
AMUTE Mute attenuation
80
VDC
DC step
0dB to Mute
3
mV
6/20
TDA7348
Electrical characteristics
Table 1.
Electrical characteristics (continued)
VS = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C; all controls flat (G = 0.3dB step
0dB); f = 1KHz. Refer to the test circuit, unless otherwise specified.
Symbol
Parameter
Test Condition
Min. Typ. Max. Unit
Soft mute
AMUTE Mute attenuation
TDON ON delay time
45
60
1
dB
ms
C
IMAX
CSM = 22nF; 0 to -20dB; I =
0.7
1.7
CCSM = 22nF; 0 to -20dB; I =
IMIN
20
25
35
55
75
ms
V
CSM = 0V; I = IMAX
50
1
μA
μA
V
TDOFF OFF delay time
VCSM = 0V; I = IMIN
VTHSM Soft mute threshold
1.5
35
2.5
50
3.5
65
RINT
VSMH
VSML
Pull-up resistor (pin 22)
(pin 22) level high
(pin 22) level low
KΩ
V
Soft Mute active
3.5
1
V
Bass control
BBOOST Max bass boost
15
-8.5
1
18
20
dB
BCUT
Astep
Rg
Max bass cut
-10 -11.5 dB
Step resolution
2
3
dB
Internal feedback resistance
45
65
85
KΩ
Treble control
CRANGE Control range
±13
±14
±15
dB
dB
Astep
Step resolution
1
2
3
Speaker attenuators
CRANGE Control range
35
0.5
80
37.5
1.25
100
40
dB
dB
dB
dB
mV
Astep
Step resolution
2.0
AMUTE Output mute attenuation
Data word = XXX11111
EA
Attenuation set error
DC steps
1.25
3
VDC
Adjacent attenuation steps
0
Audio output
Vclip
RL
Clipping level
d = 0.3%
2.1
2
2.6
Vrms
KΩ
W
Output load resistance
Output impedance
DC voltage level
RO
30
100
4.1
VDC
3.5
6
3.8
V
General
VCC
Supply voltage
9
10.2
V
7/20
Electrical characteristics
Table 1.
TDA7348
Electrical characteristics (continued)
VS = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C; all controls flat (G = 0.3dB step
0dB); f = 1KHz. Refer to the test circuit, unless otherwise specified.
Symbol
Parameter
Supply current
Test Condition
Min. Typ. Max. Unit
ICC
5
10
80
65
15
mA
dB
dB
f = 1KHz
60
PSRR Power supply rejection ratio
B = 20 to 20kHz "A" weighted
Output Muted (B = 20 to
20kHz flat)
2.5
5
μV
μV
eNO
Output noise
All Gains 0dB (B = 20 to
20kHz flat)
15
AV= 0 to -20dB
0
1
2
dB
dB
dB
dB
%
Et
Total tracking error
AV= -20 to -60dB
0
S/N
SC
d
Signal to noise ratio
Channel separation
Distortion
All Gains = 0dB; VO= 1Vrms
106
100
80
Vin = 1V
0.01 0.08
Bus inputs
VIL
VlN
IlN
Input low voltage
1
5
V
V
Input high voltage
Input current
3
VIN = 0.4V
IO = 1.6mA
-5
μA
Output voltage SDA
acknowledge
VO
0.4
0.8
V
Table 2.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VS
Tamb
Tstg
Operating supply voltage
10.5
V
Operating ambient temperature
Storage temperature range
-40 to 85
-55 to 150
°C
°C
Table 3.
Symbol
Thermal data
Parameter
SO28
Unit
Rth j-amb Thermal Resistance Junction pins
65
°C/W
Table 4.
Symbol
Quick reference data
Parameter
Min. Typ. Max. Unit
VS
VCL
Supply voltage
6
9
10.2
V
Vrms
%
Max. input signal handling
Total harmonic distortion V = 1Vrms f = 1KHz
Signal to noise ratio
2.1
2.6
THD
S/N
0.01 0.08
106
dB
8/20
TDA7348
Electrical characteristics
Min. Typ. Max. Unit
Table 4.
Symbol
Quick reference data (continued)
Parameter
SC
Channel separation f = 1KHz
Volume control
100
dB
dB
-
20
78.45
Treble control 2dB step
Bass control 2dB step
-14
-10
+14
+18
dB
dB
-
Fader and balance control 1.25dB step
0
dB
38.75
11.2
5
Input gain 3.75dB step
Mute attenuation
0
dB
dB
100
9/20
2
I C BUS interface
TDA7348
2
3
I C BUS interface
Data transmission from microprocessor to the TDA7348 and vice-versa takes place through
2
the 2 wires of the I C BUS interface, consisting of the two lines SDA and SCL (pull-up
resistors to the positive supply voltage must be externally connected).
3.1
3.2
Data validity
As shown in Figure 3., the data on the SDA line must be stable during the high period of the
clock. The HIGH and LOW state of the data line can only change when the clock signal on
the SCL line is LOW.
Start and stop conditions
As shown in Figure 4. a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH.
A STOP conditions must be sent before each START condition.
3.3
3.4
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see Figure 5.). The peripheral (audioprocessor) that
acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so
that the SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed has to generate an acknowledge after the
reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case the master transmitter can generate the STOP information in
order to abort the transfer.
3.5
Transmission without acknowledgement
The microprocessor can use a simpler transmission, if it avoids detection of the
acknowledgement from the audio processor. It simply waits one clock pulse without
checking the slave acknowledgment, and sends the new data.
This approach of course is less protected from errors, increases the possibility of
interference, and decreases the immunity to noise.
10/20
2
TDA7348
I C BUS interface
2
Figure 3.
Figure 4.
Figure 5.
Data validity on the I C BUS
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
2
Timing diagram of I C BUS
SCL
SDA
2
I CBUS
D99AU1032
START
STOP
2
Acknowledge on the I C BUS
SCL
1
2
3
7
8
9
SDA
MSB
ACKNOWLEDGMENT
FROM RECEIVER
START
D99AU1033
11/20
Software specification
TDA7348
4
Software specification
4.1
Interface protocol
The interface protocol comprises:
●
●
●
●
●
A start condition (s)
A chip address byte, (the LSB bit determines read/write transmission)
A subaddress byte.
A sequence of data (N-bytes + acknowledge)
A stop condition (P)
Chip address
Subaddress
Data 1 to data n
DATA
MSB
LSB
MSB
X
LSB
X X I A3 A2 A1 A0 ACK
MSB
LSB
S
1
0
0
0
1
0
0 R/W ACK
ACK P
ACK = Acknowledge
S = Start
P = Stop
I = Auto Increment
X = Not used
Max clock speed 500kbits/s
4.2
Auto increment
If bit I in the subaddress byte is set to "1", the auto-increment of the subaddress is enabled
Table 5.
MSB
Subaddress (receive mode)
LSB
Function
X
X
X
I
A3
0
A2
0
A1
0
A0
0
Input selector
0
0
0
1
Loudness
0
0
1
0
Volume
0
0
1
1
Bass, Treble
0
1
0
0
Speaker attenuator LF
Speaker attenuator LR
Speaker attenuator RF
Speaker attenuator RR
Mute
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
12/20
TDA7348
Software specification
4.3
Transmitted data
Table 6.
MSB
Send mode
LSB
X
X
X
X
X
SM
ZM
X
ZM = Zero crossing muted (HIGH active)
SM = Soft mute activated (HIGH active)
X = Not used
The transmitted data is automatically updated after each ACK.
Transmission can be repeated without new chip address.
4.4
Data byte specification
X = not relevant; set to "1" during testing
Table 7.
MSB
Input Selector
LSB
D0
Function
D7
D6
D5
D4
D3
D2
D1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
not used
IN 2
IN 1
AM mono
not used
IN 3
not allowed
not allowed
11.25dB gain
7.5dB gain
3.75dB gain
0dB gain
0
0
1
1
0
1
0
1
For example to select the IN 2 input with a gain of 7.5dB the Data Byte is: X X 1 0 1 0 0 1
Table 8.
MSB
Loudness
LSB
D0
Function
D7
D6
D5
D4
D3
D2
D1
X
X
X
X
X
X
X
X
X
1
1
1
0
0
0
0
0
0
0
0
1
0
1
0
0dB
-1.25dB
-2.5dB
13/20
Software specification
TDA7348
Table 8.
MSB
Loudness (continued)
LSB
D0
Function
D7
D6
D5
D4
D3
D2
D1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
-3.75dB
-5dB
-6.25dB
-7.5dB
-8.75dB
-10dB
-11.25dB
-12.5dB
-13.75dB
-15dB
-16.25dB
-17.5dB
-18.75dB
For example to select -17.5dB attenuation, loudness OFF, the Data Byte is: X X X1 1 1 1 0
Table 9.
MSB
Mute
D5
LSB
D0
Function
D7
D6
D4
D3
D2
D1
1
1
1
Soft mute on
0
1
Soft mute with fast slope (I = IMAX)
Soft mute with slow slope (I = IMIN)
Direct mute
1
0
0
1
0
Zero crossing mute on
Zero crossing mute off
(delayed until next zerocrossing)
Zero crossing mute and pause detector
reset
1
0
0
1
1
0
1
0
1
160mV ZC window threshold (WIN = 00)
80mV ZC window threshold (WIN = 01)
40mV ZC window threshold (WIN = 10)
20mV ZC window threshold (WIN = 11)
Non-symmetrical Bass Cut
0
1
Symmetrical Bass Cut
14/20
TDA7348
Software specification
An additional direct mute function is included in the speaker attenuators.
Note:
Bass cut for very low frequencies should not be used at +16 & +18dB bass boost (DC gain)
Table 10. Speaker attenuators
MSB
D7
LSB
D0
Speaker attenuator LF, LR, RF, RR
D6
D5
D4
D3
D2
D1
1.25dB step
0dB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-1.25dB
-2.5dB
-3.75dB
-5dB
-6.25dB
-7.5dB
-8.75dB
10dB step
0dB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
1
0
1
0
1
1
-10dB
-20dB
-30dB
1
1
1
Speaker mute
For example an attenuation of 25dB on a selected output is given by: X X X1 0 1 0 0
Table 11. Bass/Treble
MSB
D7
LSB
D0
Function
D6
D5
D4
D3
D2
D1
Treble step
-14dB
-12dB
-10dB
-8dB
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
1
0
-6dB
-4dB
-2dB
0dB
0dB
2dB
15/20
Software specification
Table 11. Bass/Treble (continued)
TDA7348
MSB
D7
LSB
D0
Function
D6
D5
D4
D3
D2
D1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
0
1
0
1
0
4dB
6dB
8dB
10dB
12dB
14dB
BASS STEPS
-10dB
-8dB
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
-6dB
-4dB
-2dB
-0dB
-0dB
2dB
4dB
6dB
8dB
10dB
12dB
14dB
146B
18dB
For example 12dB Treble and -8dB Bass give the following DATA BYTE: 0 0 1 1 1 0 0 1
16/20
TDA7348
Software specification
Function
Table 12. Volume
MSB
LSB
D0
D7
D6
D5
D4
D3
D2
D1
0.31dB Fine attenuation steps
0
0
1
1
0
1
0
1
0dB
-0.31dB
-0.62dB
-0.94dB
1.25dB Coarse attenuation steps
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0dB
-1.25dB
-2.5dB
-3.75dB
-5dB
-6.25dB
-7.5dB
-8.75dB
10dB Gain / attenuation steps
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
20dB
10dB
0dB
-10dB
-20dB
-30dB
-40dB
-50dB
For example to select -47.81dB volume the data byte is: 1 1 0 1 1 0 0 1
Power on RESET: All bytes set to 1 1 1 1 1 1 1 0
17/20
Package information
TDA7348
5
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 6.
SO-28 mechanical, data and package dimensions
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN. TYP. MAX.
A
a1
b
2.65
0.3
0.104
0.012
0.019
0.013
0.1
0.004
0.35
0.23
0.49 0.014
0.32 0.009
b1
C
0.5
0.020
c1
D
45° (typ.)
17.7
10
18.1 0.697
10.65 0.394
0.713
0.419
E
e
1.27
0.050
0.65
e3
F
16.51
7.4
0.4
7.6
0.291
0.299
0.050
L
1.27 0.016
SO-28
S
8 ° (max.)
18/20
TDA7348
Revision history
6
Revision history
Table 13. Document revision history
Date
Revision
Changes
14-Jan-2004
21-Jun-2004
26-Jan-2007
1
2
3
Initial release.
Technical migration from ST-PRESS to EDOCS DMS
DIP28 package removed, block diagram changed, layout modified.
19/20
TDA7348
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