STS8DNF3LL_07 [STMICROELECTRONICS]

Dual N-channel 30V - 0.017OHM - 8A SO-8 Low gate charge STripFET TM II Power MOSFET; 双N沟道30V - 0.017OHM - 8A SO- 8低栅极电荷的STripFET TM II功率MOSFET
STS8DNF3LL_07
型号: STS8DNF3LL_07
厂家: ST    ST
描述:

Dual N-channel 30V - 0.017OHM - 8A SO-8 Low gate charge STripFET TM II Power MOSFET
双N沟道30V - 0.017OHM - 8A SO- 8低栅极电荷的STripFET TM II功率MOSFET

栅极
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中文:  中文翻译
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STS8DNF3LL  
Dual N-channel 30V - 0.017- 8A SO-8  
Low gate charge STripFET™ II Power MOSFET  
General features  
Type  
VDSS  
RDS(on)  
ID  
STS8DNF3LL  
30V  
<0.020Ω  
8A  
Optimal R (on) x Qg trade-off @ 4.5V  
DS  
Conduction losses reduced  
Switching losses reduced  
S0-8  
Description  
This application specific Power MOSFET is the  
second generation of STMicroelectronics unique  
"Single Feature Size™" strip-based process. The  
resulting transistor shows the best trade-off  
between on-resistance and gate charge. When  
used as high and low side in buck regulators, it  
gives the best performance in terms of both  
conduction and switching losses. This is  
extremely important for motherboards where fast  
switching and high efficiency are of paramount  
importance.  
Internal schematic diagram  
Applications  
Switching application  
Order codes  
Part number  
Marking  
Package  
Packaging  
STS8DNF3LL  
S8DNF3LL  
SO-8  
Tape & reel  
January 2007  
Rev 10  
1/12  
www.st.com  
12  
Contents  
STS8DNF3LL  
Contents  
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
2.1  
Electrical characteristics (curves)  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
3
4
5
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
2/12  
STS8DNF3LL  
Electrical ratings  
1
Electrical ratings  
Table 1.  
Symbol  
Absolute maximum ratings  
Parameter  
Value  
Unit  
VDS  
VGS  
Drain-source voltage (vgs = 0)  
Gate- source voltage  
30  
16  
V
V
Drain current (continuos) at TC = 25°C  
single operating  
ID  
8
A
Drain current (continuos) at TC = 100°C  
single operating  
ID  
5
A
A
(1)  
IDM  
Drain current (pulsed)  
32  
Total dissipation at TC = 25°C dual operating  
Total dissipation at TC = 25°C single operating  
2
W
W
PTOT  
1.6  
1. Pulse width limited by safe operating area  
Table 2.  
Thermal data  
(1)Thermal resistance junction-ambient single  
78  
°C/W  
operating  
Rthj-a  
62.5  
°C/W  
Thermal resistance junction-ambient dual operating  
Thermal operating junction-ambient  
TJ  
150  
°C  
°C  
Tstg Storage temperature  
-55 to 150  
1. Mounted on FR-4 board with 0.5 in2 pad of Cu.  
3/12  
Electrical characteristics  
STS8DNF3LL  
2
Electrical characteristics  
(T  
=25°C unless otherwise specified)  
CASE  
Table 3.  
Symbol  
On/off states  
Parameter  
Test conditions  
Min.  
Typ.  
Max. Unit  
Drain-source  
V(BR)DSS  
ID = 250 µA, VGS = 0  
VDS = Max rating  
30  
V
Breakdown voltage  
1
µA  
µA  
Zero gate voltage  
IDSS  
VDS=Max rating,  
TC=125°C  
Drain current (VGS = 0)  
10  
Gate-body leakage  
current (VDS = 0)  
IGSS  
VGS  
=
16V  
100  
nA  
V
VGS(th) Gate threshold voltage  
VDS = VGS, ID = 250µA  
VGS = 10V, ID = 4A  
1
0.017  
0.020  
Static drain-source on  
resistance  
0.020  
0.024  
RDS(on)  
VGS = 4.5V, ID = 4A  
Table 4.  
Symbol  
Dynamic  
Parameter  
Test conditions  
Min.  
Typ. Max. Unit  
(1)  
gfs  
Forward transconductance  
Input capacitance  
VDS = 15V, ID= 4 A  
12.5  
800  
250  
S
Ciss  
pF  
pF  
VDS = 25V, f = 1 MHz,  
Coss  
Output capacitance  
VGS = 0  
Reverse transfer  
capacitance  
Crss  
60  
pF  
Qg  
Qgs  
Qgd  
Total gate charge  
Gate-source charge  
Gate-drain charge  
12.5  
3.2  
17  
nC  
nC  
nC  
VDD = 15V, ID = 8A,  
VGS = 5V  
(see Figure 14)  
4.5  
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5.  
Table 5.  
Symbol  
Switching times  
Parameter  
Test conditions  
Min. Typ. Max. Unit  
VDD=15 V, ID=4A,  
RG=4.7, VGS= 4.5V  
(see Figure 13)  
td(on)  
tr  
Turn-on delay time  
Rise time  
18  
32  
ns  
ns  
VDD=15 V, ID=4A,  
RG=4.7, VGS= 4.5V  
(see Figure 13)  
21  
11  
ns  
ns  
td(off)  
tf  
Turn-off Delay Time  
Fall Time  
4/12  
STS8DNF3LL  
Electrical characteristics  
Min. Typ. Max Unit  
Table 6.  
Source drain diode  
Parameter  
Symbol  
Test conditions  
ISD  
Source-drain current  
8
A
A
V
(1)  
ISDM  
Source-drain current (pulsed)  
Forward on voltage  
32  
1.2  
(2)  
VSD  
ISD = 8A, VGS = 0  
ISD = 8A, VDD = 15V  
di/dt = 100A/µs,  
Tj = 150°C  
trr  
Reverse recovery time  
Reverse recovery charge  
Reverse recovery current  
23  
17  
ns  
nC  
A
Qrr  
IRRM  
1.5  
(see Figure 15)  
1. Pulse width limited by safe operating area.  
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%  
5/12  
Electrical characteristics  
STS8DNF3LL  
2.1  
Electrical characteristics (curves)  
Figure 1. Safe operating area  
Figure 2. Thermal impedance  
Figure 3. Output characteristics  
Figure 4. Transfer characteristics  
Figure 5. Transconductance  
Figure 6. Static drain-source on resistance  
6/12  
 
STS8DNF3LL  
Electrical characteristics  
Figure 7. Gate charge vs. gate-source voltage Figure 8. Capacitance variations  
Figure 9. Normalized gate threshold voltage Figure 10. Normalized on resistance vs.  
vs. temperature  
temperature  
Figure 11. Source-drain diode forward  
characteristics  
Figure 12. Normalized breakdown voltage vs.  
temperature  
7/12  
Test circuit  
STS8DNF3LL  
3
Test circuit  
Figure 13. Switching times test circuit for  
resistive load  
Figure 14. Gate charge test circuit  
Figure 15. Test circuit for inductive load  
switching and diode recovery times  
Figure 16. Unclamped Inductive load test  
circuit  
Figure 17. Unclamped inductive waveform  
Figure 18. Switching time waveform  
8/12  
 
STS8DNF3LL  
Package mechanical data  
4
Package mechanical data  
In order to meet environmental requirements, ST offers these devices in ECOPACK®  
packages. These packages have a Lead-free second level interconnect. The category of  
second level interconnect is marked on the package and on the inner box label, in  
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering  
conditions are also marked on the inner box label. ECOPACK is an ST trademark.  
ECOPACK specifications are available at : www.st.com  
9/12  
 
Package mechanical data  
STS8DNF3LL  
SO-8 MECHANICAL DATA  
mm.  
inch  
TYP.  
DIM.  
MIN.  
TYP  
MAX.  
1.75  
0.25  
1.65  
0.85  
0.48  
0.25  
0.5  
MIN.  
MAX.  
0.068  
0.009  
0.064  
0.033  
0.018  
0.010  
0.019  
A
a1  
a2  
a3  
b
0.1  
0.003  
0.65  
0.35  
0.19  
0.25  
0.025  
0.013  
0.007  
0.010  
b1  
C
c1  
D
45 (typ.)  
4.8  
5.8  
5.0  
6.2  
0.188  
0.228  
0.196  
0.244  
E
1.27  
3.81  
e
0.050  
0.150  
e3  
F
3.8  
0.4  
4.0  
1.27  
0.6  
0.14  
0.157  
0.050  
0.023  
L
0.015  
M
S
8 (max.)  
10/12  
STS8DNF3LL  
Revision history  
5
Revision history  
Table 7.  
Date  
Revision history  
Revision  
Changes  
11-Sep-2006  
15-Nov-2006  
30-Jan-2007  
8
9
Complete document  
The document has been reformatted  
10  
Typo mistake on Table 1.  
11/12  
 
STS8DNF3LL  
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12/12  

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