STS8DNH3LL_08 [STMICROELECTRONICS]
Dual n-channel 30 V - 0.018 Ω - 8 A - SO-8 low gate charge STripFET™ III Power MOSFET; 双N沟道30 V - 0.018 Ω - 8 A - SO - 8低栅极电荷的STripFET ™III功率MOSFET
| 型号： | STS8DNH3LL_08 |
| 厂家： | 
ST |
| 描述： | Dual n-channel 30 V - 0.018 Ω - 8 A - SO-8 low gate charge STripFET™ III Power MOSFET |
| 文件： | 总12页 (文件大小：315K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STS8DNH3LL
Dual n-channel 30 V - 0.018 Ω - 8 A - SO-8
low gate charge STripFET™ III Power MOSFET
Features
Type
VDSS
RDS(on) max
ID
STS8DNH3LL
30 V
< 0.022 Ω
8 A
■ Optimal R
x Qg trade-off @ 4.5 V
DS(on)
■ Conduction losses reduced
■ Switching losses reduced
S0-8
Application
■ Switching applications
Description
Figure 1.
Internal schematic diagram
This product utilizes the latest advanced design
rules of ST’s proprietary STripFET™ technology
which is suitable for the most demanding DC-DC
converter applications where high efficiency is
required.
Table 1.
Device summary
Order code
STS8DNH3LL
Marking
Package
SO-8
Packaging
8DH3LL
Tape & reel
June 2008
Rev 2
1/12
www.st.com
12
Contents
STS8DNH3LL
Contents
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
. . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
4
5
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/12
STS8DNH3LL
Electrical ratings
1
Electrical ratings
Table 2.
Symbol
Absolute maximum ratings
Parameter
Value
30
16
Unit
VDS
VGS
ID
Drain-source voltage (vGS = 0)
Gate- source voltage
V
V
Drain current (continuous) at TC = 25°C
Drain current (continuous) at TC = 100°C
Drain current (pulsed)
8
5
A
ID
A
(1)
IDM
32
2
A
PTOT
Total dissipation at TC = 25°C
Single pulse avalanche energy
W
mJ
(2)
EAS
100
1. Pulse width limited by safe operating area
2. Starting TJ = 25 °C, ID = 6 A
Table 3.
Symbol
Thermal data
Parameter
Value
Unit
(1)
Rthj-a
Thermal resistance junction-ambient max
Thermal operating junction-ambient
Storage temperature
62.5
150
°C/W
°C
TJ
Tstg
-55 to 150
°C
1. When mounted on 1 inch² FR-4 board, 2 oz. Cu., t ≤ 10s
3/12
Electrical characteristics
STS8DNH3LL
2
Electrical characteristics
(T
=25°C unless otherwise specified)
CASE
Table 4.
Symbol
On/off states
Parameter
Test conditions
Min.
Typ.
Max. Unit
Drain-source
V(BR)DSS
ID = 250 µA, VGS = 0
30
V
Breakdown voltage
Zero gate voltage
IDSS
V
DS = Max rating
1
µA
µA
nA
Drain current (VGS = 0)
Zero gate voltage
IDSS
VDS =Max rating @125°C
10
100
Drain current (VGS = 0)
Gate-body leakage
current (VDS = 0)
IGSS
VGS
=
16 V
VGS(th) Gate threshold voltage VDS = VGS,ID = 250 µA
1
V
VGS = 10 V, ID = 4 A
Static drain-source on
0.018 0.022
0.020 0.025
Ω
Ω
RDS(on)
resistance
VGS = 4.5 V, ID = 4 A
Table 5.
Symbol
Dynamic
Parameter
Test conditions
Min.
Typ.
Max. Unit
Forward
transconductance
gfs
VDS = 15 V, ID = 4 A
8.5
S
Ciss
Input capacitance
Output capacitance
857
147
pF
pF
VDS = 25 V, f = 1 MHz,
Coss
VGS = 0
Reverse transfer
capacitance
Crss
20
pF
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
7
10
nC
nC
nC
VDD = 15 V, ID = 8 A,
VGS = 4.5 V
2.5
2.3
(see Figure 14)
4/12
STS8DNH3LL
Electrical characteristics
Table 6.
Switching times
Parameter
Symbol
Test conditions
Min.
Typ. Max. Unit
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
VDD=15 V, ID=4 A, RG=4.7 Ω,
VGS= 4.5 V (see Figure 16)
12
ns
ns
14.5
VDD=15 V, ID=4 A, RG=4.7 Ω,
VGS= 4.5 V (see Figure 16)
23
8
ns
ns
Turn-off delay time
Fall time
Table 7.
Symbol
Source drain diode
Parameter
Test conditions
Min
Typ. Max Unit
VDD=15 V, ID=4 A, RG=4.7 Ω,
VGS= 4.5 V
ISD
Source-drain current
8
A
VDD=15 V, ID= 4A
Source-drain current
(pulsed)
(1)
ISDM
32
A
V
RG=4.7 Ω, VGS=4.5 V
(2)
VSD
Forward on voltage
ISD = 8 A, VGS = 0
1.5
ISD = 8 A,VDD = 15 V
di/dt = 100 A/µs,
Tj = 150°C
trr
Reverse recovery time
Reverse recovery charge
Reverse recovery current
15
5.7
ns
nC
A
Qrr
IRRM
0.76
(see Figure 15)
1. Pulse width limited by safe operating area.
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
5/12
Electrical characteristics
STS8DNH3LL
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
Figure 5.
Figure 7.
Thermal resistance
Figure 4.
Figure 6.
6/12
Output characteristics
Transfer characteristics
Static drain-source on resistance
Normalized BV
vs temperature
DSS
STS8DNH3LL
Figure 8.
Electrical characteristics
Gate charge vs gate-source voltage Figure 9.
for Q1
Capacitance variations
Figure 10. Normalized gate threshold voltage Figure 11. Normalized on resistance vs
vs temperature for Q1
temperature
Figure 12. Source-drain diode forward
characteristics
7/12
Test circuit
STS8DNH3LL
3
Test circuit
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
Figure 15. Test circuit for inductive load
switching and diode recovery times
Figure 16. Unclamped Inductive load test
circuit
Figure 17. Unclamped inductive waveform
Figure 18. Switching time waveform
8/12
STS8DNH3LL
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
9/12
Package mechanical data
STS8DNH3LL
SO-8 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.75
0.25
1.65
0.85
0.48
0.25
0.5
MIN.
MAX.
0.068
0.009
0.064
0.033
0.018
0.010
0.019
A
a1
a2
a3
b
0.1
0.003
0.65
0.35
0.19
0.25
0.025
0.013
0.007
0.010
b1
C
c1
D
45 (typ.)
4.8
5.8
5.0
6.2
0.188
0.228
0.196
0.244
E
1.27
3.81
e
0.050
0.150
e3
F
3.8
0.4
4.0
1.27
0.6
0.14
0.157
0.050
0.023
L
0.015
M
S
8 (max.)
10/12
STS8DNH3LL
Revision history
5
Revision history
Table 8.
Date
Document revision history
Revision
Changes
15-Jun-2004
16-Jun-2008
1
2
First release
Modified marking
11/12
STS8DNH3LL
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