EVAL6208N [STMICROELECTRONICS]
DMOS DRIVER FOR BIPOLAR STEPPER MOTOR; DMOS驱动程序双极步进电机
| 型号： | EVAL6208N |
| 厂家： | 
ST |
| 描述： | DMOS DRIVER FOR BIPOLAR STEPPER MOTOR |
| 文件： | 总27页 (文件大小：469K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6208
DMOS DRIVER FOR BIPOLAR STEPPER MOTOR
■
OPERATING SUPPLY VOLTAGE FROM 8 TO 52V
■ 5.6A OUTPUT PEAK CURRENT (2.8A RMS)
0.3Ω TYP. VALUE @ T = 25°C
■ R
DS(ON)
j
■ OPERATING FREQUENCY UP TO 100KHz
■ NON DISSIPATIVE OVERCURRENT
PROTECTION
SO24
(20+2+2)
PowerSO36
PowerDIP24
(20+2+2)
■ DUAL INDEPENDENT CONSTANT t
PWM
OFF
CURRENT CONTROLLERS
ORDERING NUMBERS:
L6208N (PowerDIP24)
L6208PD (PowerSO36)
L6208D (SO24)
■ FAST/SLOW DECAY MODE SELECTION
■ FAST DECAY QUASI-SYNCHRONOUS
RECTIFICATION
■ DECODING LOGIC FOR STEPPER MOTOR
FULL AND HALF STEP DRIVE
■ CROSS CONDUCTION PROTECTION
■ THERMAL SHUTDOWN
■ UNDER VOLTAGE LOCKOUT
bines isolated DMOS Power Transistors with CMOS
and bipolar circuits on the same chip. The device in-
cludes all the circuitry needed to drive a two-phase
bipolar stepper motor including: a dual DMOS Full
Bridge, the constant off time PWM Current Controller
that performs the chopping regulation and the Phase
Sequence Generator, that generates the stepping
sequence. Available in PowerDIP24 (20+2+2),
PowerSO36 and SO24 (20+2+2) packages, the
L6208 features a non-dissipative overcurrent protec-
tion on the high side Power MOSFETs and thermal
shutdown.
■
INTEGRATED FAST FREE WHEELING DIODES
TYPICAL APPLICATIONS
■ BIPOLAR STEPPER MOTOR
DESCRIPTION
The L6208 is a DMOS Fully Integrated Stepper Motor
Driver with non-dissipative Overcurrent Protection,
realized in MultiPower-BCD technology, which com-
BLOCK DIAGRAM
VBOOT
VCP
VBOOT
VSA
VBOOT
VBOOT
CHARGE
PUMP
OCDA
OCDB
OVER
CURRENT
DETECTION
OUT1A
OUT2A
10V
10V
THERMAL
PROTECTION
EN
GATE
LOGIC
CONTROL
SENSEA
HALF/FULL
CLOCK
PWM
+
-
STEPPING
SEQUENCE
GENERATION
ONE SHOT
MONOSTABLE
MASKING
TIME
VREFA
RCA
RESET
SENSE
COMPARATOR
CW/CCW
BRIDGE A
VSB
OVER
OUT1B
OUT2B
SENSEB
VREFB
RCB
CURRENT
DETECTION
VOLTAGE
REGULATOR
GATE
LOGIC
10V
5V
BRIDGE B
D01IN1225
September 2003
1/27
L6208
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Supply Voltage
Test conditions
Value
60
Unit
V
V
S
V
=
=
V
V
= V
S
SA
SB
V
OD
Differential Voltage between
V
V
= V = 60V;
60
V
SA
SB
S
VS , OUT1 , OUT2 , SENSE and
= V
= GND
A
A
A
A
SENSEA
SENSEB
VS , OUT1 , OUT2 , SENSE
B
B
B
B
V
Bootstrap Peak Voltage
Input and Enable Voltage Range
Voltage Range at pins V
V
SA
=
V
SB
= V
V + 10
V
V
V
BOOT
S
S
V ,V
IN EN
-0.3 to +7
-0.3 to +7
V
REFA
,
REFA
V
and V
REFB
REFB
V
V
Voltage Range at pins RC and
-0.3 to +7
-1 to +4
7.1
V
V
A
RCA, RCB
A
RC
B
V
V
Voltage Range at pins SENSE
A
and SENSE
B
SENSEA,
SENSEB
I
Pulsed Supply Current (for each
V pin), internally limited by the
S
V
t
=
V
= V ;
S(peak)
SA
SB S
< 1ms
PULSE
overcurrent protection
I
RMS Supply Current (for each
V
SA
=
V
SB
= V
S
2.8
A
S
V pin)
S
T
, T
stg OP
Storage and Operating
Temperature Range
-40 to 150
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Supply Voltage
Test Conditions
MIN
MAX
Unit
V
V
S
V
=
=
V
V
= V
S
8
52
52
SA
SB
V
OD
Differential Voltage Between
V
V
= V ;
V
SA
SB
S
VS , OUT1 , OUT2 , SENSE and
= V
A
A
A
A
SENSEA
SENSEB
VS , OUT1 , OUT2 , SENSE
B
B
B
B
V
,
Voltage Range at pins V
-0.1
5
V
REFA
REFA
V
and V
REFB
REFB
V
V
Voltage Range at pins SENSE
(pulsed t < t )
(DC)
-6
-1
6
1
V
V
SENSEA,
A
W
rr
and SENSE
SENSEB
B
I
RMS Output Current
2.8
+125
100
A
OUT
T
Operating Junction Temperature
Switching Frequency
-25
°C
j
f
KHz
sw
2/27
L6208
THERMAL DATA
Symbol
Description
PowerDIP24
SO24
14
PowerSO36
Unit
°C/W
°C/W
°C/W
R
Maximum Thermal Resistance Junction-Pins
Maximum Thermal Resistance Junction-Case
18
-
-
1
-
th-j-pins
th-j-case
th-j-amb1
R
-
(1)
(2)
(3)
(4)
R
R
R
R
43
51
Maximum Thermal Resistance Junction-Ambient
Maximum Thermal Resistance Junction-Ambient
Maximum Thermal Resistance Junction-Ambient
Maximum Thermal Resistance Junction-Ambient
-
-
-
-
35
15
62
°C/W
°C/W
°C/W
th-j-amb1
th-j-amb1
th-j-amb2
58
77
2
(1)
(2)
(3)
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6cm (with a thickness of 35µm).
2
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm (with a thickness of 35µm).
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm (with a thickness of 35µm), 16 via holes
2
and a ground layer.
(4)
Mounted on a multi-layer FR4 PCB without any heat sinking surface on the board.
PIN CONNECTIONS (Top View)
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
GND
N.C.
GND
2
N.C.
CLOCK
CW/CCW
SENSEA
RCA
1
24
23
22
21
20
19
18
17
16
15
14
13
VREFA
RESET
VCP
3
N.C.
N.C.
2
4
VSA
VSB
3
5
OUT2A
N.C.
OUT2B
N.C.
4
OUT2A
VSA
6
OUT1A
GND
5
7
VCP
VBOOT
EN
8
RESET
VREFA
CLOCK
CW/CCW
SENSEA
RCA
6
GND
9
CONTROL
HALF/FULL
VREFB
SENSEB
RCB
GND
7
GND
10
11
12
13
14
15
16
17
18
OUT1B
RCB
8
VSB
9
OUT2B
VBOOT
EN
SENSEB
VREFB
HALF/FULL
10
11
12
N.C.
N.C.
CONTROL
OUT1A
N.C.
OUT1B
N.C.
D99IN1083
N.C.
N.C.
GND
GND
D99IN1084
PowerDIP24/SO24
(5)
PowerSO36
(5)
The slug is internally connected to pins 1,18,19 and 36 (GND pins).
3/27
L6208
PIN DESCRIPTION
PACKAGE
SO24/
PowerDIP24
PowerSO36
Name
Type
Function
PIN #
PIN #
1
10
CLOCK
Logic Input
Logic Input
Step Clock input. The state machine makes one step on
each rising edge.
2
11
CW/CCW
Selects the direction of the rotation. HIGH logic level sets
clockwise direction, whereas LOW logic level sets
counterclockwise direction.
If not used, it has to be connected to GND or +5V.
3
4
12
13
SENSE
Power Supply Bridge A Source Pin. This pin must be connected to Power
Ground through a sensing power resistor.
A
RC
RC Pin
RC Network Pin. A parallel RC network connected
between this pin and ground sets the Current Controller
OFF-Time of the Bridge A.
A
5
15
OUT1
Power Output Bridge A Output 1.
A
6, 7,
1, 18,
GND
GND Ground terminals. In PowerDIP24 and SO24 packages,
18, 19
19, 36
these pins are also used for heat dissipation toward the
PCB. On PowerSO36 package the slug is connected to
these pins.
8
9
22
24
OUT1
Power Output Bridge B Output 1.
B
RC
RC Pin RC Network Pin. A parallel RC network connected
B
between this pin and ground sets the Current Controller
OFF-Time of the Bridge B.
10
11
12
25
26
27
SENSE
Power Supply Bridge B Source Pin. This pin must be connected to Power
Ground through a sensing power resistor.
B
VREF
Analog Input Bridge B Current Controller Reference Voltage.
Do not leave this pin open or connected to GND.
B
HALF/FULL
CONTROL
EN
Logic Input
Step Mode Selector. HIGH logic level sets HALF STEP
Mode, LOW logic level sets FULL STEP Mode.
If not used, it has to be connected to GND or +5V.
13
14
28
29
Logic Input
Decay Mode Selector. HIGH logic level sets SLOW DECAY
Mode. LOW logic level sets FAST DECAY Mode.
If not used, it has to be connected to GND or +5V.
(6)
Chip Enable. LOW logic level switches OFF all Power
MOSFETs of both Bridge A and Bridge B. This pin is also
connected to the collector of the Overcurrent and Thermal
Protection to implement over current protection.
If not used, it has to be connected to +5V through a
resistor.
Logic Input
15
30
VBOOT
Supply
Voltage
Bootstrap Voltage needed for driving the upper Power
MOSFETs of both Bridge A and Bridge B.
16
17
32
33
OUT2
Power Output Bridge B Output 2.
B
VS
Power Supply Bridge B Power Supply Voltage. It must be connected to
B
the Supply Voltage together with pin VS
A
20
4
VS
Power Supply Bridge A Power Supply Voltage. It must be connected to
the Supply Voltage together with pin VS
A
B
4/27
L6208
PIN DESCRIPTION (continued)
PACKAGE
SO24/
PowerDIP24
PowerSO36
Name
Type
Function
PIN #
21
PIN #
5
7
8
OUT2
VCP
Power Output Bridge A Output 2.
A
22
Output
Charge Pump Oscillator Output.
23
RESET
Logic Input
Reset Pin. LOW logic level restores the Home State
(State 1) on the Phase Sequence Generator State
Machine.
If not used, it has to be connected to +5V.
24
9
VREF
Analog Input Bridge A Current Controller Reference Voltage.
Do not leave this pin open or connected to GND.
A
(6)
Also connected at the output drain of the Over current and Thermal protection MOSFET. Therefore, it has to be driven putting in series
a resistor with a value in the range of 2.2KΩ - 180KΩ, recommended 100KΩ.
ELECTRICAL CHARACTERISTICS
(T = 25°C, V = 48V, unless otherwise specified)
amb
Symbol
s
Parameter
Turn-on Threshold
Test Conditions
Min
6.6
5.6
Typ
7
Max
7.4
6.4
10
Unit
V
V
Sth(ON)
V
Turn-off Threshold
6
V
Sth(OFF)
I
S
Quiescent Supply Current
All Bridges OFF;
T = -25°C to 125°C
5
mA
(7)
j
T
Thermal Shutdown Temperature
165
°C
j(OFF)
Output DMOS Transistors
High-Side Switch ON Resistance T = 25 °C
R
DS(ON)
0.34
0.53
0.4
Ω
Ω
j
(7)
(7)
0.59
T =125 °C
j
Low-Side Switch ON Resistance T = 25 °C
0.28
0.47
0.34
0.53
Ω
Ω
j
T =125 °C
j
I
Leakage Current
EN = Low; OUT = V
2
mA
mA
DSS
S
EN = Low; OUT = GND
-0.15
Source Drain Diodes
V
Forward ON Voltage
I
= 2.8A, EN = LOW
1.15
300
200
1.3
V
SD
SD
t
Reverse Recovery Time
Forward Recovery Time
I = 2.8A
f
ns
ns
rr
t
fr
Logic Inputs (EN, CONTROL, HALF/FULL, CLOCK, RESET, CW/CCW)
V
Low level logic input voltage
High level logic input voltage
-0.3
2
0.8
7
V
V
IL
V
IH
5/27
L6208
ELECTRICAL CHARACTERISTICS (continued)
(T
amb
= 25°C, V = 48V, unless otherwise specified)
s
Symbol
Parameter
Test Conditions
GND Logic Input Voltage
7V Logic Input Voltage
Min
Typ
Max
Unit
µA
µA
V
I
IL
Low Level Logic Input Current
High Level Logic Input Current
Turn-on Input Threshold
Turn-off Input Threshold
Input Threshold Hysteresis
-10
I
IH
10
V
th(ON)
1.8
1.3
0.5
2.0
V
V
0.8
V
th(OFF)
th(HYS)
0.25
V
Switching Characteristics
t
Enable to Output Turn-on Delay
I
I
=2.8A, Resistive Load
=2.8A, Resistive Load
100
300
250
550
400
800
ns
ns
D(ON)EN
LOAD
(8)
Time
t
Enable to Output Turn-off Delay
D(OFF)EN
LOAD
(8)
Time
(8)
t
t
I
I
I
=2.8A, Resistive Load
=2.8A, Resistive Load
=2.8A, Resistive Load
40
40
250
250
ns
ns
µs
µs
µs
RISE
FALL
LOAD
LOAD
LOAD
Output Rise Time
(8)
Output Fall Time
(9)
t
2
DCLK
Clock to Output Delay Time
(10)
t
1
1
CLK(min)L
Minimum Clock Time
(10)
t
CLK(min)
H
Minimum Clock Time
f
Clock Frequency
100
1
KHz
µs
CLK
(11)
t
S(MIN)
H(MIN)
R(MIN)
Minimum Set-up Time
(11)
t
t
1
1
1
µs
µs
µs
Minimum Hold Time
(11)
Minimum Reset Time
t
Minimum Reset to Clock Delay
RCLK(MIN
)
(11)
Time
t
f
Dead Time Protection
0.5
3.5
1
µs
DT
CP
(7)
0.6
1
MHz
Charge Pump Frequency
T = -25°C to 125°C
j
PWM Comparator and Monostable
Source Current at pins RC and
I
I
V
V
= V
RCB
= 2.5V
= 0.5V
5.5
±5
mA
mV
RCA, RCB
A
RCA
RC
B
V
offset
Offset Voltage on Sense
Comparator
V
REFA, REFB
(12)
t
500
1
ns
µs
PROP
Turn OFF Propagation Delay
t
Internal Blanking Time on
SENSE pins
BLANK
t
Minimum On Time
1.5
2
µs
ON(MIN)
6/27
L6208
ELECTRICAL CHARACTERISTICS (continued)
(T = 25°C, V = 48V, unless otherwise specified)
amb
Symbol
s
Parameter
Test Conditions
= 20KΩ; C = 1nF
Min
Typ
13
Max
Unit
µs
t
PWM Recirculation Time
R
R
OFF
OFF
OFF
= 100KΩ; C
= 1nF
61
µs
OFF
OFF
I
Input Bias Current at pins VREF
10
µA
BIAS
A
and VREF
B
Over Current Protection
(7)
I
Input Supply Overcurrent
Protection Threshold
4
5.6
7.1
60
A
SOVER
T = -25°C to 125°C
j
R
Open Drain ON Resistance
OCD Turn-on Delay Time (13)
OCD Turn-off Delay Time (13)
I = 4mA
40
Ω
OPDR
t
I = 4mA; C < 100pF
200
100
ns
ns
OCD(ON)
EN
t
I = 4mA; C < 100pF
EN
OCD(OFF)
(7)
(8)
(9)
Tested at 25°C in a restricted range and guaranteed by characterization.
See Fig. 1.
See Fig. 2.
(10) See Fig. 3.
(11) See Fig. 4.
(12) Measured applying a voltage of 1V to pin SENSE and a voltage drop from 2V to 0V to pin VREF.
(13) See Fig. 5.
Figure 1. Switching Characteristic Definition
EN
V
th(ON)
V
th(OFF)
t
I
OUT
90%
10%
t
D01IN1316
t
t
RISE
FALL
t
t
D(ON)EN
D(OFF)EN
7/27
L6208
Figure 2. Clock to Output Delay Time
CLOCK
Vth(ON)
t
IOUT
t
D01IN1317
tDCLK
Figure 3. Minimum Timing Definition; Clock Input
CLOCK
Vth(ON)
Vth(OFF)
Vth(OFF)
tCLK(MIN)L
tCLK(MIN)H
D01IN1318
Figure 4. Minimum Timing Definition; Logic Inputs
CLOCK
V
th(ON)
LOGIC INPUTS
t
t
H(MIN)
S(MIN)
RESET
V
th(ON)
V
th(OFF)
D01IN1319
t
t
RCLK(MIN)
R(MIN)
8/27
L6208
Figure 5. Overcurrent Detection Timing Definition
IOUT
ISOVER
ON
BRIDGE
OFF
VEN
90%
10%
D02IN1399
tOCD(ON)
tOCD(OFF)
CIRCUIT DESCRIPTION
POWER STAGES and CHARGE PUMP
The L6208 integrates two independent Power MOS Full Bridges. Each Power MOS has an RDS(ON) = 0.3
Ω (typ-
ical value @ 25°C), with intrinsic fast freewheeling diode. Switching patterns are generated by the PWM Current
Controller and the Phase Sequence Generator (see below). Cross conduction protection is achieved using a
dead time (tDT = 1
a bridge.
µs typical value) between the switch off and switch on of two Power MOSFETSs in one leg of
Pins VS and VS MUST be connected together to the supply voltage V . The device operates with a supply
A
B
S
voltage in the range from 8V to 52V. It has to be noticed that the RDS(ON) increases of some percents when the
supply voltage is in the range from 8V to 12V (see Fig. 34 and 35).
Using N-Channel Power MOS for the upper transistors in the bridge requires a gate drive voltage above the
power supply voltage. The bootstrapped supply voltage VBOOT is obtained through an internal Oscillator and few
external components to realize a charge pump circuit as shown in Figure 6. The oscillator output (VCP) is a
square wave at 600KHz (typical) with 10V amplitude. Recommended values/part numbers for the charge pump
circuit are shown in Table 1.
Table 1. Charge Pump External Components Values
C
C
R
220nF
10nF
BOOT
P
P
100Ω
D1
D2
1N4148
1N4148
9/27
L6208
Figure 6. Charge Pump Circuit
VS
D1
D2
CBOOT
RP
CP
D01IN1328
VCP
VBOOT
VSA VSB
LOGIC INPUTS
Pins CONTROL, HALF/FULL, CLOCK, RESET and CW/CCW are TTL/CMOS and uC compatible logic inputs.
The internal structure is shown in Fig. 7. Typical value for turn-on and turn-off thresholds are respectively
Vth(ON)= 1.8V and Vth(OFF)= 1.3V.
Pin EN (Enable) has identical input structure with the exception that the drain of the Overcurrent and thermal
protection MOSFET is also connected to this pin. Due to this connection some care needs to be taken in driving
this pin. The EN input may be driven in one of two configurations as shown in Fig. 8 or 9. If driven by an open
drain (collector) structure, a pull-up resistor R and a capacitor C are connected as shown in Fig. 8. If the
EN
EN
driver is a standard Push-Pull structure the resistor REN and the capacitor CEN are connected as shown in Fig.
9. The resistor REN should be chosen in the range from 2.2K to 180K . Recommended values for REN and
EN are respectively 100K and 5.6nF. More information on selecting the values is found in the Overcurrent
Protection section.
Ω
Ω
C
Ω
Figure 7. Logic Inputs Internal Structure
5V
ESD
PROTECTION
D01IN1329
Figure 8. EN Pin Open Collector Driving
5V
5V
REN
EN
OPEN
COLLECTOR
OUTPUT
CEN
ESD
PROTECTION
D01IN1330
Figure 9. EN Pin Push-Pull Driving
5V
REN
EN
PUSH-PULL
OUTPUT
CEN
ESD
PROTECTION
D01IN1331
10/27
L6208
PWM CURRENT CONTROL
The L6208 includes a constant off time PWM current controller for each of the two bridges. The current control
circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected be-
tween the source of the two lower power MOS transistors and ground, as shown in Figure 10. As the current in
the motor builds up the voltage across the sense resistor increases proportionally. When the voltage drop
across the sense resistor becomes greater than the voltage at the reference input (VREFA or VREFB) the sense
comparator triggers the monostable switching the bridge off. The power MOS remain off for the time set by the
monostable and the motor current recirculates as defined by the selected decay mode, described in the next
section. When the monostable times out the bridge will again turn on. Since the internal dead time, used to pre-
vent cross conduction in the bridge, delays the turn on of the power MOS, the effective off time is the sum of the
monostable time plus the dead time.
Figure 10. PWM Current Controller Simplified Schematic
VSA (or B
)
TO GATE LOGIC
BLANKING TIME
MONOSTABLE
1µs
FROM THE
LOW-SIDE
GATE DRIVERS
5mA
2H
1H
MONOSTABLE
SET
2 PHASE
STEPPER MOTOR
S
R
BLANKER
I
OUT
Q
(0)
(1)
OUT2
A(or B)
DRIVERS
DRIVERS
+
+
-
DEAD TIME
DEAD TIME
+
5V
OUT1
A(or B)
2.5V
SENSE
COMPARATOR
2L
1L
+
-
COMPARATOR
OUTPUT
RC
A(or B)
VREF
A(or B)
SENSE
A(or B)
COFF
ROFF
R
SENSE
D01IN1332
Figure 11 shows the typical operating waveforms of the output current, the voltage drop across the sensing re-
sistor, the RC pin voltage and the status of the bridge. More details regarding the Synchronous Rectification and
the output stage configuration are included in the next section.
Immediately after the Power MOS turns on, a high peak current flows through the sensing resistor due to the
reverse recovery of the freewheeling diodes. The L6208 provides a 1
µs Blanking Time tBLANK that inhibits the
comparator output so that this current spike cannot prematurely re-trigger the monostable.
11/27
L6208
Figure 11. Output Current Regulation Waveforms
I
OUT
V
REF
R
SENSE
t
t
t
OFF
OFF
ON
1µs t
1µs t
BLANK
V
BLANK
SENSE
V
REF
Slow Decay
Slow Decay
0
t
t
V
RCRISE
RCRISE
RC
5V
2.5V
t
t
RCFALL
RCFALL
1µs t
1µs t
DT
DT
ON
SYNCHRONOUS OR QUASI
SYNCHRONOUS RECTIFICATION
OFF
B
C
D
A
B
C
D
D01IN1334
Figure 12 shows the magnitude of the Off Time t
calculated from the equations:
versus C
and R
values. It can be approximately
OFF
OFF
OFF
t
t
= 0.6 · R
· C
RCFALL
OFF OFF
= t
+ t = 0.6 · R
· C
+ t
OFF
RCFALL
DT
OFF
OFF
DT
where R
and C
are the external component values and t is the internally generated Dead Time with:
OFF DT
OFF
20KΩ ≤
0.47nF
= 1µs (typical value)
R
≤
100K
≤ 100nF
OFF
Ω
OFF
≤
C
t
DT
Therefore:
t
t
= 6.6µs
OFF(MIN)
= 6ms
OFF(MAX)
These values allow a sufficient range of t
to implement the drive circuit for most motors.
OFF
The capacitor value chosen for C
also affects the Rise Time t
of the voltage at the pin RCOFF. The
OFF
RCRISE
Rise Time t
will only be an issue if the capacitor is not completely charged before the next time the
RCRISE
monostable is triggered. Therefore, the on time t , which depends by motors and supply parameters, has to
ON
be bigger than t
for allowing a good current regulation by the PWM stage. Furthermore, the on time t
RCRISE
ON
can not be smaller than the minimum on time t
.
ON(MIN)
12/27
L6208
t
t
> t
> t
= 1.5µs (typ. value)
ON(MIN)
ON
ON
– t
RCRISE
DT
t
= 600 · C
RCRISE
OFF
Figure 13 shows the lower limit for the on time t for having a good PWM current regulation capacity. It has to
ON
be said that tON is always bigger than t
because the device imposes this condition, but it can be smaller
ON(MIN)
than t
- t . In this last case the device continues to work but the off time t
is not more constant.
RCRISE DT
OFF
So, small C
value gives more flexibility for the applications (allows smaller on time and, therefore, higher
OFF
switching frequency), but, the smaller is the value for C
performance.
, the more influential will be the noises on the circuit
OFF
Figure 12. t
versus C and R
OFF OFF
OFF
4
.
1 10
= 100kΩ
Roff
3
.
1 10
= 47kΩ
Roff
= 20kΩ
Roff
100
10
1
0.1
1
10
100
Coff [nF]
Figure 13. Area where t
can vary maintaining the PWM regulation.
ON
100
10
1.5µs (typ. value)
1
0.1
1
10
100
Coff [nF]
13/27
L6208
DECAY MODES
The CONTROL input is used to select the behavior of the bridge during the off time. When the CONTROL pin
is low, the Fast Decay mode is selected and both transistors in the bridge are switched off during the off time.
When the CONTROL pin is high, the Slow Decay mode is selected and only the low side transistor of the bridge
is switched off during the off time.
Figure 14 shows the operation of the bridge in the Fast Decay mode. At the start of the off time, both of the
power MOS are switched off and the current recirculates through the two opposite free wheeling diodes. The
current decays with a high di/dt since the voltage across the coil is essentially the power supply voltage. After
the dead time, the lower power MOS in parallel with the conducting diode is turned on in synchronous rectifica-
tion mode. In applications where the motor current is low it is possible that the current can decay completely to
zero during the off time. At this point if both of the power MOS were operating in the synchronous rectification
mode it would then be possible for the current to build in the opposite direction. To prevent this only the lower
power MOS is operated in synchronous rectification mode. This operation is called Quasi-Synchronous Recti-
fication Mode. When the monostable times out, the power MOS are turned on again after some delay set by the
dead time to prevent cross conduction.
Figure 15 shows the operation of the bridge in the Slow Decay mode. At the start of the off time, the lower power
MOS is switched off and the current recirculates around the upper half of the bridge. Since the voltage across
the coil is low, the current decays slowly. After the dead time the upper power MOS is operated in the synchro-
nous rectification mode. When the monostable times out, the lower power MOS is turned on again after some
delay set by the dead time to prevent cross conduction.
Figure 14. Fast Decay Mode Output Stage Configurations
A) ON TIME
B) 1µs DEAD TIME
C) QUASI-SYNCHRONOUS
RECTIFICATION
D) 1µs SLOW DECAY
D01IN1335
Figure 15. Slow Decay Mode Output Stage Configurations
A) ON TIME
B) 1µs DEAD TIME
C) SYNCHRONOUS
RECTIFICATION
D) 1µs DEAD TIME
D01IN1336
STEPPING SEQUENCE GENERATION
The phase sequence generator is a state machine that provides the phase and enable inputs for the two bridges
to drive a stepper motor in either full step or half step. Two full step modes are possible, the Normal Drive Mode
where both phases are energized each step and the Wave Drive Mode where only one phase is energized at a
14/27
L6208
time. The drive mode is selected by the HALF/FULL input and the current state of the sequence generator as
described below. A rising edge of the CLOCK input advances the state machine to the next state. The direction
of rotation is set by the CW/CCW input. The RESET input resets the state machine to state.
HALF STEP MODE
A HIGH logic level on the HALF/FULL input selects Half Step Mode. Figure 16 shows the motor current wave-
forms and the state diagram for the Phase Sequencer Generator. At Start-Up or after a RESET the Phase Se-
quencer is at state 1. After each clock pulse the state changes following the sequence 1,2,3,4,5,6,7,8,… if CW/
CCW is high (Clockwise movement) or 1,8,7,6,5,4,3,2,… if CW/CCW is low (Counterclockwise movement).
NORMAL DRIVE MODE (Full-step two-phase-on)
A LOW level on the HALF/FULL input selects the Full Step mode. When the low level is applied when the state
machine is at an ODD numbered state the Normal Drive Mode is selected. Figure Fig. 17 shows the motor cur-
rent waveform state diagram for the state machine of the Phase Sequencer Generator. The Normal Drive Mode
can easily be selected by holding the HALF/FULL input low and applying a RESET. AT start -up or after a RE-
SET the State Machine is in state1. While the HALF/FULL input is kept low, state changes following the se-
quence 1,3,5,7,… if CW/CCW is high (Clockwise movement) or 1,7,5,3,… if CW/CCW is low (Counterclockwise
movement).
WAVE DRIVE MODE (Full-step one-phase-on)
A LOW level on the pin HALF/FULL input selects the Full Step mode. When the low level is applied when the
state machine is at an EVEN numbered state the Wave Drive Mode is selected. Figure 18 shows the motor cur-
rent waveform and the state diagram for the state machine of the Phase Sequence Generator. To enter the
Wave Drive Mode the state machine must be in an EVEN numbered state. The most direct method to select the
Wave Drive Mode is to first apply a RESET, then while keeping the HALF/FULL input high apply one pulse to
the clock input then take the HALF/FULL input low. This sequence first forces the state machine to sate 1. The
clock pulse, with the HALF/FULL input high advances the state machine from state 1 to either state 2 or 8 de-
pending on the CW/CCW input. Starting from this point, after each clock pulse (rising edge) will advance the
state machine following the sequence 2,4,6,8,… if CW/CCW is high (Clockwise movement) or 8,6,4,2,… if CW/
CCW is low (Counterclockwise movement).
Figure 16. Half Step Mode
IOUTA
3
2
1
4
8
5
6
7
IOUTB
Start Up or Reset
CLOCK
1
2
3
4
5
6
7
8
D01IN1320
Figure 17. Normal Drive Mode
IOUTA
3
2
1
4
8
5
6
7
IOUTB
CLOCK
Start Up or Reset
1
3
5
7
1
3
5
7
D01IN1322
15/27
L6208
Figure 18. Wave Drive Mode
I
I
OUTA
OUTB
3
2
1
4
8
5
6
7
CLOCK
2
4
6
8
2
4
6
8
Start Up or Reset
D01IN1321
NON-DISSIPATIVE OVERCURRENT PROTECTION
The L6208 integrates an Overcurrent Detection Circuit (OCD). This circuit provides protection against a short
circuit to ground or between two phases of the bridge. With this internal over current detection, the external cur-
rent sense resistor normally used and its associated power dissipation are eliminated. Figure 19 shows a sim-
plified schematic of the overcurrent detection circuit.
To implement the over current detection, a sensing element that delivers a small but precise fraction of the out-
put current is implemented with each high side power MOS. Since this current is a small fraction of the output
current there is very little additional power dissipation. This current is compared with an internal reference cur-
rent I
. When the output current reaches the detection threshold (typically 5.6A) the OCD comparator signals
REF
a fault condition. When a fault condition is detected, the EN pin is pulled below the turn off threshold (1.3V typ-
ical) by an internal open drain MOS with a pull down capability of 4mA. By using an external R-C on the EN pin,
the off time before recovering normal operation can be easily programmed by means of the accurate thresholds
of the logic inputs.
Figure 19. Overcurrent Protection Simplified Schematic
OUT1A VSA OUT2A
POWER SENSE
1 cell
HIGH SIDE DMOSs OF
THE BRIDGE A
I1A
I2A
POWER SENSE
1 cell
POWER DMOS
n cells
POWER DMOS
n cells
TO GATE
LOGIC
+
µC or LOGIC
I1A / n
I2A / n
OCD
COMPARATOR
VDD
(I1A+I2A) / n
IREF
REN
.
.
EN
INTERNAL
OPEN-DRAIN
CEN
RDS(ON)
40Ω TYP.
OVER TEMPERATURE
FROM THE
BRIDGE B
OCD
COMPARATOR
D01IN1337
16/27
L6208
Figure 20 shows the Overcurrent Detection operation. The Disable Time t
before recovering normal oper-
DISABLE
ation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by
and R values and its magnitude is reported in Figure 21. The Delay Time t before turning off the
C
EN
EN
DELAY
bridge when an overcurrent has been detected depends only by C value. Its magnitude is reported in Figure 22.
EN
C
EN
is also used for providing immunity to pin EN against fast transient noises. Therefore the value of C
EN
should be chosen as big as possible according to the maximum tolerable Delay Time and the R value should
EN
be chosen according to the desired Disable Time.
The resistor R should be chosen in the range from 2.2K
Ω
to 180K
Ω. Recommended values for R and C
EN EN
EN
are respectively 100K
Ω and 5.6nF that allow obtaining 200µs Disable Time.
Figure 20. Overcurrent Protection Waveforms
I
OUT
I
SOVER
V
EN
V
DD
V
th(ON)
V
th(OFF)
V
EN(LOW)
ON
OCD
OFF
ON
BRIDGE
OFF
t
t
DELAY
DISABLE
t
t
t
t
t
OCD(ON)
EN(FALL)
OCD(OFF)
EN(RISE)
D(ON)EN
D02IN1400
t
D(OFF)EN
17/27
L6208
Figure 21. t
versus C and R (V = 5V).
EN EN DD
DISABLE
Ω
Ω
R E N = 100 k
R E N = 220 k
3
.
Ω
Ω
R EN = 47 k
R EN = 33 k
1 10
Ω
R EN = 10 k
100
10
1
1
10
100
C E N [nF]
Figure 22. t
versus C (V = 5V).
EN DD
DELAY
10
1
0.1
1
10
100
Cen [nF]
THERMAL PROTECTION
In addition to the Ovecurrent Protection, the L6208 integrates a Thermal Protection for preventing the device
destruction in case of junction over temperature. It works sensing the die temperature by means of a sensible
element integrated in the die. The device switch-off when the junction temperature reaches 165°C (typ. value)
with 15°C hysteresis (typ. value).
18/27
L6208
APPLICATION INFORMATION
A typical Bipolar Stepper Motor Driver application using L6208 is shown in Fig. 23. Typical component values
for the application are shown in Table 2. A high quality ceramic capacitor in the range of 100 to 200 nF should
be placed between the power pins (VS and VS ) and ground near the L6208 to improve the high frequency
A
B
filtering on the power supply and reduce high frequency transients generated by the switching. The capacitor
connected from the EN input to ground sets the shut down time when an over current is detected (see Overcur-
rent Protection). The two current sensing inputs (SENSE and SENSE ) should be connected to the sensing
A
B
resistors with a trace length as short as possible in the layout. The sense resistors should be non-inductive re-
sistors to minimize the di/dt transients across the resistor. To increase noise immunity, unused logic pins (except
EN) are best connected to 5V (High Logic Level) or GND (Low Logic Level) (see pin description). It is recom-
mended to keep Power Ground and Signal Ground separated on PCB.
Table 2. Component Values for Typical Application
C
C
C
C
C
C
C
C
100µF
100nF
1nF
D
D
R
R
R
R
R
R
1N4148
1N4148
39KΩ
39KΩ
100KΩ
100Ω
1
1
2
2
A
A
1nF
B
B
220nF
10nF
5.6nF
68nF
BOOT
P
EN
P
0.3Ω
EN
REF
SENSEA
SENSEB
0.3Ω
Figure 23. Typical Application
VSA
VSB
+
VS
8-52VDC
20
17
VREFA
VREFB
24
11
VREF = 0-1V
C1
C2
POWER
GROUND
-
CREF
D1
CP
RP
VCP
RESET
EN
22
23
14
RESET
REN
CEN
D2
CBOOT
ENABLE
VBOOT
SENSEA
SENSEB
SIGNAL
GROUND
15
3
RSENSEA
RSENSEB
CONTROL
HALF/FULL
CLOCK
13
12
1
FAST/SLOW DECAY
HALF/FULL
CLOCK
10
OUT1A
OUT2A
5
21
CW/CCW
M
2
CW/CCW
OUT1B
OUT2B
CA
8
16
18
19
6
RCA
4
RA
CB
GND
GND
GND
GND
RCB
7
9
RB
D01IN1341
19/27
L6208
Output Current Capability and IC Power Dissipation
In Fig. 24, 25, 26 and 27 are shown the approximate relation between the output current and the IC power dis-
sipation using PWM current control driving a two-phase stepper motor, for different driving sequences:
– HALF STEP mode (Fig. 24) in which alternately one phase / two phases are energized.
– NORMAL DRIVE (FULL-STEP TWO PHASE ON) mode (Fig. 25) in which two phases are energized
during each step.
– WAVE DRIVE (FULL-STEP ONE PHASE ON) mode (Fig. 26) in which only one phase is energized at
each step.
– MICROSTEPPING mode (Fig. 27), in which the current follows a sine-wave profile, provided through
the V pins.
ref
For a given output current and driving sequence the power dissipated by the IC can be easily evaluated, in order
to establish which package should be used and how large must be the on-board copper dissipating area to guar-
antee a safe operating junction temperature (125°C maximum).
Figure 24. IC Power Dissipation versus Output Current in HALF STEP Mode.
HALF STEP
IA
IB
10
8
IOUT
6
IOUT
PD [W]
4
Test Conditions:
Supply Voltage= 24V
No PWM
2
0
0
0.5
1
1.5
IOUT [A]
2
2.5
3
f
SW = 30 kHz (slow decay)
Figure 25. IC Power Dissipation versus Output Current in NORMAL Mode (full step two phase on).
NORMAL DRIVE
IA
10
8
IOUT
IB
6
IOUT
PD [W]
4
2
0
Test Conditions:
Supply Voltage =24V
No PWM
fSW = 30kHz (slow decay)
0
0.5
1
1.5
OUT [A]
2
2.5
3
I
20/27
L6208
Figure 26. IC Power Dissipation versus Output Current in WAVE Mode (full step one phase on).
WAVE DRIVE
10
8
IA
IOUT
IB
6
PD [W]
IOUT
4
2
0
Test Conditions:
Supply Voltage = 24V
No PWM
f
SW = 30 kHz (slow decay)
0
0.5
1
1.5
2
2.5
3
I
OUT [A]
Figure 27. IC Power Dissipation versus Output Current in MICROSTEPPING Mode.
MICROSTEPPING
IA
IOUT
10
8
IOUT
6
IB
PD [W]
4
2
0
Test Conditions:
Supply Voltage = 24V
0
0.5
1
1.5
2
2.5
3
fSW = 30 kHz (slow decay)
fSW = 50 kHz (slow decay)
IOUT [A]
Thermal Management
In most applications the power dissipation in the IC is the main factor that sets the maximum current that can
be delivered by the device in a safe operating condition. Therefore, it has to be taken into account very carefully.
Besides the available space on the PCB, the right package should be chosen considering the power dissipation.
Heat sinking can be achieved using copper on the PCB with proper area and thickness. Figures 28, 29 and 30
show the Junction-to-Ambient Thermal Resistance values for the PowerSO36, PowerDIP24 and SO24 packag-
es.
For instance, using a PowerSO package with copper slug soldered on a 1.5mm copper thickness FR4 board
2
with 6cm dissipating footprint (copper thickness of 35µm), the R
is about 35°C/W. Fig. 31 shows mount-
th(j-amb)
ing methods for this package. Using a multi-layer board with vias to a ground plane, thermal impedance can be
reduced down to 15°C/W.
21/27
L6208
Figure 28. PowerSO36 Junction-Ambient Thermal Resistance versus On-Board Copper Area.
ºC / W
43
38
33
W ithout Ground Layer
28
W ith Ground Layer
W ith Ground Layer+16 via
H oles
23
On-Board Copper Area
18
13
1
2
3
4
5
6
7
8
9
10 11 12 13
sq. cm
Figure 29. PowerDIP24 Junction-Ambient Thermal Resistance versus On-Board Copper Area.
ºC / W
On-Board Copper Area
49
48
Copper Are a is on Bottom
S ide
47
46
Copper Are a is on To p Side
45
44
43
42
41
40
39
1
2
3
4
5
6
7
8
9
10 11 12
sq. cm
Figure 30. SO24 Junction-Ambient Thermal Resistance versus On-Board Copper Area.
ºC / W
On-Board Copper Area
68
66
64
62
60
C o pp er Are a is on Top Sid e
58
56
54
52
50
48
1
2
3
4
5
6
7
8
9
10 11 12
sq. cm
Figure 31. Mounting the PowerSO Package.
Slug soldered
to PCB with
dissipating area
Slug soldered
Slug soldered to PCB with
dissipating area plus ground layer
contacted through via holes
to PCB with
dissipating area
plus ground layer
22/27
L6208
Figure 32. Typical Quiescent Current vs.
Figure 35. Typical High-Side RDS(ON) vs.
Supply Voltage
Supply Voltage
Iq [mA]
Ω
[ ]
RDS(ON)
5.6
0.380
0.376
0.372
0.368
0.364
0.360
0.356
0.352
0.348
0.344
0.340
0.336
f
= 1kHz
T = 25°C
j
sw
T = 85°C
j
5.4
5.2
5.0
4.8
4.6
T = 25°C
j
T = 125°C
j
0
5
10
15
VS [V]
20
25
30
0
10
20
30
40
50
60
VS [V]
Figure 33. Normalized Typical Quiescent
Figure 36. Normalized R
vs.Junction
DS(ON)
Current vs. Switching Frequency
Iq / (Iq @ 1 kHz)
Temperature (typical value)
RDS(ON) / (RDS(ON) @ 25 °C)
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
1.8
1.6
1.4
1.2
1.0
0.8
0
20
40
60
80
100
120
140
0
20
40
60
80
100
Tj [°C]
fSW [kHz]
Figure 34. Typical Low-Side R
Voltage
vs. Supply
Figure 37. Typical Drain-Source Diode Forward
DS(ON)
ON Characteristic
Ω
RDS(ON)
[
]
ISD [A]
0.300
3.0
T = 25°C
j
0.296
0.292
0.288
0.284
0.280
0.276
2.5
2.0
1.5
1.0
0.5
0.0
T = 25°C
j
700
800
900
1000
SD [mV]
1100
1200
1300
0
5
10
15
20
25
30
V
V
S [V]
23/27
L6208
mm
inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
OUTLINE AND
MECHANICAL DATA
A
a1
a2
a3
b
3.60
0.141
0.012
0.130
0.004
0.015
0.012
0.630
0.385
0.570
0.10
0.30 0.004
3.30
0
0.10
0
0.22
0.23
0.38 0.008
0.32 0.009
16.00 0.622
9.80 0.370
14.50 0.547
c
D (1) 15.80
D1
E
9.40
13.90
e
0.65
0.0256
0.435
e3
11.05
E1 (1) 10.90
E2
11.10 0.429
2.90
0.437
0.114
0.244
0.126
0.004
0.626
0.043
0.043
E3
E4
G
H
5.80
2.90
0
6.20 0.228
3.20 0.114
0.10
0
15.50
15.90 0.610
1.10
h
L
0.80
1.10 0.031
10°(max.)
8 °(max.)
N
S
PowerSO36
(1): "D" and "E1" do not include mold flash or protrusions
- Mold flash or protrusions shall not exceed 0.15mm (0.006 inch)
- Critical dimensions are "a3", "E" and "G".
N
N
a2
A
c
a1
e
A
DETAIL B
lead
E
DETAIL A
e3
H
DETAIL A
D
slug
a3
BOTTOM VIEW
36
19
E3
B
E1
E2
D1
DETAIL B
0.35
Gage Plane
- C -
SEATING PLANE
1
1
8
S
L
G
C
M
b
0.12
A B
PSO36MEC
h x 45˚
(COPLANARITY)
24/27
L6208
mm
MIN. TYP. MAX. MIN. TYP. MAX.
4.320 0.170
inch
DIM.
OUTLINE AND
MECHANICAL DATA
A
A1
A2
B
0.380
0.015
3.300
0.130
0.410 0.460 0.510 0.016 0.018 0.020
1.400 1.520 1.650 0.055 0.060 0.065
0.200 0.250 0.300 0.008 0.010 0.012
31.62 31.75 31.88 1.245 1.250 1.255
B1
c
D
E
7.620
8.260 0.300
0.325
e
2.54
0.100
E1
6.350 6.600 6.860 0.250 0.260 0.270
0.300
7.620
e1
L
3.180
3.430 0.125
0.135
Powerdip 24
M
0˚ min, 15˚ max.
E1
A2
A
A1
L
B
B1
e
e1
D
24
1
13
12
c
M
SDIP24L
25/27
L6208
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN.
2.35
0.10
0.33
0.23
15.20
TYP. MAX. MIN.
2.65 0.093
0.30 0.004
0.51 0.013
0.32 0.009
15.60 0.598
TYP. MAX.
0.104
A
A1
B
0.012
0.200
Weight: 0.60gr
C
0.013
(1)
0.614
D
E
e
7.40
7.60 0.291
1.27
0.299
0.050
H
10.0
0.25
0.40
10.65 0.394
0;75 0.010
1.27 0.016
0˚ (min.), 8˚ (max.)
0.10
0.419
h
0.030
L
0.050
k
ddd
0.004
SO24
(1) “D” dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
0070769 C
26/27
L6208
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
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