EVAL6482H [STMICROELECTRONICS]
High power microstepping motor driver with the L6482H; 大功率微电机驱动器与L6482H
| 型号： | EVAL6482H |
| 厂家： | 
ST |
| 描述： | High power microstepping motor driver with the L6482H |
| 文件： | 总12页 (文件大小：522K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVAL6482H
High power microstepping motor driver with the L6482H
Data brief
Features
■ Voltage range from 10.5 V to 85 V
■ Low Rds(ON) MOSFETs in DPAK package
■ SPI with daisy chain feature
■ FLAG and BUSY LED indicators
■ Flexible supply voltage management
■ Suitable for use in combination with the
STEVAL-PCC009V2
Applications
■ High power bipolar stepper motor driving
Description
The EVAL6482H demonstration board is a high
power microstepping motor driver. In combination
with the STEVAL-PCC009V2 communication
board and the evaluation software, the board
allows the user to investigate all the features of
the L6482 device. In particular, the board can be
used to check the advanced current control and to
regulate the L6482 parameters in order to fit the
application requirements.
The EVAL6482H supports the daisy chain
configuration making it suitable for the evaluation
of the L6482 in multi-motor applications.
October 2012
Doc ID 023870 Rev 1
1/12
This is information on a product in full production. For further information contact your local STMicroelectronics sales
office.
www.st.com
12
Board description
EVAL6482H
1
Board description
Table 1.
EVAL6482H electrical specifications
Parameter
Value
Supply voltage (VS)
10.5 to 85 V
Maximum output current (each phase)
External MOSFET Rds(ON)
Gate driver supply voltage (VCC)
Logic supply voltage
6 Ar.m.s. at 25 °C(1)
33 mΩ typical at 25 °C(2)
7.5 V to 15 V
3.3 V
Logic interface supply voltage
Low level logic input
3.3 V or 5 V
0 V
High level logic input
VDD(3)
Operating temperature
-25 °C to +125 °C
1. Limited by the mounted sensing resistors.
2. Refer to STD25NF10 datasheet for details.
3. All logic inputs are 5 V tolerant.
Figure 1.
Jumper and connector location
Slave SPI
connector
BUSY LED
FLAG LED
Master SPI
connector
External switch
connector
(SW input)
Application
area
ADCIN input
Power supply connector
(10.5 V - 85 V)
Supply management
connector
(VS, VSREG, VCCREG and GND)
Supply management
jumpers
Phase A
connector
Phase B
connector
AM15181v1
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Doc ID 023870 Rev 1
EVAL6482H
Board description
Table 2.
Jumper and connector description
Type
Name
Function
J5
J7
Power supply
Power output
Power output
Power supply
SPI
Main supply voltage
Power bridge A outputs
Power bridge B outputs
J8
J6
Integrated voltage regulator inputs
Master SPI connector
J3
J4
SPI
Slave SPI connector
JP1
JP2
JP3
JP4
JP5
JP6
JP7
JP8
Jumper
VS to VSREG jumper
Jumper
VSREG to VCC jumper
VCC to VCCREG jumper
VCCREG to VREG jumper
VREG to VDD jumper
Jumper
Jumper
Jumper
Jumper
VDD to 3.3 V from SPI connector jumper
Daisy chain termination jumper
STBY to VS pull-up jumper
Jumper
Jumper
Table 3.
Master SPI connector pinout (J3)
Pin number
Type
Description
1
2
3
4
Open drain output
Open drain output
Ground
L6482 BUSY output
L6482 FLAG output
Ground
Supply
EXT_VDD (can be used as external logic power supply)
SPI master IN slave OUT signal (connected to the L6482 SDO
output through daisy chain termination jumper JP7)
5
6
7
Digital output
Digital input
Digital input
SPI serial clock signal (connected to L6482 CK input)
SPI master Out slave IN signal (connected to L6482 SDI
input)
8
9
Digital input
Digital input
Digital input
SPI slave select signal (connected to L6482 CS input)
L6482 step-clock input
10
L6482 standby/reset input
Table 4.
Slave SPI connector pinout (J4)
Pin number
Type
Description
1
2
3
Open drain output
Open drain output
Ground
L6482 BUSY output
L6482 FLAG output
Ground
Doc ID 023870 Rev 1
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Board description
EVAL6482H
Table 4.
Slave SPI connector pinout (J4) (continued)
Pin number
Type
Description
4
5
6
7
Supply
EXT_VDD (can be used as external logic power supply)
SPI master In slave Out signal (connected to pin 5 of
J3)
Digital output
Digital input
Digital input
SPI serial clock signal (connected to L6482 CK input)
SPI master Out slave In signal (connected to L6482 SDO
output)
8
9
Digital input
Digital input
Digital input
SPI slave select signal (connected to L6482 CS input)
L6482 step-clock input
10
L6482 standby/reset input
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Doc ID 023870 Rev 1
EVAL6482H
Figure 2.
Board description
EVAL6482H schematic part 1/2
1
1
1
2
2
1
1
1
2
1
AM15182v1
Doc ID 023870 Rev 1
5/12
Board description
EVAL6482H
Figure 3.
EVAL6482H schematic part 2/2
4
3
3
4
1
2
4
3
4
3
3
4
3
4
1
2
3
4
3
4
1
3
AM15183v1
6/12
Doc ID 023870 Rev 1
EVAL6482H
Table 5.
Board description
Package
EVAL6482H - bill of material
Reference
Item
Quantity
Value
VS, VREG, VDD, VCC,
1
9
TPTH-RING (red)
TPTH-RING-1MM
STCK, STBY, FLAG,
BUSY, ADCIN
2
3
1
2
3
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
5
3
2
GND
TP-RING (black)
470 nF/25 V
220 nF/100 V
100 nF/6.3 V
100 nF/4 V
TPTH-RING-1MM
CAPC-0603
CAPC-0805
CAPC-0603
CAPC-0603
CAPC-1206
CAPC-0603
CAPC-0603
CAPC-0805
CAPC-0603
CAPES-R18H17
CAPE-R16H21-P75
CAPC-0603
LEDC-0805
LEDC-0805
SOT-23
C1,C7
4
C2, C14, C15
5
C3
6
C4
7
C5
22 µF/6.3 V
100 nF/25 V
100 nF/100 V
47 nF/100 V
10 nF/6.3 V
220 µF/100 V
220 µF/100 V
100 pF/6.3 V
LED amber
LED red
8
C6
9
C8
10
11
12
13
14
15
16
17
18
19
20
21
22
C9
C10, C13
C11
C11A
C12
DL1
DL2
D1
BAV99
D2
D3
BZX585-B3V3
BZX585-B3V6
Jumper CLOSED
Jumper OPEN
N.M.
SOD523
SOD523
JP1, JP3, JP5, JP7, JP8
JP2, JP4, JP6
J1, J2
JP2SO
JP2SO
STRIP254P-M-2
Pol. IDC male header vertical
10 poles (black)
23
24
1
1
J3
J4
CON-FLAT-5X2-180M
CON-FLAT-5X2-180M
Pol. IDC male header vertical
10 poles (gray)
25
26
3
1
J5, J7, J8
J6
Screw connector 2 poles
N.M.
MORSV-508-2P
STRIP254P-M-4
Q1, Q2, Q3, Q4, Q5, Q6,
Q7, Q8
27
8
STD25NF10
DPAK
28
29
30
31
1
2
2
2
R1
100 Ω
39 kΩ
RESC-0603
RESC-0603
RESC-0603
RESC-0603
R2, R3
R4, R5
R6, R7
470 Ω
100 kΩ / 0.125 W
Doc ID 023870 Rev 1
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Board description
EVAL6482H
Table 5.
Item
EVAL6482H - bill of material (continued)
Quantity
Reference
Value
Package
RESC-0603
32
33
34
1
1
4
R9
R17
N.M.
50 kΩ / 0.125 W
0.1 Ω /2 W
TRIMM-100X50X110-64W
RESC-2010
R18,R19,R20,R21
HTSSOP050P-660X110-
38-EP
35
1
U1
L6482
Figure 4.
EVAL6482H - layout (silkscreen)
AM15184v1
8/12
Doc ID 023870 Rev 1
EVAL6482H
Board description
Figure 5.
EVAL6482H - layout (top layer)
AM15185v1
Figure 6.
EVAL6482H - layout (inner layer 2)
AM15187v1
Doc ID 023870 Rev 1
9/12
Board description
EVAL6482H
Figure 7.
EVAL6482H - layout (inner layer 3)
AM15188v1
Figure 8.
EVAL6482H - layout (bottom layer)
AM15189v1
10/12
Doc ID 023870 Rev 1
EVAL6482H
Revision history
2
Revision history
Table 6.
Date
30-Oct-2012
Document revision history
Revision
Changes
1
Initial release.
Doc ID 023870 Rev 1
11/12
EVAL6482H
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Doc ID 023870 Rev 1
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