EVAL6561-80 [STMICROELECTRONICS]
POWER FACTOR CORRECTOR; 功率因数校正
| 型号： | EVAL6561-80 |
| 厂家： | 
ST |
| 描述： | POWER FACTOR CORRECTOR |
| 文件： | 总13页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6561
POWER FACTOR CORRECTOR
1 FEATURES
Figure 1. Packages
■ VERY PRECISE ADJUSTABLE OUTPUT
OVERVOLTAGE PROTECTION
■ MICRO POWER START-UP CURRENT (50µA
TYP.)
SO-8
DIP-8
■ VERY LOW OPERATING SUPPLY
CURRENT(4mA TYP.)
Table 1. Order Codes
■ INTERNAL START-UP TIMER
■ CURRENT SENSE FILTER ON CHIP
■ DISABLE FUNCTION
■ 1% PRECISION (@ Tj = 25°C) INTERNAL
REFERENCE VOLTAGE
Part Number
L6561
Package
DIP-8
L6561D
SO-8
L6561D013TR
Tape & Reel
■ TRANSITION MODE OPERATION
■ TOTEM POLE OUTPUT CURRENT: ±400mA
■ DIP-8/SO-8 PACKAGES
Realised in mixed BCD technology, the chip gives
the following benefits:
– micro power start up current
– 1% precision internal reference voltage
– (Tj = 25°C)
– Soft Output Over Voltage Protection
– no need for external low pass filter on the cur-
rent sense
– very low operating quiescent current minimis-
es power dissipation
2 DESCRIPTION
L6561 is the improved version of the L6560 stan-
dard Power Factor Corrector. Fully compatible
with the standard version, it has a superior perfor-
mant multiplier making the device capable of work-
ing in wide input voltage range applications (from
85V to 265V) with an excellent THD. Furthermore
the start up current has been reduced at few tens
of mA and a disable function has been implement-
ed on the ZCD pin, guaranteeing lower current
consumption in stand by mode.
The totem pole output stage is capable of driving
a Power MOS or IGBT with source and sink cur-
rents of ±400mA. The device is operating in tran-
sition mode and it is optimised for Electronic Lamp
Ballast application, AC-DC adaptors and SMPS.
Figure 2. Block Diagram
COMP
MULT
3
CS
2
4
1
INV
-
40K
2.5V
MULTIPLIER
+
5pF
VOLTAGE
REGULATOR
OVER-VOLTAGE
DETECTION
-
+
VCC
8
VCC
INTERNAL
SUPPLY 7V
R
S
Q
20V
R1
7
GD
+
-
UVLO
DRIVER
R2
VREF2
ZERO CURRENT
DETECTOR
2.1V
1.6V
+
-
STARTER
DISABLE
6
5
D97IN547E
GND
ZCD
REV. 16
1/13
June 2004
L6561
Table 2. Absolute Maximum Ratings
Symbol
IVcc
Pin
8
Parameter
Value
30
Unit
mA
mA
V
Iq + IZ; (IGD = 0)
Output Totem Pole Peak Current (2µs)
IGD
7
±700
INV, COMP 1, 2, 3 Analog Inputs & Outputs
MULT
-0.3 to 7
CS
4
5
Current Sense Input
Zero Current Detector
-0.3 to 7
V
ZCD
50 (source)
-10 (sink)
mA
mA
Ptot
Power Dissipation @Tamb = 50 °C
(DIP-8)
(SO-8)
1
0.65
W
W
Tj
Junction Temperature Operating Range
Storage Temperature
-40 to 150
-55 to 150
°C
°C
Tstg
Figure 3. Pin Connection (Top view)
INV
1
2
3
4
8
7
6
5
VCC
COMP
MULT
CS
GD
GND
ZCD
DIP8
Table 3. Thermal Data
Symbol
Parameter
SO 8
150
MINIDIP
Unit
Rth j-amb Thermal Resistance Junction to ambient
100
°C/W
Table 4. Pin Description
N.
Name
Function
1
INV
Inverting input of the error amplifier. A resistive divider is connected between the output
regulated voltage and this point, to provide voltage feedback.
2
3
4
COMP Output of error amplifier. A feedback compensation network is placed between this pin and the
INV pin.
MULT
Input of the multiplier stage. A resistive divider connects to this pin the rectified mains. A voltage
signal, proportional to the rectified mains, appears on this pin.
CS
Input to the comparator of the control loop. The current is sensed by a resistor and the resulting
voltage is applied to this pin.
5
6
7
ZCD
GND
GD
Zero current detection input. If it is connected to GND, the device is disabled.
Current return for driver and control circuits.
Gate driver output. A push pull output stage is able to drive the Power MOS with peak current of
400mA (source and sink).
8
VCC
Supply voltage of driver and control circuits.
(1) Parameter guaranteed by design, not tested in production.
2/13
L6561
Table 5. Electrical Characteristics
(VCC = 14.5V; Tamb = -25°C to 125°C;unless otherwise specified)
Symbol Pin
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY VOLTAGE SECTION
VCC
VCC ON
VCC OFF
Hys
8
8
8
8
Operating Range
Turn-on Threshold
Turn-off Threshold
Hysteresis
after turn-on
11
11
18
13
V
V
V
V
12
9.5
2.5
8.7
2.2
10.3
2.8
SUPPLY CURRENT SECTION
ISTART-U
Iq
8
8
8
Start-up Current
before turn-on (VCC =11V)
20
50
2.6
4
90
4
µA
mA
mA
mA
mA
µA
V
Quiescent Current
Operating Supply Current
ICC
CL = 1nF @ 70KHz
5.5
2.1
2.1
90
22
in OVP condition Vpin1 = 2.7V
1.4
1.4
50
20
Iq
8
8
8
Quiescent Current
Zener Voltage
V
V
PIN5 ≤150mV, VCC > VCC off
PIN5 ≤ 150mV, VCC < VCC off
20
18
VZ
ICC = 25mA
ERROR AMPLIFIER SECTION
VINV
1
Voltage Feedback Input
Threshold
Tamb = 25°C
2.465
2.44
2.5
2.535
2.56
5
V
V
12V < VCC < 18V
VCC = 12 to 18V
Line Regulation
Input Bias Current
Voltage Gain
2
-0.1
80
mV
µA
dB
MHz
mA
mA
V
IINV
GV
1
-1
Open loop
60
GB
Gain Bandwidth
Source Current
Sink Current
1
ICOMP
2
2
VCOMP = 4V, VINV = 2.4V
VCOMP = 4V, VINV = 2.6V
ISOURCE = 0.5mA
-2
-4
-8
2.5
4.5
5.8
2.25
VCOMP
Upper Clamp Voltage
Lower Clamp Voltage
ISink = 0.5mA
V
MULTIPLIER SECTION
VMULT
3
Linear Operating Voltage
Output Max. Slope
0 to 3 0 to 3.5
V
VMULT = from 0V to 0.5V
1.65
1.9
∆VCS
-----------------
∆Vmult
V
COMP = Upper Clamp Voltage
K
Gain
V
MULT = 1V VCOMP = 4V
0.45
1.6
0.6
1.7
0.75
1.8
1/V
V
CURRENT SENSE COMPARATOR
VCS
4
Current Sense Reference
Clamp
VMULT = 2.5V
COMP = Upper Clamp Voltage
V
ICS
4
4
4
Input Bias Current
Delay to Output
VOS = 0
-0.05
200
0
-1
450
15
µA
ns
td (H-L)
Current Sense Offset
mV
ZERO CURRENT DETECTOR
VZCD
5
Input Threshold Voltage Rising (1)
2.1
V
Edge
Hysteresis
(1)
0.3
4.5
4.7
0.5
5.1
5.2
0.7
5.9
6.1
V
V
V
VZCD
VZCD
5
5
Upper Clamp Voltage
Upper Clamp Voltage
IZCD = 20µA
IZCD = 3mA
3/13
L6561
Table 5. Electrical Characteristics (continued)
(VCC = 14.5V; Tamb = -25°C to 125°C;unless otherwise specified)
Symbol Pin
Parameter
Lower Clamp Voltage
Sink Bias Current
Test Condition
IZCD = -3mA
Min.
Typ.
0.65
2
Max.
Unit
V
VZCD
IZCD
IZCD
IZCD
VDIS
IZCD
5
5
5
5
5
5
0.3
1
1V ≤ VZCD ≤ 4.5V
µA
Source Current Capability
Sink Current Capability
Disable threshold
-3
3
-10
10
mA
mA
mV
µA
150
-100
200
250
-300
Restart Current After Disable
VZCD < Vdis; VCC > VCCOFF
-200
OUTPUT SECTION
VGD
7
Dropout Voltage
IGDsource = 200mA
GDsource = 20mA
IGDsink = 200mA
GDsink = 20mA
1.2
0.7
2
1
V
V
I
1.5
0.3
100
100
-
V
I
V
tr
tf
7
7
7
Output Voltage Rise Time
Output Voltage Fall Time
IGD Sink Current
CL = 1nF
40
40
10
ns
ns
mA
CL = 1nF
IGD off
VCC =3.5V VGD = 1V
5
OUTPUT OVERVOLTAGE SECTION
IOVP
2
OVP Triggering Current
Static OVP Threshold
35
40
45
µA
2.1
2.25
2.4
V
RESTART TIMER
tSTART
Start Timer
70
150
400
µs
3 OVER VOLTAGE PROTECTION OVP
The output voltage is expected to be kept by the operation of the PFC circuit close to its nominal value.
This is set by the ratio of the two external resistors R1 and R2 (see fig. 5), taking into consideration that
the non inverting input of the error amplifier is biased inside the L6561 at 2.5V.
In steady state conditions, the current through R1 and R2 is:
V
– 2.5
2.5V
R2
out
I
= ------------------------- = I
= ------------
R2
R1sc
R1
and, if the external compensation network is made only with a capacitor Ccomp, the current through Ccomp
equals zero.When the output voltage increases abruptly the current through R1 becomes:
V
+ ∆V
– 2.5
out
outsc
I
= ---------------------------------------------------- = I
+ ∆I
R1sc R1
R1
R1
Since the current through R2 does not change, ∆IR1 must flow through the capacitor Ccomp and enter the
error amplifier.
This current is monitored inside the L6561 and when reaches about 37µA the output voltage of the multi-
plier is forced to decrease, thus reducing the energy drawn from the mains. If the current exceeds 40µA,
the OVP protection is triggered (Dynamic OVP), and the external power transistor is switched off until the
current falls approximately below 10µA.
However, if the overvoltage persists, an internal comparator (Static OVP) confirms the OVP condition
keeping the external power switch turned off (see fig. 4).Finally, the overvoltage that triggers the OVP
function is:
∆Vout = R1 · 40µA.
Typical values for R1, R2 and C are shown in the application circuits. The overvoltage can be set indepen-
4/13
L6561
dently from the average output voltage. The precision in setting the overvoltage threshold is 7% of the ov-
ervoltage value (for instance ∆V = 60V ± 4.2V).
3.1 Disable function
The zero current detector (ZCD) pin can be used for device disabling as well. By grounding the ZCD volt-
age the device is disabled reducing the supply current consumption at 1.4mA typical (@ 14.5V supply volt-
age).
Releasing the ZCD pin the internal start-up timer will restart the device.
Figure 4.
OVER VOLTAGE
V
OUT nominal
40µA
10µA
I
SC
E/A OUTPUT
2.25V
DYNAMIC OVP
STATIC OVP
D97IN592A
Figure 5. Overvoltage Protection Circuit
Ccomp.
+Vo
R1
∆I
1
2
-
E/A
X
PWM
DRIVER
+
R2
2.5V
-
+
2.25V
∆I
40µA
D97IN591
5/13
L6561
Figure 6. Typical Application Circuit (80W, 110VAC)
D1 BYT03-400
+
T
C6
Vo=240V
Po=80W
R7 (*)
950K
R3 (*)
240K
R2
D3 1N4150
100
10nF
R1
D2
1N5248B
C3 680nF
BRIDGE
68K
4 x 1N4007
+
-
C1
1µF
250V
R9 (*)
950K
FUSE 4A/250V
5
2
1
8
R5
10
MOS
STP7NA40
C5
100µF
315V
7
4
L6561
Vac
(85V to 135V)
3
6
R10
10K
C2
22µF
25V
C7
10nF
NTC
R6 (*)
0.31
1W
R8
10K
1%
-
D97IN549B
(*) R3 = 2 x 120KΩ
R6 = 0.619Ω/2
R7 = 2 x 475KΩ, 1%
R9 = 2 x 475KΩ
TRANSFORMER
T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT (OREGA 473201A7)
primary 90T of Litz wire 10 x 0.2mm
secondary 11T of #27 AWG (0.15mm)
gap 1.8mm for a total primary inductance of 0.7mH
Figure 7. Typical Application Circuit (120W, 220VAC)
D1 BYT13-600
+
T
C6
Vo=400V
Po=120W
R3 (*)
440K
R2
D3 1N4150
R7 (*)
998K
100
10nF
R1
D2
1N5248B
C3 1µF
BRIDGE
68K
4 x 1N4007
+
-
C1
560nF
400V
FUSE 2A/250V
R9 (*)
1.82M
5
2
1
8
R5
10
MOS
STP5NA50
C5
56µF
450V
7
4
L6561
Vac
(175V to 265V)
3
6
C2
22µF
25V
R10
10K
C7
10nF
NTC
R6 (*)
0.41
1W
R8
6.34K
1%
-
D97IN550B
(*) R3 = 2 x 220KΩ
R6 = 0.82Ω/2
R7 = 2 x 499KΩ, 1%
R9 = 2 x 909KΩ
TRANSFORMER
T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT (OREGA 473201A8)
primary 90T of Litz wire 10 x 0.2mm
secondary 7T of #27 AWG (0.15mm)
gap 1.25mm for a total primary inductance of 0.8mH
Figure 8. Typical Application Circuit (80W, Wide-range Mains)
D1 BYT13-600
+
T
C6
Vo=400V
Po=80W
R3 (*)
240K
R2
D3 1N4150
R7 (*)
998K
100
12nF
R1
D2
1N5248B
C3 1µF
BRIDGE
68K
4 x 1N4007
+
-
C1
1µF
400V
FUSE 4A/250V
R9 (*)
1.24M
5
2
1
8
R5
10
MOS
STP8NA50
C5
47µF
450V
7
4
L6561
Vac
(85V to 265V)
3
6
C2
22µF
25V
C7
10nF
R10
10K
NTC
R6 (*)
0.41
1W
R8
6.34K
1%
-
D97IN553B
TRANSFORMER
(*) R3 = 2 x 120KΩ
R6 = 0.82Ω/2
R7 = 2 x 499KΩ, 1%
R9 = 2 x 620KΩ
T: core THOMSON-CSF B1ET2910A (ETD 29 x 16 x 10mm) OR EQUIVALENT (OREGA 473201A8)
primary 90T of Litz wire 10 x 0.2mm
secondary 7T of #27 AWG (0.15mm)
gap 1.25mm for a total primary inductance of 0.8mH
6/13
L6561
Figure 9. Demo Board (EVAL6561-80) Electrical Schematic
NTC
2.5
D1
STTH1L06
T
R4
R5
D8
1N4150
Vo=400V
Po=80W
C5 12 nF
180 k 180 k
R11
R14
100
750 k
R50 12 k
C3 470 nF
D2
R1
R12
750 k
750 k
1N5248B
R6
68 k
BRIDGE
W04M
C1
1 µF
400V
C23
1 µF
+
-
FUSE
4A/250V
R2
750 k
5
2
1
8
3
R7
33
C6
47 µF
MOS
7
L6561
STP8NM50
Vac
(85V to 265V)
450V
4
6
C2
10nF
C29
22 µF
25V
R3
10 k
R16
91 k
R15
220
C4
100 nF
D3 1N4148
R9
R10
0.41
R13
0.41
9.53 k
C7
10 µF
35 V
1W
1W
-
THD REDUCER (optional)
Boost Inductor Spec (ITACOIL E2543/E)
E25x13x7 core, 3C85 ferrite
1.5 mm gap for 0.7 mH primary inductance
Primary: 105 turns 20x0.1 mm
Secondary: 11 turns 0.1mm
Figure 10. EVAL6561-80: PCB and Component Layout (Top view, real size 57x108mm)
Table 6. EVAL6561-80: Evaluation Results.
w/o THD reducer
with THD reducer
Vin (Vac)
Vo (Vdc)
Pin (W)
∆
Vo (Vdc)
Po (W)
η (%)
PF
THD (%)
3.7
PF
THD (%)
2.9
85
87.2
85.2
84.2
83.5
83.1
82.9
400.1
400.1
400.1
400.1
400.1
400.1
14
14
14
14
14
14
80.7
80.7
80.7
80.7
80.7
80.7
92.8
94.7
95.8
96.6
97.1
97.3
0.999
0.996
0.989
0.976
0.940
0.890
0.999
0.996
0.989
0.976
0.941
0.893
110
135
175
220
265
5.0
3.2
6.2
3.7
8.3
4.3
10.7
13.7
5.6
8.1
7/13
L6561
Figure 11. OVP Current Threshold vs.
Temperature
Figure 13. Supply Current vs. Supply
Voltage
D97IN548A
D94IN047A
I
CC
I
OVP
(mA)
(µA)
10
5
41
1
0.5
0.1
0.05
0.01
0.005
0
40
39
38
C
= 1nF
L
f = 70KHz
= 25˚C
T
A
0
5
10
15
20
V
(V)
CC
-50 -25
0
25 50 75 100 125 T (˚C)
Figure 14. Voltage Feedback Input Threshold
vs. Temperature
Figure 12. Undervoltage Lockout Threshold
vs. Temperature
D94IN048A
V
(V)
REF
V
D94IN044A
CC-ON
(V)
13
2.50
12
11
V
CC-OFF
2.48
2.46
(V)
10
9
-25
0
25
50
75
100
125
T (˚C)
-50
0
50
100
T (˚C)
8/13
L6561
Figure 15. Output Saturation Voltage vs. Sink
Current
Figure 17. Multiplier Characteristics
Family
V
V
(pin2)
(V)
PIN7
(V)
V
(pin4)
COMP
D94IN046
D97IN555A
CS
upper voltage
clamp
(V)
V
= 14.5V
1.6
CC
SINK
3.5
5.0
2.0
1.5
1.0
0.5
0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
4.0
3.2
3.0
2.8
2.6
0
100
200
300
400
I
(mA)
GD
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
(pin3) (V)
MULT
Figure 16. Output Saturation Voltage vs.
Source Current
V
PIN7
(V)
D94IN053
V
= 14.5V
CC
V
CC
V
CC
V
CC
V
CC
-0.5
-1.0
-1.5
-2.0
0
SOURCE
0
100
200
300
400
I
(mA)
GD
9/13
L6561
Figure 18. DIP-8 Mechanical Data & Package Dimensions
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN.
TYP. MAX. MIN.
3.32
TYP. MAX.
0.131
A
a1
B
0.51
1.15
0.020
1.65 0.045
0.55 0.014
0.304 0.008
10.92
0.065
0.022
b
0.356
0.204
b1
D
E
0.012
0.430
7.95
9.75 0.313
2.54
0.384
e
0.100
e3
e4
F
7.62
0.300
7.62
0.300
6.6
0.260
I
5.08
0.200
L
3.18
3.81 0.125
1.52
0.150
DIP-8
Z
0.060
10/13
L6561
Figure 19. SO-8 Mechanical Data & Package Dimensions
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN.
TYP. MAX.
0.069
A
A1
A2
B
1.35
0.10
1.10
0.33
0.19
4.80
1.75 0.053
0.25 0.004
1.65 0.043
0.51 0.013
0.25 0.007
5.00 0.189
0.010
0.065
0.020
C
0.010
(1)
D
0.197
E
e
3.80
4.00
0.15
0.157
0.050
1.27
H
5.80
0.25
0.40
6.20 0.228
0.50 0.010
1.27 0.016
0˚ (min.), 8˚ (max.)
0.10
0.244
h
0.020
L
0.050
k
ddd
0.004
Note: (1) Dimensions D does not include mold flash, protru-
sions or gate burrs.
SO-8
Mold flash, potrusions or gate burrs shall not exceed
0.15mm (.006inch) in total (both side).
0016023 C
11/13
L6561
Table 7. Revision History
Date
Revision
Description of Changes
January 2004
June 2004
15
16
First Issue
Modified the Style-look in compliance with the “Corporate Technical
Publications Design Guide”.
Changed input of the power amplifier connected to Multiplier (Fig. 2).
12/13
L6561
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