ST7032 [SITRONIX]
Dot Matrix LCD Controller/Driver; 点阵LCD控制器/驱动器
| 型号： | ST7032 |
| 厂家： | 
SITRONIX TECHNOLOGY CO., LTD. |
| 描述： | Dot Matrix LCD Controller/Driver |
| 文件： | 总63页 (文件大小：1058K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST
Sitronix
ST7032
Dot Matrix LCD Controller/Driver
n Features
l
l
5 x 8 dot matrix possible
Low power operation support:
-- 2.7 to 5.5V
Range of LCD driver power
-- 3.0 to 7.0V
4-bit, 8-bit, serial MPU or 400kbits/s fast
I2C-bus interface are available
80 x 8-bit display RAM (80 characters max.)
10,240-bit character generator ROM for a
total of 256 character fonts(max)
64 x 8-bit character generator RAM(max)
16-common x 80-segment and 1-common x
80-segment ICON liquid crystal display
driver
l
l
Wide range of instruction functions:
Display clear, cursor home, display on/off,
cursor on/off, display character blink, cursor
shift, display shift, double height font
Automatic reset circuit that initializes the
controller/driver after power on and external
reset pin
Internal oscillator(Frequency=540KHz) and
external clock
Built-in voltage booster and follower circuit
(low power consumption )
l
l
l
l
l
l
l
l
l
l
l
Com/Seg direction selectable
Multi-selectable for CGRAM/CGROM size
Instruction compatible to ST7066U and
KS0066U and HD44780
l
16 x 5 –bit ICON RAM(max)
l
Available in COG type
n Description
The ST7032 dot-matrix liquid crystal display controller can
display alphanumeric, Japanese kana characters, and
symbols. It can be configured to drive a dot-matrix liquid
crystal display under the control of a 4 / 8-bit with
6800-series or 8080-series, 3/4-line serial interface
microprocessor. Since all the functions such as display
RAM, character generator ROM/RAM and liquid crystal
driver, required for driving a dot-matrix liquid crystal display
are internally provided on one chip, a minimal system can
be used with this controller/driver.
The ST7032 is suitable for low voltage supply (2.7V to
5.5V) and is perfectly suitable for any portable product
which is driven by the battery and requires low power
consumption.
The ST7032 LCD driver consists of 17 common signal
drivers and 80 segment signal drivers. The maximum
display RAM size can be either 80 characters in 1-line
display or 40 characters in 2-line display. A single ST7032
can display up to one 16-character line or two 16-character
lines.
The ST7032 character generator ROM size is 256 5x8dot
bits which can be used to generate 256 different character
fonts (5x8dot).
The ST7032 dot-matrix LCD driver does not need extra
cascaded drivers.
n Product Number
ST7032 supports various function for customer. Please specify correct product number for application:
For example, “ST7032–0D” the first part is illustrated below and the second part is the identification code of the built-in
character generation ROM. Please refer to the appendix for the character generation ROM code information.
6800-4bit / 8bit, 4-Line interface
(without IIC interface)
ST7032
ST7032i
IIC interface
Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice.
V1.4
2008/08/18
1/61
ST7032
ST7032 Serial Specification Revision History
Version
Date
Description
1. Change “Version 0.1y-Preliminary” to “Version 1.0”
2. Modify Bias resistor value
1.0
1.1
1.2
2003/3/24 3. Modify OSC frequency table
4. Adding Serial interface flow chart & example code
5. Adding “E” connection state for serial interface
2003/8/27 1. Include ST7032i
1. To modify Operating Temperature Range Ta=-30°C to 85°C
2. To modify Storage Temperature Range Ta=-65°C to 150°C
2005/10/17 3. To modify the vlcd voltage Range 3.0v~7.0v
4. To modify the limiting values -0.3v~+6.0v
5. To add Chip Thickness: 480 um
1.2a
1.3
2006/05/23 1. Modify description mistake (Page 1)
1. Add appendix section for Character Generation ROM.
2007/11/09
2. Move ROM table to appendix.
1.4
2008/08/18 Update I/O PAD Circuit
V1.4
2008/08/18
2/61
ST7032
n Pad Dimensions
54
1
152
55
Center on
(2100,185)
(0,0)
Center on
(-2470,-445)
Center on
(2470, -445)
68
139
69
138
35μm
35μm
30μm
30μm
30μm
30μm
30μm
Ø Chip Size: 5130.0 x 1080.0μm
Ø Chip Thickness: 480μm
Ø Bump Pitch : 62μm(min)
Ø Bump Height : 17μm(Typ)
Ø Bump Size :
l
l
Pad No.1~54 : 54 x 97μm
Pad No.55~152 : 40 x 97μm
V1.4
2008/08/18
3/61
ST7032
n Pad Location Coordinates
Pad No. Function
X
Y
Pad No. Function
X
Y
1
XRESET
OSC1
OSC2
RS
2165.5
2089.5
2013.5
1937.5
1861.5
1785.5
1709.5
1633.5
1557.5
1481.5
1405.5
1329.5
1253.5
1177.5
1101.5
1025.5
949.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
EXT
VSS
-874.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
420.5
423
2
-950.5
3
CLS
-1026.5
-1102.5
-1178.5
-1254.5
-1330.5
-1406.5
-1482.5
-1558.5
-1634.5
-1710.5
-1786.5
-1862.5
-2445.5
-2445.5
-2445.5
-2445.5
-2445.5
-2445.5
-2445.5
-2445.5
-2445.5
-2445.5
-2445.5
-2445.5
-2445.5
-2445.5
-2130.5
-2068.5
-2006.5
-1944.5
-1882.5
-1820.5
-1758.5
-1696.5
-1634.5
-1572.5
-1510.5
-1448.5
4
CAP1N
CAP1N
VOUT
VOUT
V0
5
CSB
6
RW
7
E
8
DB0
9
DB1
V0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DB2
V1
DB3
V2
DB4
V3
DB5
V4
DB6
NC
DB7
COM[8]
COM[7]
COM[6]
COM[5]
COM[4]
COM[3]
COM[2]
COM[1]
COMI1
SEG[1]
SEG[2]
SEG[3]
SEG[4]
SEG[5]
SEG[6]
SEG[7]
SEG[8]
SEG[9]
SEG[10]
SEG[11]
SEG[12]
SEG[13]
SEG[14]
SEG[15]
SEG[16]
SEG[17]
VSS
361
VSS
299
VSS
873.5
237
OPF1
OPF2
OPR1
OPR2
SHLC
SHLS
VDD
VDD
VDD
VIN
797.5
175
721.5
113
645.5
51
569.5
-11
493.5
-73
417.5
-135
341.5
-197
265.5
-259
189.5
-321
113.5
-383
VIN
37.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
TEST1
TEST2
VSS
-38.5
-114.5
-190.5
-266.5
-342.5
-418.5
-494.5
-570.5
-646.5
-722.5
-798.5
NC
VOUT
VOUT
PSB
VSS
PSI2B
CAP1P
CAP1P
V1.4
2008/08/18
4/61
ST7032
Pad No. Function
X
Y
Pad No. Function
X
Y
81
82
SEG[18]
SEG[19]
SEG[20]
SEG[21]
SEG[22]
SEG[23]
SEG[24]
SEG[25]
SEG[26]
SEG[27]
SEG[28]
SEG[29]
SEG[30]
SEG[31]
SEG[32]
SEG[33]
SEG[34]
SEG[35]
SEG[36]
SEG[37]
SEG[38]
SEG[39]
SEG[40]
SEG[41]
SEG[42]
SEG[43]
SEG[44]
SEG[45]
SEG[46]
SEG[47]
SEG[48]
SEG[49]
SEG[50]
SEG[51]
SEG[52]
SEG[53]
SEG[54]
SEG[55]
SEG[56]
SEG[57]
-1386.5
-1324.5
-1262.5
-1200.5
-1138.5
-1076.5
-1014.5
-952.5
-890.5
-828.5
-766.5
-704.5
-642.5
-580.5
-518.5
-456.5
-394.5
-332.5
-270.5
-208.5
-146.5
-84.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
SEG[58]
SEG[59]
SEG[60]
SEG[61]
SEG[62]
SEG[63]
SEG[64]
SEG[65]
SEG[66]
SEG[67]
SEG[68]
SEG[69]
SEG[70]
SEG[71]
SEG[72]
SEG[73]
SEG[74]
SEG[75]
SEG[76]
SEG[77]
SEG[78]
SEG[79]
SEG[80]
COM[9]
1093.5
1155.5
1217.5
1279.5
1341.5
1403.5
1465.5
1527.5
1589.5
1651.5
1713.5
1775.5
1837.5
1899.5
1961.5
2023.5
2085.5
2147.5
2445.5
2445.5
2445.5
2445.5
2445.5
2445.5
2445.5
2445.5
2445.5
2445.5
2445.5
2445.5
2445.5
2445.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-420.5
-383
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
-321
-259
-197
-22.5
-135
39.5
-73
101.5
163.5
225.5
287.5
349.5
411.5
473.5
535.5
597.5
659.5
721.5
783.5
845.5
907.5
969.5
1031.5
COM[10]
COM[11]
COM[12]
COM[13]
COM[14]
COM[15]
COM[16]
COMI2
-11
51
113
175
237
299
361
423
V1.4
2008/08/18
5/61
ST7032
n Block Diagram
OSC1 OSC2
CPG
XRESET
CLS
Reset
circuit
Timing
generator
Instruction
register(IR)
Instruction
decoder
Display data
RAM
(DDRAM)
80x8 bits
COM1 to
COM16
16-bit
shift
register
Common
signal
driver
COMI
RS
RW
E
MPU
interface
Address
CSB
counter
(AC)
PSB
PSI2B
SEG1 to
SEG80
80-bit
shift
80-bit
latch
Segment
signal
register
circuit
driver
Data
register
(DR)
DB4 to
DB7
V0~V4
VOUT
LCD drive
voltage
follower
Input/
output
buffer
DB0 to
DB3
Busy
flag
Character
generator RAM
(CGRAM)
VIN
Voltage
booster
circuit
Character
generator ROM
(CGROM)
Cursor
and
blink
SHLC
SHLS
CAP1P
CAP1N
64 bytes
controller
10.240 bits
EXT
ICON RAM
80 bits
OPR1,2
OPF1,2
VSS
Parallel/serial converter
and
attribute circuit
VDD
V1.4
2008/08/18
6/61
ST7032
n Pin Function
Name
Number I/O Interfaced with
Function
External reset pin. Only if the power on reset used, the
XRESET pin must be fixed to VDD.
XRESET
1
I
MPU
Low active.
Select registers.
0: Instruction register (for write)
Busy flag & address counter (for read)
1: Data register (for write and read)
RS
1
I
MPU
Select read or write (In parallel mode).
0: Write
1: Read
R/W
E
1
1
1
I
I
I
MPU
MPU
MPU
Starts data read/write. (“E” must connect to “VDD” when
serial interface is selected.)
Chip select in parallel mode and serial interface (Low
active).When the CSB in falling edge state (in serial
interface), the shift register and the clock counter are reset.
Four high order bi-directional data bus pins. Used for data
transfer and receive between the MPU and the ST7032.
DB7 can be used as a busy flag. In serial interface mode
DB7 is SI (input data), DB6 is SCL (serial clock).
In I2C interface DB7 (SDA) is input data and DB6 (SCL) is
clock input.
CSB
DB4 to DB7
4
I/O
MPU
SDA and SCL must connect to I2C bus (I2C bus is to connect
a resister between SDA/SCL and the power of I2C bus ).
Four low order bi-directional data bus pins. Used for data
transfer and receive between the MPU and the ST7032.
These pins are not used during 4-bit operation.
Extension instruction select:
DB0 to DB3
4
1
I/O
I
MPU
0:enable extension instruction(add contrast/ICON/double
height font/ extension instruction)
Ext
ITO option
1:disable extension instruction(compatible to ST7066U, but
without 5x11dot font)
Interface selection
0:serial mode
(“E” must connect to “VDD” when serial mode is selected.)
1:parallel mode(4/8 bit)
PSB
1
1
I
I
MPU
In I2C interface PSB must connect to VDD
PSB
PSI2B
Interface
No use
0
0
1
1
0
1
0
1
PSI2B
ITO option
SI4
SI2 (I2C )
Parallel 68
Character generator select:
OPR1
OPR2
CGROM
240
CGRAM
0
0
1
1
0
1
0
1
8
6
8
0
OPR1,
OPR2
2
I
ITO option
250
248
256
V1.4
2008/08/18
7/61
ST7032
Name
Number I/O Interfaced with
Function
Common signals direction select:
SHLC
1
I
ITO option
ITO option
LCD
0:Com1~16←Row address 15~0(Invert)
1:Com1~16←Row address 0~15(Normal)
Segment signals direction select:
SHLS
1
I
0:Seg1~80←Column address 79~0(Invert)
1:Seg1~80←Column address 0~79(Normal)
Common signals that are not used are changed to
non-selection waveform. COM9 to COM16
are non-selection waveforms at 1/8 or 1/9 duty factor
ICON common signals
COM1 to
COM16
16
O
COMI
SEG1 to
SEG80
2
O
O
LCD
LCD
80
Segment signals
The built-in voltage follower circuit selection
OPF1 OPF2
Bias select
OPF1
OPF2
0
0
1
1
0
1
0
1
Built-in voltage follower(only use at EXT=0)
Built-in bias resistor(3.3KΩ) ±30%
Built-in bias resistor(9.6KΩ) ±30%
External bias resistor select
2
1
I
ITO option
For voltage booster circuit(VDD-VSS)
External capacitor about 0.1u~4.7uf
CAP1P
-
Power supply
CAP1N
VIN
1
1
-
-
Power supply
Power supply
Input the voltage to booster
DC/DC voltage converter. Connect a capacitor between this
terminal and VIN when the built-in booster is used.
Power supply for LCD drive
VOUT
1
5
2
-
-
-
I
Power supply
Power supply
Power supply
ITO option
V0 to V4
V0-Vss = 7V (Max)
Built-in/external Voltage follower circuit
VDD: 2.7V to 5.5V, VSS: 0V
VDD
VSS
Internal/External oscillation select
0:external clock
CLS
1:internal oscillation
OSC1
OSC2
When the pin input is an external clock, it must be input to
OSC1.
2
2
I/O
I/O
Oscillation
Test pin
TEST1,2
TEST1,2 must connect to VDD.
V1.4
2008/08/18
8/61
ST7032
n EXT option pin difference table
ST7066U normal mode (EXT=1)
Extension mode (EXT=0)
Booster
Always OFF
ON/OFF control by instruction
Can’t use the follower circuit
Bias (V0~V4)
Only use external resistor or internal resistor(1/5 Follower or internal/external resistor selectable
bias)
1. Control by instruction with follower
Contrast adjust
Control by external VR
2. Control by external VR with internal/external
resistor
ICON RAM
Can’t be use
RAM size has 80 bit width (S1~S80).
Control extension instruction for low power
consumption.
Instruction
Control normal instruction similar to ST7066U.
Only 5x8 font
Double height font
Can set 5x8 or 5x16 font
OSC frequency adjust Only adjust by external clock.
Can set OSC frequency by instruction set.
V1.4
2008/08/18
9/61
ST7032
n Function Description
l
System Interface
This chip has all four kinds of interface type with MPU: 4-bit bus, 8-bit bus, serial and fast I2C interface. 4-bit bus
or 8-bit bus is selected by DL bit in the instruction register.
During read or write operation, two 8-bit registers are used. One is data register (DR); the other is instruction
register (IR).
The data register (DR) is used as temporary data storage place for being written into or read from
DDRAM/CGRAM/ICON RAM, target RAM is selected by RAM address setting instruction. Each internal
operation, reading from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the
data in the next DDRAM/CGRAM/ICON RAM address is transferred into DR automatically. Also after MPU writes
data to DR, the data in DR is transferred into DDRAM/CGRAM/ICON RAM automatically.
The Instruction register (IR) is used only to store instruction code transferred from MPU. MPU cannot use it to
read instruction data.
Using RS input pin to select command or data in 4-bit/8-bit bus mode.
RS R/W
Operation
InstructionWriteoperation(MPUwritesInstructioncode
L
L
into IR)
L
H
H
H
L
H
Read Busy Flag(DB7) and address counter (DB0 ~ DB6)
Data Write operation (MPU writes data into DR)
Data Read operation (MPU reads data from DR)
Table 1. Various kinds of operations according to RS and R/W bits.
I2C interface
It just only could write Data or Instruction to ST7032 by the IIC Interface.
It could not read Data or Instruction from ST7032 (except Acknowledge signal).
SCL: serial clock input
SDA: serial data input
Slaver address could only set to 0111110, no other slaver address could be set
The I2C interface send RAM data and executes the commands sent via the I2C Interface. It could send data bit to the RAM.
The I2C Interface is two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA)
and a Serial Clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be
initiated only when the bus is not busy.
BIT TRANSFER
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of
the clock pulse because changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated
in Fig.1.
START AND STOP CONDITIONS
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock
is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined
as the STOP condition (P). The START and STOP conditions are illustrated in Fig.2.
SYSTEM CONFIGURATION
The system configuration is illustrated in Fig.3.
· Transmitter: the device, which sends the data to the bus
· Master: the device, which initiates a transfer, generates clock signals and terminates a transfer
· Slave: the device addressed by a master
V1.4
2008/08/18
10/61
ST7032
· Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message
· Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to
do so and the message is not corrupted
· Synchronization: procedure to synchronize the clock signals of two or more devices.
ACKNOWLEDGE
Acknowledge is not Busy Flag in I2C interface.
Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the
transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is
addressed must generate an acknowledge after the reception of each byte. A master receiver must also generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that
acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master
receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been
clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP
condition. Acknowledgement on the I2C Interface is illustrated in Fig.4.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 1. Bit transfer
SDA
SCL
S
P
START con dition
STOP con dition
Figure 2. Definition of START and STOP conditions
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER (1)
0111100
SLAVE
RECEIVER (2)
0111101
SLAVE
RECEIVER (3)
0111110
SLAVE
RECEIVER (4)
0111111
SDA
SCL
Figure 3. System configuration
V1.4
2008/08/18
11/61
ST7032
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
8
SCL FROM
MASTER
2
1
9
S
clock pulse for
START
acknowledge ment
condition
Figure 4. Acknowledgement on the 2-line Interface
I2C Interface protocol
The ST7032 supports command, data write addressed slaves on the bus.
Before any data is transmitted on the I2C Interface, the device, which should respond, is addressed first. Only one 7-bit
slave addresses (0111110) is reserved for the ST7032. The R/W is assigned to 0 for Write only.
The I2C Interface protocol is illustrated in Fig.5.
The sequence is initiated with a START condition (S) from the I2C Interface master, which is followed by the slave address.
All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I2C Interface transfer. After
acknowledgement, one or more command words follow which define the status of the addressed slaves.
A command word consists of a control byte, which defines Co and RS, plus a data byte.
The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a
cleared Co bit, only data bytes will follow. The state of the RS bit defines whether the data byte is interpreted as a command
or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte,
depending on the RS bit setting; either a series of display data bytes or command data bytes may follow. If the RS bit is set
to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is
automatically updated and the data is directed to the intended ST7032i device. If the RS bit of the last control byte is set to
logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received
commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the I2C
INTERFACE-bus master issues a STOP condition (P).
V1.4
2008/08/18
12/61
ST7032
Write mode
acknowledgement
from ST7032i
acknowledgement
from ST7032i
acknowledgement
from ST7032i
acknowledgement
from ST7032i
acknowledgement
from ST7032i
R
S
R
S
control byte
data byte
control byte
data byte
S
0
1
1
1
1
0
A 1
A
A 0
A
A P
1
0
n>=0bytes
MSB.......................LSB
R/W
slave address
1 byte
2n>=0bytes
command word
Co
Co
R
/
W
R
Co
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0
1
1
1
1
1
0
0
0
0
0
0
0
S
slave address
control byte
data byte
Figure 5. 2-line Interface protocol
Last control byte to be sent. Only a stream of data bytes is allowed to follow.
This stream may only be terminated by a STOP condition.
Another control byte will follow the data byte unless a STOP condition is received.
0
1
Co
During write operation, two 8-bit registers are used. One is data register (DR), the other is instruction register
(IR).
The data register (DR) is used as temporary data storage place for being written into DDRAM/CGRAM/ICON
RAM, target RAM is selected by RAM address setting instruction. Each internal operation, writing into RAM, is
done automatically. So to speak, after MPU writes data to DR, the data in DR is transferred into
DDRAM/CGRAM/ICON RAM automatically.
The Instruction register (IR) is used only to store instruction code transferred from MPU. MPU cannot use it to
read instruction data.
To select register, use RS input in I2C interface.
RS R/W
Operation
InstructionWriteoperation(MPUwritesInstructioncode
L
H
L
L
into IR)
Data Write operation (MPU writes data into DR)
Table 2. Various kinds of operations according to RS and R/W bits.
l
Busy Flag (BF)
When BF = "High”, it indicates that the internal operation is being processed. So during this time the next
instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation),
through DB7 port. Before executing the next instruction, be sure that BF is not High.
l
Address Counter (AC)
Address Counter (AC) stores DDRAM/CGRAM/ICON RAM address, transferred from IR.
After writing into (reading from) DDRAM/CGRAM/ICON RAM, AC is automatically increased (decreased) by 1.
When RS = "Low" and R/W = "High", AC can be read through DB0 ~ DB6 ports.
V1.4
2008/08/18
13/61
ST7032
l
Display Data RAM (DDRAM)
Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended capacity is 80
x 8 bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used as
general data RAM. See Figure 7 for the relationships between DDRAM addresses and positions on the liquid
crystal display.
The DDRAM address (ADD ) is set in the address counter (AC)as hexadecimal.
Ø
1-line display (N = 0) (Figure 8)
When there are fewer than 80 display characters, the display begins at the head position. For example, if
using only the ST7032, 16 characters are displayed. See Figure 8.
When the display shift operation is performed, the DDRAM address shifts. See Figure 9.
High order bits
Low order bits
Example : DDRAM Address 4F
AC6 AC5 AC4 AC3 AC2 AC1 AC0
1
0
0
1
1
1
1
Figure 7. DDRAM Address
Display Position (digit)
1
2
3
4
5
6
78 79 80
DDRAM Address 00 01 02 03 04 05 ........ 4D 4E 4F
Figure 8. 1-Line Display
Display Position
1
2
3
4
16
0F
DDRAM Address
00 01 02 03
....
For Shift Left
01 02 03 04
4F 00 01 02
....
....
10
0E
For Shift Right
Figure 9. 1-Line by 16-Character Display Example
V1.4
2008/08/18
14/61
ST7032
Ø
2-line display (N = 1) (Figure 10)
Case 1: When the number of display characters is less than 40 2 lines, the two lines are displayed from the
head. Note that the first line end address and the second line start address are not consecutive. See Figure
10.
Display Position
1
2
3
4
5
6
38 39 40
00 01 02 03 04 05 ........ 25 26 27
DDRAM Address
(hexadecimal)
40 41 42 43 44 45 ........ 65 66 67
Figure 10. 2-Line Display
Case 2: For a 16-character
2-line display See Figure 11.
When display shift operation is performed, the DDRAM address shifts. See Figure 11.
Display
Position
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
DDRAM
Address
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50
For Shift
Left
27 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E
67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E
For Shift
Right
Figure 11. 2-Line by 16-Character Display Example
V1.4
2008/08/18
15/61
ST7032
l
Character Generator ROM (CGROM)
The character generator ROM generates 5 x 8 dot character patterns from 8-bit character codes. It can generate
240/250/248/256 5 x 8 dot character patterns (select by OPR1/2 ITO pin). User-defined character patterns are
also available by mask-programmed ROM.
l
Character Generator RAM (CGRAM)
In the character generator RAM, the user can rewrite character patterns by program. For 5 x 8 dots, eight
character patterns can be written.
Write into DDRAM the character codes at the addresses shown as the left column of code table (refer to
appendix) to show the character patterns stored in CGRAM.
See Table 4 for the relationship between CGRAM addresses and data and display patterns. Areas that are not
used for display can be used as general data RAM.
l
ICON RAM
In the ICON RAM, the user can rewrite icon pattern by program.
There are totally 80 dots for icon can be written.
See Table 5 for the relationship between ICON RAM address and data and the display patterns.
l
Timing Generation Circuit
The timing generation circuit generates timing signals for the operation of internal circuits such as
DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU
access are generated separately to avoid interfering with each other. Therefore, when writing data to
DDRAM, for example, there will be no undesirable interference, such as flickering, in areas other than
the display area.(In I2C interface the reading function is invalid.)
l
LCD Driver Circuit
LCD Driver circuit has 17 common and 80 segment signals for LCD driving. Data from CGRAM/CGROM/ICON
is transferred to 80 bit segment latch serially, and then it is stored to 80 bit shift latch. When each common is
selected by 17 bit common register, segment data also output through segment driver from 80 bit segment latch.
l
Cursor/Blink Control Circuit
It can generate the cursor or blink in the cursor/blink control circuit. The cursor or the blink appears in the digit at
the display data RAM address set in the address counter.
V1.4
2008/08/18
16/61
ST7032
Character Code
(DDRAM Data)
CGRAM
Address
Character Patterns
(CGRAM Data)
b7 b6 b5 b4 b3 b2 b1 b0 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
1
1
1
1
1
1
0
1
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
-
0
0
0
-
-
-
0
0
0
0
-
0
0
1
-
-
-
Table 4. Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character
patterns (CGRAM Data)
Notes:
1.
2.
Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types).
CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position
and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding to the
cursor display position, at 0 as the cursor display. If the 8th line data is 1, 1 bit will light up the 8th line
regardless of the cursor presence.
3.
4.
Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left).
As shown Table 4, CGRAM character patterns are selected when character code bits 4 to 7 are all 0.
However, since character code bit 3 has no effect, the R display example above can be selected by either
character code 00H or 08H.
5.
6.
“1” for CGRAM data corresponds to display selection and “0” to non-selection,“-“ Indicates no effect.
Different OPR1/2 ITO option can select different CGRAM size.
V1.4
2008/08/18
17/61
ST7032
When SHLS=1, ICON RAM map refer below table
ICON RAM bits
ICON address
D7
-
D6
-
D5
-
D4
D3
D2
D1
D0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
S1
S2
S3
S4
S5
-
-
-
S6
S7
S8
S9
S10
S15
S20
S25
S30
S35
S40
S45
S50
S55
S60
S65
S70
S75
S80
-
-
-
S11
S16
S21
S26
S31
S36
S41
S46
S51
S56
S61
S66
S71
S76
S12
S17
S22
S27
S32
S37
S42
S47
S52
S57
S62
S67
S72
S77
S13
S18
S23
S28
S33
S38
S43
S48
S53
S58
S63
S68
S73
S78
S14
S19
S24
S29
S34
S39
S44
S49
S54
S59
S64
S69
S74
S79
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
When SHLS=0, ICON RAM map refer below table
ICON address
ICON RAM bits
D7
D6
D5
D4
D3
D2
D1
D0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
-
-
-
S80
S75
S70
S65
S60
S55
S50
S45
S40
S35
S30
S25
S20
S15
S10
S5
S79
S74
S69
S64
S59
S54
S49
S44
S39
S34
S29
S24
S19
S14
S9
S78
S73
S68
S63
S58
S53
S48
S43
S38
S33
S28
S23
S18
S13
S8
S77
S72
S67
S62
S57
S52
S47
S42
S37
S32
S27
S22
S17
S12
S7
S76
S71
S66
S61
S56
S51
S46
S41
S36
S31
S26
S21
S16
S11
S6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
S4
S3
S2
S1
Table 5. ICON RAM map
When ICON RAM data is filled the corresponding position displayed is described as the following table.
V1.4
2008/08/18
18/61
ST7032
n Instructions
There are four categories of instructions that:
l
l
l
l
Designate ST7032 functions, such as display format, data length, etc.
Set internal RAM addresses
Perform data transfer with internal RAM
Others
Ø
instruction table at “Normal mode”
(When “EXT” option pin connect to VDD, the instruction set follow below table)
Instruction
Execution Time
OSC= OSC= OSC=
380KHz 540kHz 700KHz
Instruction Code
Instruction
Clear Display
Return Home
Description
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Write "20H" to DDRAM. and set
DDRAM address to "00H" from AC
Set DDRAM address to "00H" from
AC and return cursor to its original
position if shifted. The contents of
DDRAM are not changed.
Sets cursor move direction and
specifies display shift. These
operations are performed during
data write and read.
1.08
ms
0.76
ms
0.59
ms
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
x
1.08
ms
0.76
ms
0.59
ms
Entry Mode
Set
26.3 us 18.5 us 14.3 us
26.3 us 18.5 us 14.3 us
26.3 us 18.5 us 14.3 us
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
I/D
C
S
B
D=1:entire display on
C=1:cursor on
B=1:cursor position on
Display
ON/OFF
D
S/C and R/L:
Cursor or
Display Shift
Set cursor moving and display shift
control bit, and the direction, without
changing DDRAM data.
0
1
1
S/C R/L
x
x
x
x
DL: interface data is 8/4 bits
N: number of line is 2/1
26.3 us 18.5 us 14.3 us
26.3 us 18.5 us 14.3 us
26.3 us 18.5 us 14.3 us
Function Set
Set CGRAM
0
0
0
0
0
0
0
0
1
0
1
DL
N
x
Set CGRAM address in address
counter
AC5 AC4 AC3 AC2 AC1 AC0
Set DDRAM
address
Set DDRAM address in address
counter
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Whether during internal operation or
not can be known by reading BF.
The contents of address counter
can also be read.
Read Busy
flag and
address
0
0
0
0
1
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
Write data
to RAM
Read data
from RAM
Write data into internal RAM
(DDRAM/CGRAM)
26.3 us 18.5 us 14.3 us
26.3 us 18.5 us 14.3 us
1
1
0
1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Read data from internal RAM
(DDRAM/CGRAM)
Note:
Be sure the ST7032 is not in the busy state (BF = 0) before sending an instruction from the MPU to the ST7032.
If an instruction is sent without checking the busy flag, the time between the first instruction and next instruction
will take much longer than the instruction time itself. Refer to Instruction Table for the list of each instruction
execution time.
V1.4
2008/08/18
19/61
ST7032
Ø instruction table at “Extension mode”
(when “EXT” option pin connect to VSS, the instruction set follow below table)
Instruction
Execution Time
OSC= OSC= OSC=
380KHz 540kHz 700KHz
Instruction Code
Instruction
Description
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Clear
Write "20H" to DDRAM. and set
DDRAM address to "00H" from AC
Set DDRAM address to "00H" from
AC and return cursor to its original
position if shifted. The contents of
DDRAM are not changed.
Sets cursor move direction and
specifies display shift. These
operations are performed during
data write and read.
1.08
ms
0.76
ms
0.59
ms
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
x
Display
Return
Home
1.08
ms
0.76
ms
0.59
ms
Entry Mode
Set
26.3 us 18.5 us 14.3 us
26.3 us 18.5 us 14.3 us
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
I/D
C
S
B
D=1:entire display on
C=1:cursor on
B=1:cursor position on
Display
ON/OFF
D
DL: interface data is 8/4 bits
N: number of line is 2/1
DH: double height font
26.3 us 18.5 us 14.3 us
26.3 us 18.5 us 14.3 us
Function Set
0
0
0
0
0
1
0
1
DL
N
DH *0 IS
IS: instruction table select
Set DDRAM
address
Set DDRAM address in address
counter
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Whether during internal operation or
not can be known by reading BF.
The contents of address counter
can also be read.
Read Busy
flag and
address
0
0
0
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
Write data
to RAM
Read data
from RAM
Write data into internal RAM
(DDRAM/CGRAM/ICONRAM)
Read data from internal RAM
(DDRAM/CGRAM/ICONRAM)
26.3 us 18.5 us 14.3 us
26.3 us 18.5 us 14.3 us
1
1
0
1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Note * : this bit is for test command , and must always set to “0”
Instruction table 0(IS=0)
S/C and R/L:
Cursor or
Set cursor moving and display shift
control bit, and the direction, without
changing DDRAM data.
Set CGRAM address in address
counter
26.3 us 18.5 us 14.3 us
26.3 us 18.5 us 14.3 us
0
0
0
0
0
0
0
1
0
1
S/C R/L
x
x
Display Shift
Set CGRAM
AC5 AC4 AC3 AC2 AC1 AC0
Instruction table 1(IS=1)
BS=1:1/4 bias
Internal OSC
frequency
BS=0:1/5 bias
0
0
0
0
0
0
26.3 us 18.5 us 14.3 us
26.3 us 18.5 us 14.3 us
26.3 us 18.5 us 14.3 us
0
0
0
0
1
1
0
0
0
1
0
1
BS F2 F1 F0
AC3 AC2 AC1 AC0
Ion Bon C5 C4
F2~0: adjust internal OSC
frequency for FR frequency.
Set ICON address in address
counter.
Set ICON
address
Ion: ICON display on/off
Bon: set booster circuit on/off
C5,C4: Contrast set for internal
follower mode.
Power/ICON
control/Contr
ast set
Fon: set follower circuit on/off
Rab2~0:
select follower amplified ratio.
Contrast set for internal follower
mode.
Follower
control
Rab Rab Rab
Fon
0
0
0
0
26.3 us 18.5 us 14.3 us
26.3 us 18.5 us 14.3 us
0
0
1
1
1
1
0
1
2
1
0
Contrast set
C3 C2 C1 C0
V1.4
2008/08/18
20/61
ST7032
n Instruction Description
l
Clear Display
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
1
Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to
"00H" into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge
on first line of the display. Make entry mode increment (I/D = "1").
l
Return Home
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
1
X
Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter.
Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM do not
change.
l
Entry Mode Set
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
I/D
0
0
0
0
0
0
0
1
S
Set the moving direction of cursor and display.
I/D : Increment / decrement of DDRAM address (cursor or blink)
Ø
Ø
When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1.
When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1.
* CGRAM operates the same as DDRAM, when read from or write to CGRAM.
S: Shift of entire display
When DDRAM read (CGRAM read/write) operation or S = "Low", shift of entire display is not performed. If
S = "High" and DDRAM write operation, shift of entire display is performed according to I/D value (I/D = "1":
shift left, I/D = "0" : shift right).
S
H
H
I/D
H
Description
Shift the display to the left
Shift the display to the right
L
V1.4
2008/08/18
21/61
ST7032
l
Display ON/OFF
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
1
D
C
B
Control display/cursor/blink ON/OFF 1 bit register.
Ø
Ø
Ø
D : Display ON/OFF control bit
When D = "High", entire display is turned on.
When D = "Low", display is turned off, but display data is remained in DDRAM.
C : Cursor ON/OFF control bit
When C = "High", cursor is turned on.
When C = "Low", cursor is disappeared in current display, but I/D register remains its data.
B : Cursor Blink ON/OFF control bit
When B = "High", cursor blink is on, that performs alternate between all the high data and display
character at the cursor position.
When B = "Low", blink is off.
Alternating
display
Every
64 frames
Cursor
l
Cursor or Display Shift
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
S/C R/L
0
0
0
0
0
1
X
X
Ø
Ø
S/C: Screen/Cursor select bit
When S/C=”High”, Screen is controlled by R/L bit.
When S/C=”Low”, Cursor is controlled by R/L bit.
R/L: Right/Left
When R/L=”High”, set direction to right.
When R/L=”Low”, set direction to left.
Without writing or reading of display data, shift right/left cursor position or display. This instruction is used to
correct or search display data. During 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st
line. Note that display shift is performed simultaneously in all the line. When displayed data is shifted
repeatedly, each line shifted individually. When display shift is performed, the contents of address counter are
not changed.
S/C
L
R/L
L
Description
AC Value
AC=AC-1
AC=AC+1
AC=AC
Shift cursor to the left
L
H
Shift cursor to the right
H
L
Shift display to the left. Cursor follows the display shift
H
H
Shift display to the right. Cursor follows the display shift AC=AC
V1.4
2008/08/18
22/61
ST7032
l
Function Set
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DL DH IS
0
0
0
0
1
N
0
Ø
DL : Interface data length control bit
When DL = "High", it means 8-bit bus mode with MPU.
When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit
bus mode.
When in 4-bit bus mode, it needs to transfer 4-bit data by two times.
Ø
Ø
N : Display line number control bit
When N = "High", 2-line display mode is set.
When N = "Low", it means 1-line display mode.
DH : Double height font type control bit
When DH = " High " and N= “Low”, display font is selected to double height mode(5x16 dot),RAM address
can only use 00H~27H.
When DH= “High” and N= “High”, it is forbidden.
When DH = " Low ", display font is normal (5x8 dot).
EXT option pin connect to high EXT option pin connect to low
Display Lines Character Font Display Lines Character Font
N
DH
L
L
L
H
L
1
1
2
2
5x8
5x8
5x8
5x8
1
1
2
5x8
5x16
5x8
H
H
H
Forbidden
2 line mode normal display (DH=0/N=1)
1 line mode with double height font (DH=1/N=0)
Ø
IS : normal/extension instruction select
When IS=” High”, extension instruction be selected (refer extension instruction table)
When IS=” Low”, normal instruction be selected (refer normal instruction table)
V1.4
2008/08/18
23/61
ST7032
l
Set CGRAM Address
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
AC5 AC4 AC3 AC2 AC1 AC0
0
0
0
1
Set CGRAM address to AC.
This instruction makes CGRAM data available from MPU.
l
Set DDRAM Address
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
AC6 AC5 AC4 AC3 AC2 AC1 AC0
0
0
1
Set DDRAM address to AC.
This instruction makes DDRAM data available from MPU.
When 1-line display mode (N = 0), DDRAM address is from "00H" to "4FH".
In 2-line display mode (N = 1), DDRAM address in the 1st line is from "00H" to "27H", and
DDRAM address in the 2nd line is from "40H" to "67H".
l
Read Busy Flag and Address
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
0
1
When BF = “High”, indicates that the internal operation is being processed. So during this time the next
instruction cannot be accepted.
The address Counter (AC) stores DDRAM/CGRAM addresses, transferred from IR.
After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1.
V1.4
2008/08/18
24/61
ST7032
l
Write Data to CGRAM,DDRAM or ICON RAM
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
Write binary 8-bit data to CGRAM, DDRAM or ICON RAM
The selection of RAM from DDRAM, CGRAM or ICON RAM, is set by the previous address set instruction
: DDRAM address set, CGRAM address set, ICON RAM address set. RAM set instruction can also determine
the AC direction to RAM.
After write operation, the address is automatically increased/decreased by 1, according to the entry mode.
l
Read Data from CGRAM,DDRAM or ICON RAM
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D7 D6 D5 D4 D3 D2 D1 D0
1
1
Read binary 8-bit data from DDRAM/CGRAM/ICON RAM
The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not
performed before this instruction, the data that read first is invalid, because the direction of AC is not
determined. If you read RAM data several times without RAM address set instruction before read operation,
you can get correct RAM data from the second, but the first data would be incorrect, because there is no time
margin to transfer RAM data.
※Read data must be “set address” before this instruction.
V1.4
2008/08/18
25/61
ST7032
l
Bias selection/Internal OSC frequency adjust
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
BS F2 F1 F0
0
0
0
0
0
1
Ø
Ø
BS: bias selection
When BS=”High”, the bias will be 1/4
When BS=”Low”, the bias will be 1/5
BS will be invalid when external bias resistors are used (OPF1=1, OPF2=1)
F2,F1,F0 : Internal OSC frequency adjust
When CLS connect to high, that instruction can adjust OSC and Frame frequency.
Frame frequency ( Hz )
(2 line mode)
400
350
300
250
200
150
100
50
Internal frequency adjust
F2
0
F1
0
F0
0
VDD = 3.0 V
VDD = 5.0 V
120
122
131
144
161
183
221
274
347
0
0
1
133
0
1
0
149
0
1
1
167
1
0
0
192
1
0
1
227
0
1
1
0
277
0
1
2
3
4
5
6
7
1
1
1
347
Instruction Step
l
Set ICON RAM address
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
AC3 AC2 AC1 AC0
0
0
0
1
0
0
Set ICON RAM address to AC.
This instruction makes ICON data available from MPU.
When IS=1 at Extension mode,
The ICON RAM address is from "00H" to "0FH".
l
Power/ICON control/Contrast set(high byte)
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
0
1
I
ON
BON C5 C4
Ø
Ø
Ion: set ICON display on/off
When Ion = "High", ICON display on.
When Ion = "Low", ICON display off.
Bon: switch booster circuit
Bon can only be set when internal follower is used (OPF1=0, OPF2=0).
When Bon = "High", booster circuit is turn on.
When Bon = "Low", booster circuit is turn off.
C5,C4 : Contrast set(high byte)
Ø
C5,C4,C3,C2,C1,C0 can only be set when internal follower is used (OPF1=0,OPF2=0).They can more
precisely adjust the input reference voltage of V0 generator. The details please refer to the supply voltage
for LCD driver.
V1.4
2008/08/18
26/61
ST7032
l
Follower control
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Rab Rab Rab
0
0
0
1
1
0
F
ON
2
1
0
Ø
Fon: switch follower circuit
Fon can only be set when internal follower is used (OPF1=0,OPF2=0).
When Fon = "High", internal follower circuit is turn on.
When Fon = "Low", internal follower circuit is turn off.
Ø
Rab2,Rab1,Rab0 : V0 generator amplified ratio
Rab2,Rab1,Rab0 can only be set when internal follower is used (OPF1=0,OPF2=0).They can adjust the
amplified ratio of V0 generator. The details please refer to the supply voltage for LCD driver.
l
Contrast set(low byte)
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C3 C2 C1 C0
0
0
0
1
1
1
Ø
C3,C2,C1,C0:Contrast set(low byte)
C5,C4,C3,C2,C1,C0 can only be set when internal follower is used (OPF1=0,OPF2=0).They can more
precisely adjust the input reference voltage of V0 generator. The details please refer to the supply voltage
for LCD driver.
V1.4
2008/08/18
27/61
ST7032
n Reset Function
Initializing by Internal Reset Circuit
An internal reset circuit automatically initializes the ST7032 when the power is turned on. The following
instructions are executed during the initialization. The busy flag (BF) is kept in the busy state (BF = 1) until the
initialization ends. The busy state lasts for 40 ms after VDD rises to stable.
1.
2.
Display clear
Function set:
DL = 1; 8-bit interface data
N = 0; 1-line display
DH=0; normal 5x8 font
IS=0; use instruction table 0
Display on/off control:
D = 0; Display off
3.
4.
C = 0; Cursor off
B = 0; Blinking off
Entry mode set:
I/D = 1; Increment by 1
S = 0; No shift
5.
6.
7.
Internal OSC frequency
(F2,F1,F0)=(1,0,0)
ICON control
Ion=0; ICON off
Power control
BS=0; 1/5bias
Bon=0; booster off
Fon=0; follower off
(C5,C4,C3,C2,C1,C0)=(1,0,0,0,0,0)
(Rab2,Rab1,Rab0)=(0,1,0)
Note:
If the electrical characteristics conditions listed under the table Power Supply Conditions Using
Internal Reset Circuit are not met, the internal reset circuit will not operate normally and will fail to initialize the
ST7032.
When internal Reset Circuit not operate, ST7032 can be reset by XRESET pin from MPU control signal.
V1.4
2008/08/18
28/61
ST7032
n Initializing by Instruction
l
8-bit Interface (fosc=380KHz)
POWER ON and external reset
Wait time >40mS
After VDD stable
Function set
BF cannot be
checked before
this instruction.
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
N
DH
X
IS
Wait time >26.3μS
Function set
BF cannot be
checked before
this instruction.
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
N
DH
X
IS
Wait time >26.3μS
Internal OSC frequency
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
BS F2 F1 F0
0
0
0
0
0
1
Wait time >26.3μS
Contrast Set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
1
1
C3
C2
C1
C0
Wait time >26.3μS
Power/ICON/Contrast control
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Bon
C5
C4
0
0
0
1
0
1
Ion
Wait time >26.3μS
Follower control
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Rab2 Rab1 Rab0
0
0
0
1
1
0
Fon
Wait time >200mS
(for power stable)
Display ON/OFF control
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
1
D
C
B
Wait time >26.3μS
Initialization end
V1.4
2008/08/18
29/61
ST7032
Ø
Initial Program Code Example For 8051 MPU(8 Bit Interface):
;---------------------------------------------------------------------------------
INITIAL_START:
CALL HARDWARE_RESET
CALL DELAY40mS
MOV A,#38H
;FUNCTION SET
CALL WRINS_NOCHK ;8 bit,N=1,5*7dot
CALL DELAY30uS
MOV A,#39H
;FUNCTION SET
CALL WRINS_NOCHK ;8 bit,N=1,5*7dot,IS=1
CALL DELAY30uS
MOV A,#14H
;Internal OSC frequency adjustment
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#78H
; Contrast control
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#5EH
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#6AH
;Power/ICON/Contrast control
;Follower control
CALL WRINS_CHK
CALL DELAY200mS
MOV A,#0CH
;for power stable
;DISPLAY ON
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#01H
;CLEAR DISPLAY
CALL WRINS_CHK
CALL DELAY2mS
MOV A,#06H
;ENTRY MODE SET
CALL WRINS_CHK
CALL DELAY30uS
;CURSOR MOVES TO RIGHT
;---------------------------------------------------------------------------------
MAIN_START:
XXXX
XXXX
XXXX
XXXX
;---------------------------------------------------------------------------------
WRINS_CHK:
CALL CHK_BUSY
WRINS_NOCHK:
CLR
CLR
SETB
RS
RW
E
;EX:Port 3.0
;EX:Port 3.1
;EX:Port 3.2
MOV P1,A
CLR
;EX:Port 1=Data Bus
E
MOV P1,#FFH
RET
;For Check Busy Flag
;---------------------------------------------------------------------------------
CHK_BUSY:
CLR
;Check Busy Flag
RS
SETB RW
SETB
JB
CLR
RET
E
P1.7,$
E
V1.4
2008/08/18
30/61
ST7032
l
4-bit Interface (fosc=380KHz)
V1.4
2008/08/18
31/61
ST7032
Ø
Initial Program Code Example For 8051 MPU(4 Bit Interface):
;-------------------------------------------------------------------
INITIAL_START:
.
.
CALL HARDWARE_RESET
CALL DELAY40mS
.
.
MOV A,#38H
CALL WRINS_ONCE ;8 bit, 5*7 dot
CALL DELAY2mS
;FUNCTION SET
;-------------------------------------------------------------------
WRINS_CHK:
CALL CHK_BUSY
WRINS_NOCHK:
MOV A,#38H
;FUNCTION SET
PUSH
A
CALL WRINS_ONCE
CALL DELAY30uS
;8 bit, 5*7 dot
ANL A,#F0H
CLR RS
;EX:Port 3.0
CLR RW
;EX:Port 3.1
MOV A,#38H
CALL WRINS_ONCE
CALL DELAY30uS
;FUNCTION SET
;8 bit, 5*7 dot
SETB
MOV P1,A
CLR
POP
E
;EX:Port 3.2
;EX:Port1=Data Bus
E
A
CALL CHK_BUSY
MOV A,#28H
CALL WRINS_ONCE
CALL DELAY30uS
SWAP
WRINS_ONCE:
A
;FUNCTION SET
; 4 bit, 5*7 dot
ANL A,#F0H
CLR RS
CLR RW
MOV A,#29H
CALL WRINS_CHK
CALL DELAY30uS
;FUNCTION SET
; 4 bit N = 1, 5*7 dot
; IS = 1
SETB
MOV P1,A
CLR
E
E
MOV P1,#FFH
RET
;For Check Bus Flag
MOV A,#14H
;Internal OSC
CALL WRINS_CHK
CALL DELAY30uS
;-------------------------------------------------------------------
CHK_BUSY:
PUSH
;Check Busy Flag
A
MOV
A,#78H
;Contrast set
MOV P1,#FFH
CALL WRINS_CHK
CALL DELAY30uS
$1
CLR RS
SETB RW
MOV A,#5EH
CALL WRINS_CHK
CALL DELAY30uS
;Power/ICON/Contrast
SETB
MOV A,P1
CLR
E
E
MOV P1,#FFH
CLR RS
SETB RW
MOV A,#6AH
CALL WRINS_CHK
CALL DELAY200mS
;Follower control
;For power stable
;DISPLAY ON
SETB
NOP
CLR
JB
POP
RET
E
MOV A,#0CH
CALL WRINS_CHK
CALL DELAY30uS
E
A.7,$1
A
MOV A,#01H
;CLEAR DISPLAY
CALL WRINS_CHK
CALL DELAY2mS
MOV A,#06H
;ENTRY MODE SET
CALL WRINS_CHK
CALL DELAY30uS
;-------------------------------------------------------------------
MAIN_START:
XXXX
XXXX
XXXX
.
V1.4
2008/08/18
32/61
ST7032
l
Serial interface & IIC interface ( fosc = 380KHz )
POWER ON and external reset
Wait time >40mS
After VDD stable
Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
N
DH
0
IS
Wait time >26.3μS
Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
N
DH
0
IS
Wait time >26.3μS
Internal OSC frequency
Power/ICON/Contrast control
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
BS F2 F1 F0
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
1
Bon
C5
C4
0
0
0
1
0
1
Ion
Wait time >26.3μS
Wait time >26.3μS
Contrast set
Follower control
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
1
1
C3
C2
C1
C0
Rab2 Rab1 Rab0
0
0
0
1
1
0
Fon
Wait time >26.3μS
Wait time >200mS
(for power stable)
Display ON/OFF control
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
1
D
C
B
Wait time >26.3μS
Initialization end
V1.4
2008/08/18
33/61
ST7032
Ø
Initial Program Code Example For 8051 MPU(Serial Interface):
;---------------------------------------------------------------------------------
INITIAL_START:
CALL HARDWARE_RESET
CALL DELAY40mS
MOV A,#38H
;FUNCTION SET
CALL WRINS_NOCHK ;8 bit,N=1,5*7dot
CALL DELAY30uS
MOV A,#39H
;FUNCTION SET
CALL WRINS_NOCHK ;8 bit,N=1,5*7dot,IS=1
CALL DELAY30uS
MOV A,#14H
;Internal OSC frequency adjustment
CALL WRINS_NOCHK
CALL DELAY30uS
MOV A,#78H
;Contrast set
CALL WRINS_NOCHK
CALL DELAY30uS
MOV A,#5EH
CALL WRINS_NOCHK
CALL DELAY30uS
MOV A,#6AH
;Power/ICON/Contrast control
;Follower control
CALL WRINS_NOCHK
CALL DELAY200mS
MOV A,#0CH
;for power stable
;DISPLAY ON
CALL WRINS_NOCHK
CALL DELAY30uS
MOV A,#01H
;CLEAR DISPLAY
CALL WRINS_NOCHK
CALL DELAY2mS
MOV A,#06H
;ENTRY MODE SET
CALL WRINS_NOCHK ;CURSOR MOVES TO RIGHT
CALL DELAY30uS
;---------------------------------------------------------------------------------
MAIN_START:
XXXX
XXXX
XXXX
XXXX
.
.
.
;---------------------------------------------------------------------------------
WRINS_NOCHK:
PUSH
MOV
CLR
1
R1,#8
RS
$1
RLC
A
MOV SI,C
SET
NOP
CLR
SCL
SCL
DJNZ R1,$1
POP
1
CALL DLY1.5mS
RET
V1.4
2008/08/18
34/61
ST7032
n Interfacing to the MPU
The ST7032 can send data in two 4-bit operations/one 8-bit operation, serial 1 bit operation or fastI2C operation,
thus allowing interfacing with 4-bit, 8-bit or I2C MPU.
l
For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3
are disabled. The data transfer between the ST7032 and the MPU is completed after the 4-bit data has been
transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB4 to DB7)
are transferred before the four low order bits (for 8-bit operation, DB0 to DB3). The busy flag must be
checked (one instruction) after the 4-bit data has been transferred twice. Two more 4-bit operations then
transfer the busy flag and address counter data.
Ø
Example of busy flag check timing sequence
CSB
RS
R/W
E
Internal
operation
Functioning
Not
Busy
IR7
IR3
AC3
AC3
IR7
IR3
DB7
Instruction write
Busy flag check
Busy flag check
Instruction write
Ø
Intel 8051 interface(4 Bit)
16
COM1 to COM16
DB4 to DB7
4
P1.0 to P1.3
P3.0
P3.1
P3.2
P3.3
RS
R/W
E
80
SEG1 to SEG80
CSB
Intel 8051 Serial
ST7032
V1.4
2008/08/18
35/61
ST7032
l
For 8-bit interface data, all eight bus lines (DB0 to DB7) are used.
Ø
Example of busy flag check timing sequence
CSB
RS
R/W
E
Internal
operation
Functioning
Not
Busy
Data
Busy
Busy
Data
DB7
Instruction
write
Busy flag
check
Busy flag
check
Busy flag
check
Instruction
write
Ø
Intel 8051 interface(8 Bit)
16
COM1 to COM16
DB0 to DB7
8
P1.0 to P1.7
P3.0
P3.1
P3.2
P3.3
RS
R/W
E
80
SEG1 to SEG80
CSB
Intel 8051 Serial
ST7032
V1.4
2008/08/18
36/61
ST7032
l
For serial interface data, only two bus lines (DB6 to DB7) are used.
Ø
Example of timing sequence
CSB
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
SI
SCL
RS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Note:The falling edge must cause on CSB before the serial clock ( SCL ) active.
Ø
Intel 8051 interface(Serial)
16
COM1 to COM16
SI , SCL
2
P1.6 to P1.7
P3.0
P3.3
RS
CSB
80
SEG1 to SEG80
ST7032
Intel 8051 Serial
V1.4
2008/08/18
37/61
ST7032
l
For I2C interface data, only two bus lines (DB6 to DB7) are used.
Ø
Example of timing sequence
. . . . . . .
ACK
ACK
SDA
SCL
D7
1
D6
2
D5
3
D4
4
D3
5
D2
6
D1
7
D0
8
D0
. . . . . .
9
Ø
Intel 8051 interface( I2C )
16
COM1 to COM16
SDA , SCL
2
P1.6 to P1.7
80
SEG1 to SEG80
ST7032
Intel 8051 Serial
V1.4
2008/08/18
38/61
ST7032
n Supply Voltage for LCD Drive
l
When external bias resistors are used
(OPF1=1,OPF2=1)
VCC (2.7~ 5.5V)
VCC (2.7~ 5.5V)
Vext
Vext
OPF1 OPF2
OPF1 OPF2
VDD
V0
VDD
V0
VOUT
VIN
VR
VR
VOUT
VIN
R
R
V1
V2
CAP1P
CAP1N
CAP1P
CAP1N
V1
R
R
R
R
R
V2
V3
VLCD
VLCD
V3
V4
V4
R
VSS
VSS
1/4 bias
1/5 bias
GND
GND
l
When built-in bias resistors(9.6KΩ) are used
(OPF1=1,OPF2=0)
VCC(2.7~5.5V)
Vext
OPF1
VOUT
VDD
V0
VR
VIN
V1
V2
CAP1P
CAP1N
VLCD
V3
V4
VSS
OPF2
GND
V1.4
2008/08/18
39/61
ST7032
l
When built-in bias resistors(3.3KΩ) are used
(OPF1=0,OPF2=1)
VCC (2.7~ 5.5V)
Vext
OPF2
VOUT
VDD
V0
VR
VIN
V1
V2
CAP1P
CAP1N
VLCD
V3
V4
VSS
OPF1
GND
l
When built-in voltage followers with external Vout are used
(OPF1=0,OPF2=0 and instruction setting Bon=0,Fon=1)
VCC (2.7~ 5.5V)
Vext ≧ V0
Don't need to connect stable capacitor when
use internal follower circuit
VOUT
VIN
VDD
V0
V1
V2
CAP1P
CAP1N
VLCD
V3
V4
VSS
OPF1 OPF2
GND
V1.4
2008/08/18
40/61
ST7032
l
When built-in booster and voltage followers are used(OPF1=0,OPF2=0)
VCC (2.7~ 3.5V)
Don't need to connect stable capacitor when
use internal follower circuit
VIN
VDD
V0
VOUT
VOUT≦2xVDD
VDD=2.7~3.5V
VSS=0V
V1
V2
CAP1P
CAP1N
VLCD
V3
V4
2 x step-up voltage relationships
VSS
OPF1 OPF2
GND
Note:
Ensure V0 level stable, that must let |Vout-V0| over 0.5V(if panel size over 4.5”,the |Vout-V0| propose over 0.8V).
|Vout-V0|>0.5V(minimum)
Vout
V0
VCC
VDD
VSS
GND
(System side)
(ST7032Side)
V1.4
2008/08/18
41/61
ST7032
Ø
V0 voltage follower value calculation
VDD
Vout(≧VDD)
Rb
Ra
V0=(1+
) Vref
Vref
Ra
*
V0
α+36
)
Rb
While Vref=VDD (
*
100
VSS
C5
0
C4
C3
C2
0
C1
0
C0
0
α
0
Rab2 Rab1 Rab0 1+Rb/Ra
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1.25
1.5
1.8
2
0
0
0
1
1
0
0
1
0
2
.
.
.
.
2.5
3
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
61
62
63
3.75
8
7
6
5
4
3
2
1
0
1
3
5
7
9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63
V0 level (Condition:Booster on, Follower on, VIN=3.5V, VDD=3.0V,Display off)
The recommended curve: follower = 04H
Notes:
1.
Vout ≧V0 ≧V1 ≧V2 ≧V3 ≧V4 ≧Vss must be maintained.
2.
3.
If the calculation value of V0 is higher than Vout, the real V0 value will saturate to Vout.
internal built-in booster can only be used when OPF1=0,OPF2=0.
V1.4
2008/08/18
42/61
ST7032
8
7
6
5
4
3
2
1
0
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62
(Condition:Booster on, Follower on, VIN = 3.5 V, VDD=5.0V, Display off)
V0 level
The recommanded curve: follower = 01H
Notes:
1.
Vout ≧V0 ≧V1 ≧V2 ≧V3 ≧V4 ≧Vss must be maintained.
2.
3.
If the calculation value of V0 is higher than Vout, the real V0 value will saturate to Vout.
internal built-in booster can only be used when OPF1=0,OPF2=0.
V1.4
2008/08/18
43/61
ST7032
n AC Characteristics
l
68 Interface
RS
R/W
tAW6
tAH6
CSB
tCYC6
tEWH
tEWL
E
tr
tf
tDS6
tDH6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
( Ta = 25°C )
VDD=4.5 to 5.5V
Rating
VDD=2.7 to 4.5V
Rating
Item
Signal
Symbol
Condition
Units
Min.
Max.
Min.
Max.
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
RS
RS
tAH6
tAW6
tCYC6
tDS6
tDH6
tACC6
tOH6
tr,tf
20
20
400
100
40
-
-
20
20
280
80
20
-
-
—
—
—
ns
ns
ns
-
-
RS
-
-
-
-
D0 to D7
D0 to D7
D0 to D7
D0 to D7
E
-
-
Access time
500
-
400
-
CL = 100 pF
ns
Output disable time
Enable Rise/Fall time
300
-
150
-
—
—
—
20
20
ns
ns
ns
Enable H pulse time
Enable L pulse time
E
E
tEWH
200
150
-
-
120
130
-
-
tEWL
Note: All timing is specified using 20% and 80% of VDD as the reference.
V1.4
2008/08/18
44/61
ST7032
l
Serial Interface
tCSS
tCSH
CSB
RS
tSAS
tSAH
tSCYC
tSLW
tSHW
SCL
tf
tr
tSDS
tSDH
SI
( Ta = 25°C )
VDD=2.7 to 4.5V
Rating
VDD=4.5 to 5.5V
Rating
Item
Signal
Symbol
Condition
Units
Min.
Max.
Min.
Max.
Serial Clock Period
SCL “H” pulse width
SCL “L” pulse width
SCL Rise/Fall time
Address setup time
Address hold time
Data setup time
200
20
-
-
100
20
-
-
tSCYC
tSHW
tSLW
tr,tf
SCL
—
ns
160
-
-
120
-
-
SCL
RS
—
—
20
-
20
-
ns
ns
10
10
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
250
10
-
150
10
-
-
-
SI
—
—
ns
ns
Data hold time
10
-
20
-
20
-
20
-
CS-SCL time
CS
350
-
200
-
*1 All timing is specified using 20% and 80% of VDD as the standard.
V1.4
2008/08/18
45/61
ST7032
l
I2C interface
SDA
t
BUF
t
HIGH
t
SU; DAT
t
LOW
SCL
SDA
t
f
t
DH; STA
t
r
t
HD; DAT
t
SU; STA
t
SU; STO
( Ta = 25°C )
VDD=2.7 to 4.5V VDD=4.5 to 5.5V
Rating Rating
Units
Item
Signal Symbol Condition
Min.
Max.
Min.
Max.
SCL clock frequency
SCL clock low period
fSCLK
DC
1.3
0.6
180
0
400
—
—
DC
1.3
0.6
100
0
400 KHz
SCL
SI
—
—
—
us
—
tLOW
tHIGH
tSU;DAT
tHD:DAT
tr
SCL clock high period
Data set-up time
Data hold time
—
—
ns
us
0.9
300
300
0.9
300
300
20+0.1C
b
20+0.1C
b
SCL,SDA rise time
SCL,SDA fall time
Capacitive load represent by each bus
SCL,
SDA
—
—
ns
pf
20+0.1C
b
20+0.1C
b
tf
—
—
Cb
400
400
line
Setup time for a repeated START
condition
Start condition hold time
—
—
—
—
tSU;STA
tHD;STA
tSU;STO
—
—
0.6
0.6
0.6
0.6
us
us
SI
—
—
—
—
Setup time for STOP condition
—
—
0.6
1.3
0.6
1.3
us
us
Bus free time between a Stop and
START condition
SCL
tBUF
V1.4
2008/08/18
46/61
ST7032
l
Internal Power Supply Reset
2.7V/4.5V
0.2V
0.2V
0.2V
trcc
tOFF
0.1mS≦trcc≦10mS
tOFF≧1mS
Notes:
w
w
w
tOFF compensates for the power oscillation period caused by momentary power supply oscillations.
Specified at 4.5V for 5V operation,and at 2.7V for 3V operation.
If 2.7V/4.5V is not reached during 3V/5V operation, internal reset circuit will not operate normally.
l
Hardware reset(XRESET)
tr≦100nS
2.7V/4.5V
0.2V
tL>100uS
V1.4
2008/08/18
47/61
ST7032
n Absolute Maximum Ratings
Characteristics
Power Supply Voltage
LCD Driver Voltage
Input Voltage
Symbol
Value
VDD
VLCD
VIN
-0.3 to +6.0
7.0- Vss to -0.3+Vss
-0.3 to VDD+0.3
-30oC to + 85oC
-65oC to + 150oC
Operating Temperature
Storage Temperature
TA
TSTO
n DC Characteristics
( TA = 25℃ , VDD = 2.7 V – 4.5 V )
Symbol Characteristics
Test Condition
Min. Typ. Max. Unit
VDD
VLCD
Operating Voltage
LCD Voltage
-
2.7
2.7
-
-
4.5
7.0
V
V
V0-Vss
VDD=3.0V
(Use internal
booster/follower circuit)
ICC
VIH1
VIL1
Power Supply Current
-
160
230
VDD
0.8
uA
V
V
V
V
V
V
V
V
Input High Voltage
(Except OSC1)
-
1.9
- 0.3
-
-
-
-
-
-
-
-
Input Low Voltage
(Except OSC1)
-
Input High Voltage
(OSC1)
0.7
VDD
VIH2
-
VDD
Input Low Voltage
(OSC1)
0.2
VDD
VIL2
-
-
Output High Voltage
(DB0 - DB7)
0.75
VDD
VOH1
VOL1
VOH2
VOL2
IOH = -1.0mA
IOL = 1.0mA
IOH = -0.04mA
IOL = 0.04mA
-
Output Low Voltage
(DB0 - DB7)
-
0.8
Output High Voltage
(Except DB0 - DB7)
0.8
VDD
VDD
Output Low Voltage
(Except DB0 - DB7)
0.2
VDD
-
RCOM
RSEG
Common Resistance VLCD = 4V, Id = 0.05mA
Segment Resistance VLCD = 4V, Id = 0.05mA
-
-
2
2
20
30
KW
KW
Input Leakage
VIN = 0V to VDD
Current
ILEAK
-1
-
1
mA
IPUP
Pull Up MOS Current
Oscillation frequency
VDD = 3V
20
30
40
mA
fOSC
VDD = 3V,1/17duty
350
540
1100
KHz
V1.4
2008/08/18
48/61
ST7032
n DC Characteristics
( TA = 25℃, VDD = 4.5 V - 5.5 V )
Symbol Characteristics
Test Condition
Min. Typ. Max. Unit
VDD
VLCD
Operating Voltage
LCD Voltage
-
4.5
2.7
-
-
5.5
7.0
V
V
V0-Vss
VDD=5.0V
(Use internal
booster/follower circuit)
ICC
VIH1
VIL1
Power Supply Current
-
240
340
VDD
0.8
uA
V
V
V
V
V
V
V
V
Input High Voltage
(Except OSC1)
-
2.7
-0.3
-
-
-
-
-
-
-
-
Input Low Voltage
(Except OSC1)
-
Input High Voltage
(OSC1)
0.7
VDD
VIH2
-
VDD
1.0
Input Low Voltage
(OSC1)
VIL2
-
-
3.8
-
Output High Voltage
(DB0 - DB7)
VOH1
VOL1
VOH2
VOL2
IOH = -1.0mA
IOL = 1.0mA
IOH = -0.04mA
IOL = 0.04mA
VDD
0.8
Output Low Voltage
(DB0 - DB7)
Output High Voltage
(Except DB0 - DB7)
0.8
VDD
VDD
Output Low Voltage
(Except DB0 - DB7)
0.2
VDD
-
RCOM Common Resistance VLCD = 4V, Id = 0.05mA
-
-
2
2
20
30
KW
KW
RSEG
Segment Resistance VLCD = 4V, Id = 0.05mA
Input Leakage
VIN = 0V to VDD
Current
ILEAK
-1
-
1
mA
IPUP
Pull Up MOS Current
Oscillation frequency
VDD = 5V
65
95
125
mA
fOSC
VDD = 5V,1/17duty
350
540
1100
KHz
V1.4
2008/08/18
49/61
ST7032
n LCD Frame Frequency
l
1/16 Duty(ST7066U normal mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time
= 1.85us, 1/16 duty; 1/5 bias,1 frame =1.85us x 200 x 16 = 5.92ms=168.9Hz(SHLC and SHLS connect
to High)
200 clocks
n
1
2
3
4
16
1
2
3
4
16
1
2
3
4
16
V0
V1
V2
COM1
V3
V4
Vss
V0
V1
V2
COM2
V3
V4
Vss
V0
V1
V2
COM16
V3
V4
Vss
V0
V1
V2
SEGx off
V3
V4
Vss
V0
V1
V2
SEGx on
V3
V4
Vss
1 frame
V1.4
2008/08/18
50/61
ST7032
l
1/17 Duty(Extension mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time =
1.85us, 1/17 duty; 1/5 bias,1 frame =1.85us x 200 x 17 = 6.29ms=159Hz(SHLC and SHLS connect to
High)
200 clocks
1
2
3
4
17
1
2
3
4
17
1
2
3
4
17
V0
V1
V2
COM1
V3
V4
Vss
V0
V1
V2
COM2
V3
V4
Vss
V0
V1
V2
COM17
V3
V4
Vss
V0
V1
V2
SEGx off
V3
V4
Vss
V0
V1
V2
SEGx on
V3
V4
Vss
1 frame
V1.4
2008/08/18
51/61
ST7032
l
1/8 Duty(ST7066U normal mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time =
1.85us, 1/8 duty; 1/4 bias,1 frame = 1.85us x 400 x 8 = 5.92ms=168.9Hz(SHLC and SHLS connect to
400 clocks
1
2
3
4
8
1
2
3
4
8
1
2
3
4
8
V0
V1
V2
V3
COM1
V4
Vss
V0
V1
V2
V3
COM2
V4
Vss
V0
V1
V2
V3
COM8
V4
Vss
V0
V1
V2
V3
SEGx off
V4
Vss
V0
V1
V2
V3
SEGx on
V4
Vss
1 frame
High)
V1.4
2008/08/18
52/61
ST7032
l
1/9 Duty(Extension mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time =
1.85us, 1/9 duty; 1/4 bias,1 frame = 1.85us x 400 x 9 = 6.66ms=150Hz(SHLC and SHLS connect to
400 clocks
1
2
3
4
9
1
2
3
4
9
1
2
3
4
9
V0
V1
V2
V3
COM1
V4
Vss
V0
V1
V2
V3
COM2
V4
Vss
V0
V1
V2
V3
COM9
V4
Vss
V0
V1
V2
V3
SEGx off
V4
Vss
V0
V1
V2
V3
SEGx on
V4
Vss
1 frame
High)
V1.4
2008/08/18
53/61
ST7032
n I/O Pad Configuration
V1.4
2008/08/18
54/61
ST7032
n LCD and ST7032 Connection
SHLC/SHLS ITO option pin can select at different direction for LCD panel
l
Com normal direction/Seg normal direction
l
Com normal direction/Seg reverse direction
l
Com reverse direction/Seg normal direction
l
Com reverse direction/Seg reverse direction
V1.4
2008/08/18
55/61
ST7032
n Application Circuit(ST7066U normal mode)
Ø Use internal resistor(9.6K ohm) and contrast adjust with external VR.
Ø Booster always off.
Ø Has 240 character of CGROM and 8 characters of CGRAM
Ø Internal oscillator.
Dot Matrix LCD Panel
VDD
Com 1-16
Seg 1-80
Vext
VOUT
VIN
CLS
SHLC
SHLS
CAP1N
CAP1P
V0
V1
V2
V3
V4
EXT
OPF1
OPF2
OPR1
OPR2
ST7032
RS,R/W,E,CSB,DB0-DB7,XRESET
To MPU
V1.4
2008/08/18
56/61
ST7032
n Application Circuit(Extension mode)
Ø Use internal follower circuit.
Ø Booster has 2 times pump.
Ø Has 240 character of CGROM and 8 characters of CGRAM
Ø Internal oscillator
Dot Matrix LCD Panel
Vext
VDD
Com 1-17
Seg 1-80
VOUT
VIN
CLS
SHLC
SHLS
CAP1N
CAP1P
V0
V1
V2
V3
V4
EXT
OPF1
OPF2
OPR1
OPR2
ST7032
RS,R/W,E,CSB,DB0-DB7,XRESET
To MPU
l
When the heavy load is applied, the dotted line part could be added.
V1.4
2008/08/18
57/61
ST7032
n Application Circuit(for glass layout)
l
ST7032 over Glass,6800 serial 8bit interface, with booster and follower circuit on
V1.4
2008/08/18
58/61
ST7032
l
ST7032 over Glass,6800 serial 4bit interface, with booster and follower circuit on
V1.4
2008/08/18
59/61
ST7032
l
ST7032 under Glass, serial interface, with booster and follower circuit on
V1.4
2008/08/18
60/61
ST7032
l
ST7032i under Glass, IIC interface, with booster and follower circuit on
V1.4
2008/08/18
61/61
Appendix – Product Number
Product Number
OPR1
OPR2
Support Character
ST7032-0D
1
1
English/Japan/European
Table A1. Correspondence between Character Codes and Character Patterns
A1
Table A2. Select display pattern in CGRAM or CGROM (use OPR1, OPR2)
OPR2,OPR1=(0,0) OPR2,OPR1=(0,1) OPR2,OPR1=(1,0) OPR2,OPR1=(1,1)
A2
相关型号：
©2020 ICPDF网 联系我们和版权申明