ST7033 [SITRONIX]
4 x 96 Dot Matrix LCD Controller/Driver; 4 ×96点阵LCD控制器/驱动器
| 型号： | ST7033 |
| 厂家： | 
SITRONIX TECHNOLOGY CO., LTD. |
| 描述： | 4 x 96 Dot Matrix LCD Controller/Driver |
| 文件： | 总39页 (文件大小：436K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST
ST7033
Sitronix
4 x 96 Dot Matrix LCD Controller/Driver
1. INTRODUCTION
The ST7033 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 96 segment and 4
common driver circuits. This chip is connected directly to a microprocessor, accepts 3-line serial peripheral interface (SPI),
display data can stores in an on-chip display data RAM of 4 x 96 bits. It performs display data RAM read/write operation
with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits to
drive liquid crystal, it is possible to make a display system with the fewest components.
2. FEATURES
Single-chip LCD controller & driver
Driver Output Circuits
supply voltage (external V0/XV0 voltage supply is
also supported).
ꢀ
ꢀ
4 common outputs / 96 segment. Output
96 segment drivers : up to forty-eight 8-segment
numeric characters; up to twenty-five 15-segment
alphanumeric characters; or any graphics of up to
384 elements
ꢀ
ꢀ
ꢀ
Built-in high-accuracy Regulator.
Built-in voltage follower generates LCD bias voltages
Built-in Oscillator requires no external components
(external clock is also supported)
External RESB (reset) pin
Logic supply voltage range
On-chip Display Data Ram
Capacity: 4X96=384bits
Microprocessor Interface
ꢀ
ꢀ
ꢀ
VDD1-VSS: 1.65V~3.4V
VDD2-VSS: 2.5V~3.4V
ꢀ
ꢀ
Parallel MPU interface: 8-bit parallel 6800-series or
8080-series
Display supply voltage 4.0V
Temperature range: -30 to +80 degree
Serial MPU interface: 4-line and 3-line SPI (serial
peripheral interfaces) are available.
On-chip Low Power Analog Circuit
Built-in Booster (x4 or x5) circuit generates LCD
ꢀ
Ver 1.1
1/39
2009/07/17
ST7033
3. ST7033 PAD ARRANGEMENT (COG)
Dice Size:
5080um X 770um
Bump Height: 15um
Chip Thickness: 300um
Bump Pitch:
PAD Number
Pitch (um)
37.2
PAD Number
Pitch (um)
86.97
46.66
38.8
1~23, 120~142, 143~153, 227~238:
24~119:
153-154:
199-200
33
154~199, 213~226:
200~205, 207~212:
23-24:
59.3
205-206, 206-207
212-213
33.3
53.44
79.9
69.1
226-227
119-120:
60.70
Ver 1.1
2/39
2009/07/17
ST7033
4-1. PAD CENTER COORDINATES
NO.
1
NAME
NC
X
Y
NO.
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
NAME
X
Y
2450.80
2413.60
2376.40
2339.20
2302.00
2264.80
2227.60
2190.40
2153.20
2116.00
2078.80
2041.60
2004.40
1967.20
1930.00
1892.80
1855.60
1818.40
1781.20
1744.00
1706.80
1669.60
1632.40
1563.30
1530.30
1497.30
1464.30
1431.30
1398.30
1365.30
1332.30
1299.30
1266.30
1233.30
1200.30
1167.30
1134.30
1101.30
1068.30
1035.30
1002.30
969.30
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
SEG[22]
SEG[23]
SEG[24]
SEG[25]
SEG[26]
SEG[27]
SEG[28]
SEG[29]
SEG[30]
SEG[31]
SEG[32]
SEG[33]
SEG[34]
SEG[35]
SEG[36]
SEG[37]
SEG[38]
SEG[39]
SEG[40]
SEG[41]
SEG[42]
SEG[43]
SEG[44]
SEG[45]
SEG[46]
SEG[47]
SEG[48]
SEG[49]
SEG[50]
SEG[51]
SEG[52]
SEG[53]
SEG[54]
SEG[55]
SEG[56]
SEG[57]
SEG[58]
SEG[59]
SEG[60]
SEG[61]
SEG[62]
SEG[63]
SEG[64]
SEG[65]
SEG[66]
837.30
804.30
771.30
738.30
705.30
672.30
639.30
606.30
573.30
540.30
507.30
474.30
441.30
408.30
375.30
342.30
309.30
276.30
243.30
210.30
177.30
144.30
111.30
78.30
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
2
NC
3
NC
4
NC
5
NC
6
NC
7
NC
8
NC
9
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SEG[0]
SEG[1]
SEG[2]
SEG[3]
SEG[4]
SEG[5]
SEG[6]
SEG[7]
SEG[8]
SEG[9]
SEG[10]
SEG[11]
SEG[12]
SEG[13]
SEG[14]
SEG[15]
SEG[16]
SEG[17]
SEG[18]
SEG[19]
SEG[20]
SEG[21]
45.30
12.30
-20.71
-53.71
-86.71
-119.71
-152.71
-185.71
-218.71
-251.71
-284.71
-317.71
-350.71
-383.71
-416.71
-449.71
-482.71
-515.71
-548.71
-581.71
-614.71
936.30
903.30
870.30
Ver 1.1
3/39
2009/07/17
ST7033
NO.
91
NAME
SEG[67]
SEG[68]
SEG[69]
SEG[70]
SEG[71]
SEG[72]
SEG[73]
SEG[74]
SEG[75]
SEG[76]
SEG[77]
SEG[78]
SEG[79]
SEG[80]
SEG[81]
SEG[82]
SEG[83]
SEG[84]
SEG[85]
SEG[86]
SEG[87]
SEG[88]
SEG[89]
SEG[90]
SEG[91]
SEG[92]
SEG[93]
SEG[94]
SEG[95]
NC
X
Y
NO.
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
NAME
NC
X
Y
-647.71
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
282.75
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
293.00
-2339.20
-2376.40
-2413.60
-2450.80
-2450.80
-2413.60
-2376.40
-2339.20
-2302.00
-2264.80
-2227.60
-2190.40
-2153.20
-2116.00
-2078.80
-1991.84
-1932.53
-1873.23
-1813.92
-1754.62
-1695.31
-1636.01
-1576.70
-1517.40
-1458.09
-1398.79
-1339.49
-1280.18
-1220.88
-1161.57
-1102.27
-1042.96
-983.66
-924.35
-865.05
-805.74
-746.43
-687.13
-627.83
-568.52
-509.22
-449.91
-390.61
-331.30
-272.00
-212.69
-153.39
-94.08
293.00
293.00
293.00
293.00
-293.00
-293.00
-293.00
-293.00
-293.00
-293.00
-293.00
-293.00
-293.00
-293.00
-293.00
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
92
-680.71
NC
93
-713.71
NC
94
-746.71
NC
95
-779.71
NC
96
-812.71
NC
97
-845.71
NC
98
-878.71
NC
99
-911.71
NC
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
-944.71
NC
-977.71
NC
-1010.71
-1043.71
-1076.71
-1109.71
-1142.71
-1175.71
-1208.71
-1241.71
-1274.71
-1307.71
-1340.71
-1373.71
-1406.71
-1439.71
-1472.71
-1505.71
-1538.71
-1571.71
-1632.40
-1669.60
-1706.80
-1744.00
-1781.20
-1818.40
-1855.60
-1892.80
-1930.00
-1967.20
-2004.40
-2041.60
-2078.80
-2116.00
-2153.20
-2190.40
-2227.60
-2264.80
-2302.00
NC
NC
NC
NC
VM
VM
VM
VGO
VGO
VGI
VGI
VGI
VGI
VGS
/RESB
/CSB
PS0
PS1
TMX
TMY
BR
COM[0]
COM[1]
COM[2]
COM[3]
NC
MODE
CP
VSS
VSS
VSS
VSS
VSS
RW_WR
E_RD
DA
NC
NC
NC
NC
NC
NC
NC
NC
A0
NC
D[7]
D[6]
D[5]
D[4]
D[3]
NC
NC
NC
NC
Ver 1.1
4/39
2009/07/17
ST7033
NO.
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
NAME
D[2]
D[1]
D[0]
OSC
VDD1
VDD1
VDD1
VDD1
VDD2
VDD2
VDD2
VDD2
VRS
T[1]
X
Y
NO.
234
235
236
237
238
NAME
NC
X
Y
-34.78
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-307.75
-307.75
-307.75
-307.75
-307.75
-307.75
-307.75
-307.75
-307.75
-307.75
-307.75
-307.75
-307.75
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-311.50
-293.00
-293.00
-293.00
-293.00
-293.00
-293.00
-293.00
2302.00
2339.20
2376.40
2413.60
2450.80
-293.00
-293.00
-293.00
-293.00
-293.00
24.54
NC
83.84
NC
143.15
202.45
261.75
321.06
380.37
439.67
498.97
558.28
617.59
676.89
723.54
756.84
790.14
823.44
856.74
890.04
928.84
967.64
1000.94
1034.24
1067.54
1100.84
1134.14
1187.58
1246.89
1306.20
1365.50
1424.80
1484.11
1543.42
1605.87
1665.17
1724.48
1783.79
1843.09
1902.39
1961.70
2041.60
2078.80
2116.00
2153.20
2190.40
2227.60
2264.80
NC
NC
T[2]
T[3]
T[4]
T[5]
T[6]
T[0]
T[7]
T[8]
T[9]
T[10]
T[11]
T[12]
V0O
V0O
V0I
V0I
V0I
V0I
V0S
XV0O
XV0O
XV0I
XV0I
XV0I
XV0I
XV0S
NC
NC
NC
NC
NC
NC
NC
Ver 1.1
5/39
2009/07/17
ST7033
5. BLOCK DIAGRAM
SEG0...SEG95
COM0...COM3
VM
VG
SEGMENT
Drivers
COMMON
Drivers
VM
Voltage
Follower
VGI
VGO
VGS
COMMON
Output
Controller
DisplayꢀDataꢀLatchs
XV0I
XV0O
XV0S
XV0
Generator
XV0
Timing
Generator
V0I
V0O
V0S
V0
Generator
V0
DisplayꢀDataꢀRAM
(DDRAM)
4X96
Power
System
VDD2
Oscillator
OSC
Data
Register
Address
Counter
Control
Registers
VDD1
VSS
Command
Decoder
Reset
Circuit
MPUꢀINTERFACEꢀ(Parallelꢀ/ꢀSerial)
Figure 1. Block Diagram
Ver 1.1
6/39
2009/07/17
ST7033
6. PINNING DESCRIPTIONS
Pin Name
I/O
Description
Pin Count
LCD driver outputs
LCD segment driver outputs.
The display data and the M signal control the output voltage of segment
driver.
Segment drover output voltage
Display data
Frame
-
Normal display
Reverse display
SEG0 to SEG95
O
96
H
H
L
VG
VSS
VSS
VG
VSS
VG
+
-
VG
L
+
VSS
VSS
Power save mode
VSS
LCD column driver outputs.
The internal scanning data and the M signal control the output voltage of
common driver.
Common drover output voltage
Display data
Frame
Normal display
Reverse display
COM0 to COM3
O
68
H
H
L
-
+
-
XV0
V0
VM
VM
VSS
L
+
Power save mode
MICROPROCESSOR INTERFACE
Microprocessor interface mode selection pins.
PS1
1
PS0
1
Interface Mode
8080-series parallel MPU interface
6800-series parallel MPU interface
4-line SPI MPU interface
PS[1,0]
I
2
1
0
0
1
0
0
3-line SPI MPU interface
Chip select input pin.
/CSB
I
I
Data/instruction I/O is enabled only when /CSB is "L". When chip select is
non-active, D7…D0 are high impedance.
Reset input pin.
1
1
/RESB
When /RESB is "L", initialization is executed.
It determines whether the data bits are data or a command.
A0=" H “: Indicates that D0 to D7 are display data.
A0=" L “: Indicates that D0 to D7 are control data.
There is no A0 pin in three line , so this pin can fix to ” H”
A0
I
1
Read/Write operation control pin (if using Parallel interface).
MPU Type
RW_WR
Interface Mode
R/W=”H”: Read;
6800-series
R/W
RW_WR
I
R/W=”L”: Write.
1
Signals (Instruction or Data) on
data bus will be latched at the
raising edge of this signal.
8080-series
/WR
Ver 1.1
7/39
2009/07/17
ST7033
Read/Write operation control pin (if using Parallel interface).
MPU Type
E_RD
Interface Mode
Signals (Instruction or Data) on
data bus will be latched by MPU
or this IC (depends on R/W) at
the falling edge of this signal.
Internal status (or display data)
will be read out to data bus after
the falling edge of this signal.
6800-series
E
E_RD
I
1
8080-series
/RD
Data Bus. If /CSB signal is not actived, D7…D0 are high impedance.
ꢀ
Parallel interface (6800 or 8080):
I/O port which is connected to the standard 8-bit MPU data bus.
Serial SPI interface (3 line or 4 line):
SCLK: D0;
D0…D7
I
ꢀ
8
SDA: D1~D3;
D4~D7 must connect to VDD1.
LCD DRIVER SUPPLY
OSC
ꢀ
ꢀ
OSC=”H”: Use the built-in oscillator.
OSC=”L”: Both external clock and built-in oscillator are inhibited. And
the display circuits will not be clocked and kept in a DC state. To
avoid this, the chip should always be put into Power-Down Mode
before stopping the clock.
I
1
ꢀ
If using external clock, connect this pin to the external clock.
POWER SUPPLY
VSS
Power Ground.
Digital circuits supply voltage.
5
4
VDD1
Power The 2 power supply rails, VDD1 and VDD2, could be connected together.
Use this power to be the high voltage level for the Option pins.
Analog circuits supply voltage.
VDD2
Power
4
7
The 2 power supply rails, VDD and VDD2, could be connected together.
Negative LCD driver supply voltages.
Power
XV0I, XV0O & XV0S should be separated in ITO layout.
XV0I, XV0O, XV0S
Supply
XV0I, XV0O & XV0S should be connected together in FPC layout.
This is a multi-level power supply for the liquid crystal.
V0 ≥ VG ≥ VM ≥ VSS ≥ XV0
V0I, V0O & V0S should be separated in ITO layout.
V0I, V0O, V0S;
VGI, VGO, VGS
Power
6
V0I, V0O & V0S should be connected together in FPC layout.
VGI, VGO & VGS should be separated in ITO layout.
Supply
VGI, VGO & VGS should be connected together in FPC layout.
Power
VM
3
1
LCD driving voltage for commons.
Supply
Reserved to monitor internal Voltage Regulator reference level, must be left
VRS
Configuration Pins
MODE
Power
open.
Test pin.
I
1
1
Must fix to “L”
Set Booster stage.
CP
I
VSS=4X;
VDD=5X.
Ver 1.1
8/39
2009/07/17
ST7033
Test pin.
BR
I
1
Must fix to “L”
Test Pin
T0~T12
---
I
Test pins. Do not use these pins.
13
1
Mirror X: SEG bi-direction selection (refer to pad center coordinates).
TMX connect to VSS :MX mode1(refer to segment driver direction select)
TMX connect to VDD1 :MX mode2(refer to segment driver direction select)
Mirror Y: COM bi-direction selection (refer to pad center coordinates).
TMY connect to VSS: MY mode1(refer to common driver direction select)
TMY connect to VDD1: MY mode2(refer to common driver direction select)
Test pin.
TMX
TMY
DA
I
I
1
1
Must fix to “L”
Recommended I/O PIN ITO Resistance Limitation
PIN Name
ITO Resister
PS[1:0],OSC,CP,BR
T0~T12,VRS
<5KΩ
Floating
<100Ω
<500Ω
<1KΩ
VDD1, VDD2, VSS
V0, VG , VM , XV0
A0,/WR,/RD,/CSB, D0 …D7
/RESB
RESB<10KΩ
Ver 1.1
9/39
2009/07/17
ST7033
7. FUNCTIONS DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input
There is /CSB pin for chip selection. The ST7033 can interface with an MPU when /CSB is "L". When /CSB is “H”, the
internal shift register and the counter are reset.
Parallel / Serial Interface
ST7033 has five types of interface with an MPU, which are three serial and two parallel interfaces. This parallel or serial
interface is determined by PS [1:0] pin as shown in Table 1.
PS1 PS0
/CSB
/CSB
/CSB
/CSB
/CSB
A0
A0
State
H
H
L
H
L
8080-series parallel MPU interface
6800-series parallel MPU interface
4 Pin-SPI MPU interface
A0
H
L
A0
L
" * "
3 Pin-SPI MPU interface
Table 1. Parallel/Serial Interface Mode
Parallel Interface
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS1~PS0 as shown in
Table 2. The type of data transfer is determined by signals at A0, /RD (E) and /WR(R/W) as shown in Table 3.
PS1
H
PS0 /CSB
A0
A0
A0
/RD (E) /WR (R/W) DB0 to DB7
MPU bus
8080-series
6800-series
H
L
/CSB
/CSB
/RD
E
/WR
R/W
DB0 to DB7
DB0 to DB7
H
Table 2. Microprocessor Selection for Parallel Interface
Common
6800-series
8080-series
Description
A0
H
H
L
E
H
H
H
H
R/W
/RD
L
/WR
H
H
L
Display data read out
Display data write
H
L
H
L
L
H
Register status read
L
H
L
Writes to internal register (instruction)
Table 3. Parallel Data Transfer
NOTE: By fixing /RD (E) pin at high (VDD1) in 6800-series interface mode, /CSB can be used as enable signal. In this case,
interface data is latched at the rising edge of /CSB and the access type is determined by signals on A0, /WR(R/W) just
same as 6800-series mode.
Ver 1.1
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ST7033
Serial Interface
Serial Mode
PS1
PS0
/CSB
A0
4-line SPI interface
L
H
/CSB
Used
Not Used
Fix to “H”
3-line SPI interface
L
L
/CSB
Table 4. Microprocessor Selection for Serial Interface
PS1= “L”, PS0= “H”: 4-line SPI interface
When the ST7033 is active (/CSB=”L”), serial data (D1) and serial clock (D0) inputs are enabled. When /CSB is “High”, the
internal 8-bit shift register and the 3-bit counter are reset. The display data/command indication is controlled by the register
selection pin (A0). The signals transferred on data bus will be display data when A0 is high and will be instruction when A0
is low. The read feature is not supported in this mode. Serial data on SDA (D1) is latched at the rising edge of serial clock
on SCLK (D0). After the eighth serial clock, the serial data will be processed as 8-bit parallel data. The DDRAM column
address pointer will be increased by one automatically after each byte of DDRAM access.
Figure 2. 4-Line SPI Timing
3-line SPI interface
When ST7033 is active (/CSB=”L”), SDA-out, SDA-in and SCL inputs are enabled. When ST7033 is not active (/CSB=”H”),
the internal 8-bit shift register and the 3-bit counter are reset. The A0 pin is not available in this mode. Before issuing serial
data, an A0 bit is required to indicate the access is data or instruction. The read feature is not supported in this mode except
ID code read feature. Serial data on SDA (D1) is latched at the rising edge of serial clock on SCLK (D0). After the eighth
serial clock, the serial data will be processed as 8-bit parallel data. The DDRAM column address pointer will be increased
by one automatically after each byte of DDRAM access.
Figure 3. 3-Line SPI Timing
Ver 1.1
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ST7033
DISPLAY DATA RAM (DDRAM)
The ST7033 contains a 4x96 bit static RAM that stores the display data. The display data RAM store the dot data for the
LCD.It is 4-row by 96-column addressable array. Each pixel can be selected when the column addresses are
specified.Data are written to ram directly through D0 to D3 and D4 to D7 are disabled bits. The display data from the
microprocessor correspond to the LCD common lines. The microprocessor can write to RAM through the I/O buffer. Since
the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed
without causing the LCD flicker.
Line Address Circuit
This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line
Address repeatedly.At the beginning of each LCD frame, the contents of register are copied to the line counter which is
increased by CL signal and generates the line address for transferring the 96-bit RAM data to the display data latch circuit.
Column Address Circuit
Column Address Circuit has an 8-bit preset counter that provides Column Address to the Display Data RAM. The display
data RAM column address is specified by the Column Address Set command. The specified column address is
incremented (+1) with each display data write command. This allows the MPU display data to be accessed continuously.
ADDRESSING
Data is downloaded in bytes into the RAM matrix of ST7033 as indicated in Figure 4. The display RAM has a matrix of 4 by
96 bits. The address pointer addresses the columns. The column address ranges are: 0 to 95 (1011111), .Addresses
outside these ranges are not allowed. After the last column address (95) wraps around to 0 .
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ST7033
Data Structure
Line
Address
COM output
Start
D0
D1
D2
D3
D4
D5
D6
D7
00H
01H
02H
03H
COM0 COM3
COM1 COM2
COM2 COM1
COM3 COM0
……
Data
Normal
direction direction
MY=0 MY=1
Reverse
D4~D7 are disabled bits
Column Address
……
Start
Normal
direction
MX=0
……
……
SEG
output
Reverse
direction
MX=1
Figure 4. Display Data RAM Map (1/4 Duty)
Ver 1.1
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ST7033
LCD layout reference
Layout method
LCD SEG
LCD COM
Display RAM filling order
SEGn+2
COM0
a
SEGn
SEGn+1 SEGn+2
SEGn+3 SEGn+4 SEGn+5
SEGn+6 SEGn+7
SEGn+1
f
b
c
COM0
COM1
COM2
COM3
c
x
x
x
b
a
x
x
x
f
x
x
x
g
x
x
x
e
x
x
x
d
x
x
x
DP
x
SEGn+3
SEGn+4
g
x
Method 1
SEGn
SEGn+5
SEGn+6
e
x
x
x
SEGn+7
d
x
DP
SEGn
COM0
a
SEGn
SEGn+1 SEGn+2
SEGn+3
b
c
f
COM0
COM1
COM2
COM3
a
b
x
x
f
e
c
x
x
d
DP
x
SEGn+1
Method 2
g
g
x
x
SEGn+2
SEGn+3
e
COM1
d
x
DP
SEGn+1
SEGn+2
COM0
COM1
a
SEGn
SEGn+1 SEGn+2
SEGn
f
b
c
b
DP
c
a
d
g
x
f
COM0
COM1
COM2
COM3
g
e
x
x
Method 3
e
COM2
d
x
DP
SEGn
COM0
COM1
a
SEGn
SEGn+1
COM2
COM3
b
c
f
a
c
f
COM0
COM1
COM2
COM3
g
e
g
d
Method 4
e
b
SEGn+1
d
DP
DP
Figure 5. Relationships between LCD layout and display RAM filling order and display data
Notes 1 ’ x ‘= data bit unchanged.
：
：
Notes 2 ST7033 is always operating in 1/4 duty.
Ver 1.1
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ST7033
LCD DRIVER CIRCUIT
4-channel common drivers and 96-channel segment drivers configure this driver circuit. This LCD panel driver voltage
depends on the combination of display data and frame (positive or negative).
Figure 6. LCD Driver Waveforms
Liquid Crystal Driver Power Circuit
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power
consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage
follower circuits. They are controlled by power control instruction.
Figure 7. External Components on V0, XV0 and VG
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ST7033
8. RESET CIRCUIT
Setting /RESB to “L” or Reset instruction can initialize internal function.
When /RESB becomes “L”, following procedure is occurred.
Power save mode is entered
--Oscillator circuit is stopped
--The LCD power supply circuit is stopped
--Display OFF
--Display all point ON
--Segment/Common output go to the VSS level
Display normal
Column address: 0
Common scan direction : MY=0
Segment scan direction : MX=0
Power control [VB VR VF]=0
Booster: CP pad
Ver 1.1
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ST7033
9-1. INSTRUCTION TABLE
CODE
D4
COMMAND
DESCRIPTION
A0
D7
D6
D5
D3
D2
D1
D0
D0 Write data to RAM
Display data write
Display ON/OFF
1
D7
D6
D5
D4
D3
D2
D1
0
1
0
1
0
1
LCD display
0:OFF,1:ON
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
1
0
1
1
1
1
Display
LCD display
0:normal;1:reverse
LCD display
0:normal;1:all points ON
Set the DDRAM page
address
normal/reverse
Display all points
ON/OFF
0
1
0
Page address set
0
0
0
0
Column address set
Upper 3-bit address
Column address set
Lower 4-bit address
*
X6
X2
X5
X1
X4
X0
Set the DDRAM column
address
X3
Sets the correspondence
between the DDRAM column
address and the SEG driver
output
Segment driver
direction select
0
0
1
1
0
1
1
0
0
0
0
0
*
0
*
MX
*
Sets the correspondence
between the DDRAM line
address and the COM driver
output
Common driver
direction select
MY
Set the on-chip power supply
circuit operation mode
Compound command of
Display OFF and
Power control set
Power save mode
0
-
0
-
0
-
1
-
0
-
1
-
VB
-
VR
-
VF
-
Display-all-points-ON
Software reset
Reset
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
0
1
0
1
0
0
0
1
0
0
0
0
1
0
1
1
0
0
0
0
1
1
0
0
NOP
No operation
Enter mode set
Duty mode set
Finish mode set
Enter mode set
Set 1/4 duty
Finish mode set
Notes: “*” = Disabled bit
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ST7033
9-2. INSTRUCTION DESCRIPTION
Display data Write
8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address .
The column address is increased by 1 automatically so that the microprocessor can continuously write data . During
auto-increment, the column address wraps to 0 after the last column is written.
A0
D7
D6
D5
D4
D3
D2
D1
D0
Description
1
Write data
Write to the DDRAM
Display ON/OFF
This command turns the display ON and OFF.
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
Description
Display OFF
Display ON
0
1
0
1
0
1
1
1
1
Display Normal/Reverse
This command can reserve the lit and unlit without overwriting the content of the DDRAM.
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
Description
LCD ON Voltage
LCD OFF Voltage
0
1
0
1
0
0
1
1
1
Display All Points ON/OFF
The command makes it possible to force all display points ON regardless of the content of the DDRAM. Even when this is
done, the DDRAM contents are maintained. This command takes priority over the Display normal/reverse command.
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
Description
Normal Display Mode
Display All Points ON
0
1
0
1
0
0
1
0
1
When the Display all points ON command is executed when in the Display OFF mode, Power Save mode is entered. See
the “Power Save mode” for detail.
Page Address Set
This command specifies the start page address of the DDRAM.
A0
D7
D6
D5
D4
D3
D2
D1
D0
Description
0
1
0
1
1
0
0
0
0
Ser page address
Column Address Set
This command specifies the column address of the DDRAM. The column address is split into two sections (the upper 3-bits
and lower 4-bits) when it is set.
Each time the DDRAM is accessed, the column address automatically increments by +1, imaging it possible for the MCU to
continuously access to the display data. After the last column address (5FH), column address returns to 00H.
A0
D7
D6
D5
D4
1
D3
*
D2
X6
X2
D1
X5
X1
D0
X4
X0
Description
Upper bit address
Lower bit address
0
0
0
0
0
X3
Notes:’ * ‘Disabled bit
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ST7033
X6
0
0
0
0
:
X5
0
0
0
0
:
X4
0
0
0
0
:
X3
0
0
0
0
:
X2
0
0
0
0
:
X1
0
0
1
1
:
X0
0
1
0
1
:
Column Address
0
1
2
3
:
1
1
0
0
1
1
1
1
1
1
1
1
0
1
94
95
Segment Driver Direction Select
This command can reverse the correspondence between the DDRAM column address and the segment driver output
A0
D7
D6
D5
D4
D3
D2
D1
D0
Description
MX=0 SEG95 SEG0
→
TMX=VSS
MX mode 1
TMX=VDD1
MX mode 2
→
MX=1 SEG0 SEG95
0
1
0
1
0
0
0
0
MX
→
MX=0 SEG0
SEG95
→
MX=1 SEG95
SEG0
Common Driver Direction Select
This command can reverse the correspondence between the DDRAM line address and the common driver output
A0
D7
D6
D5
D4
D3
D2
D1
D0
Description
MY=0 COM0→ COM67
TMY=VSS
MY mode 1
TMY=VDD1
MY mode 2
MY=1 COM67→ COM0
MY=0 COM67→ COM0
MY=1 COM0→ COM67
0
1
1
0
0
MY
*
*
*
Notes1:’ * ‘Disabled bit
Power control set
This command sets the on-chip power supply function ON/OFF.
A0
D7
D6
D5
D4
D3
D2
D1
D0
Description
Booster: OFF
0
0
0
1
Voltage Regulator: OFF
Voltage Follower: OFF
Booster: ON
Voltage Regulator: ON
Voltage Follower: ON
0
0
0
1
0
1
1
1
(D2 : Booster, D1 : Voltage Regulator, D0 : Voltage Follower)
Set 1/4 duty mode (Combinative instructions)
These combinative instructions set the driver into 1/4 duty mode.
Enter mode set
A0
D7
D6
D5
D4
D3
D2
D1
D0
Description
0
1
1
1
1
0
0
0
1
Enter mode set
Duty mode set
A0
D7
D6
D5
D4
D3
D2
D1
D0
Description
0
1
0
1
0
1
1
0
0
Set 1/4 duty
Finish mode set
A0
D7
D6
D5
D4
D3
D2
D1
D0
Description
0
1
1
1
1
0
0
0
0
Finish mode set
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ST7033
Power Save Mode
If the display all points ON command is executed when the display is in display OFF mode, power saver mode is entered.
This mode stops every operation of the LCD display system.
Power save (Display OFF & Display all points ON)
Command
Power save mode
Effect
Power save OFF (Display all points OFF)
Power save mode canceled
Figure 8. Power Save Mode
The internal states in power save mode are as follows:
-The oscillator circuit is stopped
-The LCD driver circuit is stopped
-The LCD driver circuit is stopped and segment/common driver output s to VSS level
-The display data and operation mode before execution of the Power save are held, and the MCU can access to the
DDRAM and internal registers.
Reset
When this command is issued, the driver is initialized. This command doesn’t change DDRAM content.
A0
D7
D6
D5
D4
D3
D2
D1
D0
Description
0
1
1
1
0
0
0
1
0
Software reset
NOP
Non-operation command
A0
D7
D6
D5
D4
D3
D2
D1
D0
Description
0
1
1
1
0
0
0
1
1
No operation
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2009/07/17
ST7033
Command Description
Referential instruction setup flow for power on:
Referential instruction setup flow for power down:
Figure 9. Power On and Power Down Sequence
Ver 1.1
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ST7033
10. LIMITING VALUES
In accordance with the Absolute Maximum Rating System; see notes 1 and 2.
Parameter
Power supply voltage
Power supply voltage
Symbol
Conditions
-0.3 ~ 3.6
Unit
VDD1
VDD2
V
-0.3 ~ 3.6
-0.3 ~ 13.5
0.3 to V0
V
Power supply voltage (VDD2 standard) V0, |XV0|
Power supply voltage (VDD2 standard) VG, VM
V
V
Operating temperature
Storage temperature
TOPR
TSTR
–30 to +80
–65 to +150
°C
°C
Figure 10.
Notes
1. Stresses above those listed under Limiting Values may cause permanent damage to the device.
2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to
VSS unless otherwise noted.
3. Insure that the voltage levels of VG, VM, VSS, and XV0 are always such that
≧
≧
≧
≧
VSS XV0
V0
VG
VM
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ST7033
11. HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices
12. DC CHARACTERISTICS
℃
℃
to +80 ; unless otherwise specified.
VSS = 0 V; Ta = -30
Rating
Typ.
Applicable
Pin
Item
Symbol
Condition
Units
Min.
Max.
Operating Voltage (1)
VDD1
1.65
—
—
3.4
V
VSS
VSS
Operating Voltage (2)
VDD2 (Relative to VSS)
2.5
3.4
V
V
High-level Input Voltage
Low-level Input Voltage
High-level Output Voltage
Low-level Output Voltage
Input leakage current
VIHC
0.7 x VDD1
VSS
—
—
—
—
—
—
VDD1
VILC
0.3 x VDD1 V
VDD1
0.2 x VDD1 V
VOHC IOH=1mA
0.8 x VDD1
VSS
V
VOLC IOL1mA
μ
ILI
–1.0
1.0
3.0
A
A
μ
Output leakage current
ILO
–3.0
V0 =9.0 V
VG = 2.0 V
—
—
0.8
0.9
—
—
Liquid Crystal Driver ON
Resistance
Ta= 25°C
SEGn
COMn
Ω
K
RON
FR
△
V=10%
Frame frequency
—
70
—
Hz
Supply Step-up output
voltage Circuit
V0
(V0 To VSS)
—
—
4
—
—
V
V0
Voltage regulator Circuit
Operating Voltage
XV0
(VG To XV0)
-4
V
XV0
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ST7033
Dynamic Consumption Current :
During Display, with the Internal Power Supply ON Current consumed by total ICs(bare die)
Rating
Test pattern
Symbol
Condition
Units
Notes
Min.
Typ.
Max.
μ
A
Power Down
ISS
Ta = 25°C
—
1.0
10
Notes to the DC characteristics
1. The maximum possible V0 oltage that may be generated is dependent on voltage, temperature and (display) load.
2. During power down all static currents are switched off.
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ST7033
13. TIMING CHARACTERISTICS
System Bus Read/Write Characteristics 1 (For the 8080 Series MPU)
A0
t
AW8
tAH8
tAS8
/CSB
tCYC8
t
CCLR,tCCLW
WR,RD
t
CCHR,tCCHW
tDH8
t
DS8
D0 to D7
(Write)
t
ACC8
tOH8
D0 to D7
(Read)
Figure 11. Parallel 8080 Series Interface Characteristics
°
(VDD1 = 3.3V , Ta =25 C)
Rating
Units
Item
Signal
Symbol
tAH8
Condition
Min.
Max.
Address hold time
10
—
Address setup time
tAW8
tAS8
80
—
A0
Address setup time
60
—
System cycle time
tCYC8
tCCLW
tCCHW
tDS8
350
70
—
ns
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
WRITE Data setup time
WRITE Address hold time
—
/WR
50
—
60
—
D0 to D7
tDH8
50
—
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ST7033
(VDD1 = 2.8V , Ta =25°C )
Rating
Units
Item
Signal
Symbol
tAH8
Condition
Min.
Max.
Address hold time
15
—
Address setup time
tAW8
tAS8
120
80
—
A0
Address setup time
—
System cycle time
tCYC8
tCCLW
tCCHW
tDS8
450
120
100
90
—
ns
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
WRITE Data setup time
WRITE Address hold time
—
/WR
—
—
D0 to D7
tDH8
60
—
(VDD1 = 1.8V , Ta =25°C)
Rating
Units
Item
Signal
Symbol
Condition
Min.
Max.
Address hold time
tAH8
30
—
Address setup time
tAW8
tAS8
150
100
550
170
150
120
70
—
A0
Address setup time
—
System cycle time
tCYC8
tCCLW
tCCHW
tDS8
—
ns
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
WRITE Data setup time
WRITE Address hold time
—
/WR
—
—
D0 to D7
tDH8
—
Notes1:The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely
≦
≦
(tCYC8 – tCCLR – tCCHR) are specified.
fast,(tr +tf)
Notes2: All timing is specified using 20% and 80% of VDD1 as the reference.
Notes3: tCCLW and tCCLR are specified as the overlap between /CSB being “L” and /WR and /RD being at the “L” level.
(tCYC8 – tCCLW – tCCHW) for (tr + tf)
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System Bus Read/Write Characteristics 1 (For the 6800 Series MPU)
A0
R/W
tAW6
tAH6
/CSB
tCYC6
tEWHR, tEWHW
E
tEWLR, tEWLW
tDH6
tDS6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
Figure 12. Parallel 6800 Series Interface Characteristics
(VDD1 = 3.3V , Ta =25°C)
Rating
Item
Signal
Symbol
tAH6
Condition
Units
Min.
10
Max.
—
Address hold time
Address setup time
System cycle time
A0
tAW6
80
—
R/W
tCYC6
tEWLW
tEWHW
tDS6
240
70
—
ns
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
WRITE Data setup time
—
E
50
—
60
—
D0 to D7
WRITE Address hold time
tDH6
50
—
Ver 1.1
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°
(VDD1 = 2.8V , Ta =25 C)
Rating
Units
Item
Signal
Symbol
tAH6
Condition
Min.
Max.
Address hold time
15
—
A0
Address setup time
tAW6
100
340
120
100
120
60
—
R/W
System cycle time
tCYC6
tEWLW
tEWHW
tDS6
—
ns
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
WRITE Data setup time
WRITE Address hold time
—
E
—
—
D0 to D7
tDH6
—
(VDD1 = 1.8V , Ta =25°C)
Rating
Units
Item
Signal
Symbol
Condition
Min.
Max.
Address hold time
tAH6
30
—
A0
Address setup time
tAW6
150
440
170
150
180
70
—
R/W
System cycle time
tCYC6
tEWLW
tEWHW
tDS6
—
ns
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
WRITE Data setup time
WRITE Address hold time
—
E
—
—
D0 to D7
tDH6
—
Notes1:The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely
≦
≦
(tCYC6 – tEWLR – tEWHR) are specified.
fast,(tr +tf)
Notes2:All timing is specified using 20% and 80% of VDD1 as the reference.
Notes3:tEWLW and tEWLR are specified as the overlap between /CSB being “L” and E.
(tCYC6 – tEWLW – tEWHW) for (tr + tf)
Ver 1.1
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ST7033
SERIAL INTERFACE (4-Line Interface)
t
CSS
tCSH
/CSB
t
SAS
tSAH
A0
t
SCYC
t
SLW
SCLK
t
SHW
t
f
t
r
t
SDS
tSDH
SDA
Figure 13. 4- Line Serial Interface Characteristics
(VDD1 = 3.3V , Ta =25°C )
Rating
Units
Item
Signal
Symbol
tSCYC
Condition
Min.
Max.
Serial Clock Period
120
—
SCLK
SCL “H” pulse width
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
Data hold time
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
60
60
20
90
20
10
20
120
—
—
—
—
—
—
—
—
A0
ns
SDA
/CSB
CS-SCL time
CS-SCL time
(VDD1 = 2.8V , Ta =-25°C)
Rating
Units
Item
Signal
Symbol
Condition
Min.
200
100
100
30
Max.
—
Serial Clock Period
SCL “H” pulse width
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
Data hold time
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
SCLK
—
—
—
A0
ns
120
30
—
—
SDA
/CSB
20
—
CS-SCL time
30
—
CS-SCL time
150
—
Ver 1.1
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ST7033
(VDD1 = 1.8V , Ta =25°C)
Rating
Units
Item
Signal
Symbol
tSCYC
Condition
Min.
280
140
140
50
Max.
—
Serial Clock Period
SCL “H” pulse width
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
Data hold time
SCLK
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
—
—
—
A0
ns
150
50
—
—
SDA
/CSB
50
—
CS-SCL time
40
—
CS-SCL time
180
—
Notes1: The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
Notes2: All timing is specified using 20% and 80% of VDD1 as the standard.
Ver 1.1
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ST7033
SERIAL INTERFACE (3-Line Interface)
Figure 14. 3- Line Serial Interface Characteristics
℃
(VDD1=3.3V ,Ta=25
)
Rating
Item
Signal
Symbol
Condition
Units
Min.
Max.
Serial Clock Period(Write)
SCL “H” pulse width(Write)
SCL “L” pulse width(Write)
Data setup time
tSCYC
tSHW
tSLW
tSDS
tSDH
tCSS
tCSH
120
60
60
30
30
30
30
10
30
—
—
—
—
—
—
—
—
—
SCLK
SDAIN
/CSB
ns
Data hold time
CS-SCL time
CS-SCL time
SCL-CS
/CSB tSCC
/CSB tCHW
CS “H” pulse width
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ST7033
℃
(VDD1=2.8V ,Ta=25
)
Rating
Item
Signal
Symbol
Condition
Units
Min.
Max.
Serial Clock Period(Write)
SCL “H” pulse width(Write)
SCL “L” pulse width(Write)
Data setup time
tSCYC
tSHW
tSLW
tSDS
tSDH
tCSS
tCSH
180
90
90
40
40
40
40
15
35
—
—
—
—
—
—
—
—
—
SCLK
SDAIN
/CSB
ns
Data hold time
CS-SCL time
CS-SCL time
SCL-CS
/CSB tSCC
/CSB tCHW
CS “H” pulse width
℃
(VDD1=1.8V ,Ta=25
)
Rating
Item
Signal
Symbol
Condition
Units
Min.
Max.
Serial Clock Period(Write)
SCL “H” pulse width(Write)
SCL “L” pulse width(Write)
Data setup time
tSCYC
tSHW
tSLW
tSDS
tSDH
tCSS
tCSH
250
100
100
60
—
—
—
—
—
—
—
—
—
SCLK
SDAIN
/CSB
ns
Data hold time
60
CS-SCL time
60
CS-SCL time
65
SCL-CS
/CSB tSCC
/CSB tCHW
20
CS “H” pulse width
45
Notes1:The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
Notes2:All timing is specified using 30% and 70% of VDD1 as the standard.
Ver 1.1
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ST7033
14. RESET TIMING
tRJ
t
RW
/RESB
tR
Internal
status
During reset
Reset complete
Figure 15. Reset Timing Characteristics
(VDD1 = 3.3V , Ta = 25°C )
Rating
Units
Item
Signal Symbol
Condition
Condition
Condition
Min.
20
2
Typ.
—
Max.
—
Reset time
/RESB tR
us
us
us
Reset “L” pulse width
/RESB tRW
—
—
Reset rejection (for noise spike) /RESB tRJ
—
—
1
(VDD1 = 2.8V , Ta =25°C )
Rating
Units
Item
Signal Symbol
Min.
20
2
Typ.
—
Max.
—
Reset time
Reset “L” pulse width
/RESB tR
us
us
us
/RESB tRW
—
—
Reset rejection (for noise spike) /RESB tRJ
—
—
1
(VDD1 =1.8V , Ta = 25°C )
Rating
Units
Item
Signal Symbol
Min.
30
3
Typ.
—
Max.
—
Reset time
Reset “L” pulse width
/RESB tR
us
us
us
/RESB tRW
—
—
Reset rejection (for noise spike) /RESB tRJ
—
—
1
Ver 1.1
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ST7033
15. APPLICATION NOTE
.............................................
.............................................
.............................................
..........................................
ST7033
................
.........
IC PAD SIDE
C=1.0uF
C=1.0uF
Figure 16. 6800 Parallel Application
Ver 1.1
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ST7033
.............................................
.............................................
.............................................
..........................................
ST7033
................
.........
IC PAD SIDE
C=1.0uF
C=1.0uF
Figure 17. 8080 Parallel Applicaiton
Ver 1.1
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ST7033
.............................................
.............................................
.............................................
..........................................
ST7033
................
.........
IC PAD SIDE
C=1.0uF
C=1.0uF
Figure 18. 3-Line Serial Application
Ver 1.1
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ST7033
.............................................
.............................................
.............................................
..........................................
ST7033
................
.........
IC PAD SIDE
C=1.0uF
C=1.0uF
Figure 19. 4-Line Serial Application
Ver 1.1
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ST7033
ITO Layout Reference
：
About ITO layout, please refer the following pictures
FPC
PIN
FPC
PIN
FPC
PIN
FPC
PIN
Ver 1.1
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2009/07/17
ST7033
ST7033 Serial Specification Revision History
Description
Version
Date
1.0
1.1
2008/04/18 First Issue Version
2009/07/15 Modify application note
Ver 1.1
39/39
2009/07/17
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