ST7066U [SITRONIX]
Dot Matrix LCD Controller/Driver; 点阵LCD控制器/驱动器
| 型号： | ST7066U |
| 厂家： | 
SITRONIX TECHNOLOGY CO., LTD. |
| 描述： | Dot Matrix LCD Controller/Driver |
| 文件： | 总42页 (文件大小：601K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST
Sitronix
ST7066U
Dot Matrix LCD Controller/Driver
n Features
l
l
5 x 8 and 5 x 11 dot matrix possible
Low power operation support:
-- 2.7 to 5.5V
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16-common x 40-segment liquid crystal
display driver
Programmable duty cycles
l
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Wide range of LCD driver power
-- 3.0 to 10V
Correspond to high speed MPU bus
interface
-- 1/8 for one line of 5 x 8 dots with cursor
-- 1/11 for one line of 5 x 11 dots & cursor
-- 1/16 for two lines of 5 x 8 dots & cursor
Wide range of instruction functions:
Display clear, cursor home, display on/off,
cursor on/off, display character blink, cursor
shift, display shift
Automatic reset circuit that initializes the
controller/driver after power on
Internal oscillator with external resistors
Low power consumption
l
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-- 2 MHz (when VCC = 5V)
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4-bit or 8-bit MPU interface enabled
80 x 8-bit display RAM (80 characters max.)
13,200-bit character generator ROM for a
total of 240 character fonts(5 x 8 dot or 5 x 11
dot)
64 x 8-bit character generator RAM
-- 8 character fonts (5 x 8 dot)
-- 4 character fonts (5 x 11 dot)
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QFP80 and Bare Chip available
n Description
The ST7066U dot-matrix liquid crystal display
controller and driver LSI displays alphanumeric,
Japanese kana characters, and symbols. It can be
configured to drive a dot-matrix liquid crystal display
under the control of a 4- or 8-bit microprocessor.
Since all the functions such as display RAM,
character generator, and liquid crystal driver, required
for driving a dot-matrix liquid crystal display are
internally provided on one chip, a minimal system can
be interfaced with this controller/driver.
total of 240 different character fonts. The low power
supply (2.7V to 5.5V) of the ST7066U is suitable for
any portable battery-driven product requiring low
power dissipation.
The ST7066U LCD driver consists of 16 common
signal drivers and 40 segment signal drivers which
can extend display size by cascading segment driver
ST7065 or ST7063. The maximum display size can
be either 80 characters in 1-line display or 40
characters in 2-line display. A single ST7066U can
display up to one 8-character line or two 8-character
lines.
The ST7066U character generator ROM is extended
to generate 240 5x8(5x11) dot character fonts for a
Product Name
Support Character
ST7066U-0A
ST7066U-0B
ST7066U-0E
English / Japan
English / European
English / European
V2.2
1/42
2006/05/11
ST7066U
ST7066 Serial Specification Revision History
Version
Date
Description
1. Added 8051 Example Program Code(Page 21,23)
2. Added Annotated Flow Chart :
1.7
2000/10/31
“BF cannot be checked before this instruction”
3. Changed Maximum Ratings
Power Supply Voltage:+5.5V →+7.0V(Page 28)
1.8
2000/11/14 Added QFP Pad Configuration(Page 5)
1. Moved QFP Package Dimensions(Page 39) to
Page 5
1.8a
2000/11/30
2. Changed DC Characteristics Ratings(Page
32,33)
2.0
2.1
2.2
2001/03/01 Transition to ST7066U
1. Add Power Supply Conditions (Page 31);
2006/04/10
2. Modify reset description on Page 22.
2006/05/11 Emphasis checking BF procedure (Page 9, 27, 28).
V2.2
2/42
2006/05/11
ST7066U
n Block Diagram
OSC1 OSC2
CPG
CL1
CL2
M
Reset
circuit
Timing
generator
Instruction
register(IR)
D
Instruction
decoder
Display data
RAM
(DDRAM)
80x8 bits
COM1 to
COM16
16-bit
shift
register
Common
signal
driver
RS
RW
E
MPU
interface
Address
counter
SEG1 to
SEG40
40-bit
shift
register
40-bit
latch
circuit
Segment
signal
driver
Data
register
(DR)
DB4 to
DB7
LCD drive
voltage
selector
Input/
output
buffer
DB0 to
DB3
Busy
flag
Character
generator
RAM
(CGRAM)
64 bytes
Character
generator
ROM
(CGROM)
13,200 bits
Cursor
and
blink
controller
GND
Parallel/serial converter
and
attribute circuit
Vcc
V1 V2 V3 V4 V5
V2.2
3/42
2006/05/11
ST7066U
n Pad Arrangement
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG09
SEG08
SEG07
SEG06
SEG05
SEG04
SEG03
SEG02
SEG01
GND
SEG39
SEG40
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM09
COM08
COM07
COM06
COM05
COM04
COM03
COM02
COM01
DB7
1
2
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
63
ST7066U
3
62
4
61
60
59
58
57
5
6
7
8
9
56
(0,0)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
55
54
53
Chip Size : 2300x3000μm
52
Coordinate : Pad Center
Origin : Chip Center
51
Min Pad Pitch : 120μm
50
Pad Size : 96x96μm
49
48
47
46
45
44
43
42
DB6
DB5
DB4
DB3
OSC1
DB2
24 25 26 27 28 29 30 31 32 33
3
35 36 37 38 39 40 41
Substrate Connect to VDD.
V2.2
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2006/05/11
ST7066U
n Package Dimensions
V2.2
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2006/05/11
ST7066U
n Pad Configuration(80 QFP)
S
2
3
S
2
4
S
2
5
S
2
6
S
2
7
S
2
8
S
2
9
S
3
0
S
3
1
S
3
2
S
3
3
S
3
4
S
3
5
S
3
6
S
3
7
S
3
8
8
0
7
9
7
8
7
7
7
6
7
5
7
4
7
3
7
2
7
1
7
0
6
9
6
8
6
7
6
6
6
5
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S09
S08
S07
S06
S05
S04
S03
S02
S01
GND
OSC1
1
2
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
S39
S40
3
C16
C15
C14
C13
C12
C11
C10
C09
C08
C07
C06
C05
C04
C03
C02
C01
DB7
DB6
DB5
DB4
DB3
DB2
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
O
S
C
2
C
L
1
C
L
2
V
C
C
D
B
0
D
B
1
M
D
E
V
1
V
2
V
3
V
4
V
5
R
S
R
W
V2.2
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2006/05/11
ST7066U
n Pad Location Coordinates
Pad No. Function
X
Y
Pad No. Function
X
Y
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
DB2
1040
1040
1040
1040
1040
1040
1040
1040
1040
1040
1040
1040
1040
1040
1040
1040
1040
1040
1040
1040
1040
1040
1040
1040
910
-1400
-1270
-1140
-1020
-900
-780
-660
-540
-420
-300
-180
-60
1
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
GND
OSC1
OSC2
V1
-1040
-1040
-1040
-1040
-1040
-1040
-1040
-1040
-1040
-1040
-1040
-1040
-1040
-1040
-1040
-1040
-1040
-1040
-1040
-1040
-1040
-1040
-1040
-1040
-910
1400
1270
1140
1020
900
DB3
2
DB4
3
DB5
4
DB6
5
DB7
6
780
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
7
660
8
540
9
420
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
300
180
60
60
-60
180
-180
-300
-420
-540
-660
-780
-900
-1020
-1140
-1270
-1400
-1400
-1400
-1400
-1400
-1400
-1400
-1400
-1400
-1400
-1400
-1400
-1400
-1400
-1400
-1400
-1400
300
420
540
660
780
900
1020
1140
1270
1400
1400
1400
1400
1400
1400
1400
1400
1400
1400
1400
1400
1400
1400
1400
1400
1400
780
-780
660
V2
-660
540
V3
-540
420
V4
-420
300
V5
-300
180
CL1
-180
60
CL2
-60
-60
Vcc
60
-180
-300
-420
-540
-660
-780
-910
M
180
D
300
RS
420
RW
540
E
660
DB0
780
DB1
910
V2.2
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2006/05/11
ST7066U
n Pin Function
Name
Number I/O Interfaced with
Function
Select registers.
0: Instruction register (for write) Busy flag:
address counter (for read)
RS
1
I
MPU
1: Data register (for write and read)
Select read or write.
0: Write
R/W
E
1
1
I
I
MPU
MPU
1: Read
Starts data read/write.
Four high order bi-directional tristate data bus
pins. Used for data transfer and receive
between the MPU and the ST7066U. DB7 can
DB4 to DB7
DB0 to DB3
4
4
I/O
I/O
MPU
be used as a busy flag.
Four low order bi-directional tristate data bus
pins. Used for data transfer and receive
between the MPU and the ST7066U.
MPU
These pins are not used during 4-bit operation.
Clock to latch serial data D sent to the
extension driver
CL1
CL2
M
1
1
1
O
O
O
Extension driver
Extension driver Clock to shift serial data D
Switch signal for converting the liquid crystal
Extension driver
Extension driver
drive waveform to AC
Character pattern data corresponding to each
D
1
O
segment signal
Common signals that are not used are changed
to non-selection waveform. COM9 to COM16
are non-selection waveforms at 1/8 duty factor
and COM12 to COM16 are non-selection
COM1 to
COM16
O
16
LCD
waveforms at 1/11 duty factor.
Segment signals
SEG1 to
SEG40
40
O
LCD
Power supply for LCD drive
V1 to V5
5
2
-
-
Power supply
Power supply
VCC - V5 = 10 V (Max)
VCC , GND
V
CC : 2.7V to 5.5V, GND: 0V
When crystal oscillation is performed, a resistor
must be connected externally. When the pin
Oscillation
OSC1, OSC2
2
resistor clock
input is an external clock, it must be input to OSC1.
Note:
1. Vcc>=V1>=V2>=V3>=V4>=V5 must be maintained
2. Two clock options:
R=91KΩ (Vcc=5V)
R=75KΩ (Vcc=3V)
OSC1
OSC2
OSC1
OSC2
R
Clock input
V2.2
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2006/05/11
ST7066U
n Function Description
l
System Interface
This chip has all two kinds of interface type with MPU : 4-bit bus and 8-bit bus. 4-bit bus or 8-bit bus is selected
by DL bit in the instruction register.
During read or write operation, two 8-bit registers are used. One is data register (DR), the other is instruction
register(IR).
The data register(DR) is used as temporary data storage place for being written into or read from
DDRAM/CGRAM, target RAM is selected by RAM address setting instruction. Each internal operation, reading
from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the data in the next
DDRAM/CGRAM address is transferred into DR automatically. Also after MPU writes data to DR, the data in DR
is transferred into DDRAM/CGRAM automatically.
The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to
read instruction data.
To select register, use RS input pin in 4-bit/8-bit bus mode.
RS R/W
Operation
InstructionWriteoperation(MPUwritesInstructioncode
into IR)
L
L
L
H
H
H
L
H
Read Busy Flag(DB7) and address counter (DB0 ~ DB6)
Data Write operation (MPU writes data into DR)
Data Read operation (MPU reads data from DR)
Table 1. Various kinds of operations according to RS and R/W bits.
l
Busy Flag (BF)
When BF = "High”, it indicates that the internal operation is being processed. So during this time the next
instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation),
through DB7 port. Before executing the next instruction, be sure that BF is not High. Before checking BF, be
sure to wait at least 80us. Please refer to Page 27 for the example. Do NOT keep “E” always “High” for
checking BF.
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Address Counter (AC)
Address Counter(AC) stores DDRAM/CGRAM address, transferred from IR.
After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1.
When RS = "Low" and R/W = "High", AC can be read through DB0 ~ DB6 ports.
V2.2
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2006/05/11
ST7066U
l
Display Data RAM (DDRAM)
Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended capacity is 80
x 8 bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used as
general data RAM. See Figure 1 for the relationships between DDRAM addresses and positions on the liquid
crystal display.
The DDRAM address (ADD ) is set in the address counter (AC) as hexadecimal.
Ø
1-line display (N = 0) (Figure 2)
When there are fewer than 80 display characters, the display begins at the head position. For
example, if using only the ST7066U, 8 characters are displayed. See Figure 3.
When the display shift operation is performed, the DDRAM address shifts. See Figure 3.
High Order
bits
Low Order
bits
Example: DDRAM Address 4F
AC
AC6 AC5 AC4 AC3 AC2 AC1 AC0
1
0
0
1
1
1
1
Figure 1 DDRAM Address
Display
Position
(Digit)
1
2
3
4
5
6
78 79 80
4D 4E 4F
00 01 02 03 04 05
………………..
DDRAM Address
Figure 2 1-Line Display
Display
Position
1
2
3
4
5
6
7
8
00 01 02 03 04 05 06 07
DDRAM
Address
For
01 02 03 04 05 06 07 08
4F 00 01 02 03 04 05 06
Shift Left
For
Shift Right
Figure 3 1-Line by 8-Character Display Example
Ø
2-line display (N = 1) (Figure 4)
Case 1: When the number of display characters is less than 40 × 2 lines, the two lines are displayed from the head. Note
that the first line end address and the second line start address are not consecutive. For example, when just the
ST7066U is used, 8 characters × 2 lines are displayed. See Figure 5.
V2.2
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2006/05/11
ST7066U
When display shift operation is performed, the DDRAM address shifts. See Figure 5.
Display
Position
38
39
40
1
2
3
4
5
6
00 01 02 03 04 05
40 41 42 43 44 45
………………..
………………..
25 26 27
65 66 67
DDRAM
Address
(hexadecimal)
Figure 4 2-Line Display
Display
Position
1
2
3
4
5
6
7
8
00 01 02 03 04 05 06 07
40 41 42 43 44 45 46 47
DDRAM
Address
01 02 03 04 05 06 07 08
41 42 43 44 45 46 47 48
For
Shift Left
For
Shift Right
27 00 01 02 03 04 05 06
67 40 41 42 43 44 45 46
Figure 5 2-Line by 8-Character Display Example
Case 2: For a 16-character × 2-line display, the ST7066U can be extended using one 40-output
extension driver. See Figure 6.
When display shift operation is performed, the DDRAM address shifts. See Figure 6.
Display
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Position
DDRAM
Address
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F
For
Shift
Left
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50
For
Shift
Right
27 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E
67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E
Figure 6 2-Line by 16-Character Display Example
V2.2
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ST7066U
l
Character Generator ROM (CGROM)
The character generator ROM generates 5 x 8 dot or 5 x 11 dot character patterns from 8-bit character codes. It
can generate 240 5 x 8 dot character patterns. User-defined character patterns are also available by
mask-programmed ROM.
l
Character Generator RAM (CGRAM)
In the character generator RAM, the user can rewrite character patterns by program. For 5 x 8 dots, eight
character patterns can be written, and for 5 x 11 dots, four character patterns can be written.
Write into DDRAM the character codes at the addresses shown as the left column of Table 4 to show the
character patterns stored in CGRAM.
See Table 5 for the relationship between CGRAM addresses and data and display patterns. Areas that are not
used for display can be used as general data RAM.
l
Timing Generation Circuit
The timing generation circuit generates timing signals for the operation of internal circuits such as
DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU
access are generated separately to avoid interfering with each other. Therefore, when writing data to
DDRAM, for example, there will be no undesirable interference, such as flickering, in areas other than
the display area.
l
LCD Driver Circuit
LCD Driver circuit has 16 common and 40 segment signals for LCD driving. Data from CGRAM/CGROM is
transferred to 40 bit segment latch serially, and then it is stored to 40 bit shift latch. When each common is
selected by 16 bit common register, segment data also output through segment driver from 40 bit segment latch.
In case of 1-line display mode, COM1 ~ COM8 have 1/8 duty or COM1 ~ COM11 have 1/11duty , and in 2-line
mode, COM1 ~ COM16 have 1/16 duty ratio.
l
Cursor/Blink Control Circuit
It can generate the cursor or blink in the cursor/blink control circuit. The cursor or the blink appears in the digit at
the display data RAM address set in the address counter.
V2.2
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ST7066U
Table 4 Correspondence between Character Codes and Character Patterns (ROM Code: 0A)
V2.2
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ST7066U
Table 4(Cont.) (ROM Code: 0B)
V2.2
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ST7066U
Table 4(Cont.) (ROM Code: 0E)
V2.2
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ST7066U
Character Code
(DDRAM Data)
CGRAM
Address
Character Patterns
(CGRAM Data)
b7 b6 b5 b4 b3 b2 b1 b0 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
1
1
1
1
1
1
0
1
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
-
0
0
0
-
-
-
0
0
0
0
-
0
0
1
-
-
-
Table 5 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character
patterns (CGRAM Data)
Notes:
1. Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types).
2. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the
cursor position and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding
to the cursor display position, at 0 as the cursor display. If the 8th line data is 1, 1 bits will light up the 8th line
regardless of the cursor presence.
3. Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left).
4. As shown Table 5, CGRAM character patterns are selected when character code bits 4 to 7 are
all 0. However, since character code bit 3 has no effect, the R display example above can be selected by either
character code 00H or 08H.
5. 1 for CGRAM data corresponds to display selection and 0 to non-selection.
“-“: Indicates no effect.
V2.2
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ST7066U
n Instructions
There are four categories of instructions that:
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l
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Designate ST7066U functions, such as display format, data length, etc.
Set internal RAM addresses
Perform data transfer with internal RAM
Others
Instruction Table:
Instruction Code
Description
Instruction
Description
Time
(270KHz)
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Write "20H" to DDRAM. and
set DDRAM address to
"00H" from AC
Clear
Display
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
x
1.52 ms
1.52 ms
Set DDRAM address to
"00H" from AC and return
cursor to its original position
if shifted. The contents of
DDRAM are not changed.
Sets cursor move direction
and specifies display shift.
These operations are
performed during data write
and read.
Return
Home
Entry Mode
Set
0
0
0
0
0
0
0
1
1
I/D
S
37 us
D=1:entire display on
C=1:cursor on
Display
ON/OFF
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
D
C
x
B
x
37 us
37 us
37 us
B=1:cursor position on
Set cursor moving and
display shift control bit, and
the direction, without
Cursor or
Display
Shift
S/C R/L
changing DDRAM data.
DL:interface data is 8/4 bits
N:number of line is 2/1
F:font size is 5x11/5x8
Function
Set
0
1
DL
N
F
x
x
Set CGRAM
address
Set CGRAM address in
address counter
0
0
0
0
0
1
AC5 AC4 AC3 AC2 AC1 AC0
37 us
37 us
Set DDRAM
address
Set DDRAM address in
address counter
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Whether during internal
operation or not can be
Read Busy
flag and
address
0
1
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 known by reading BF. The
contents of address counter
0 us
can also be read.
Write data into internal
Write data
to RAM
1
1
0
1
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0 RAM
(DDRAM/CGRAM)
Read data from internal
D0 RAM
(DDRAM/CGRAM)
37 us
37 us
Read data
from RAM
Note:
Be sure the ST7066U is not in the busy state (BF = 0) before sending an instruction from the MPU to the
ST7066U. If an instruction is sent without checking the busy flag, the time between the first instruction and next
instruction will take much longer than the instruction time itself. Refer to Instruction Table for the list of each
instruction execution time.
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ST7066U
n Instruction Description
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Clear Display
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
0
0
0
0
0
1
Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to
"00H" into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge
on first line of the display. Make entry mode increment (I/D = "1").
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Return Home
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
0
0
0
0
1
x
Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter.
Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does
not change.
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Entry Mode Set
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
0
0
0
1
I/D
S
Set the moving direction of cursor and display.
Ø
Ø
I/D : Increment / decrement of DDRAM address (cursor or blink)
When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1.
When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1.
* CGRAM operates the same as DDRAM, when read from or write to CGRAM.
S: Shift of entire display
When DDRAM read (CGRAM read/write) operation or S = "Low", shift of entire display is not performed. If
S = "High" and DDRAM write operation, shift of entire display is performed according to I/D value (I/D =
"1" : shift left, I/D = "0" : shift right).
S
H
H
I/D
H
Description
Shift the display to the left
Shift the display to the right
L
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ST7066U
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Display ON/OFF
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
0
0
1
D
C
B
Control display/cursor/blink ON/OFF 1 bit register.
Ø
Ø
Ø
D : Display ON/OFF control bit
When D = "High", entire display is turned on.
When D = "Low", display is turned off, but display data is remained in DDRAM.
C : Cursor ON/OFF control bit
When C = "High", cursor is turned on.
When C = "Low", cursor is disappeared in current display, but I/D register remains its data.
B : Cursor Blink ON/OFF control bit
When B = "High", cursor blink is on, that performs alternate between all the high data and display
character at the cursor position.
When B = "Low", blink is off.
Cursor or Display Shift
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RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
0
1
S/C R/L
x
x
Without writing or reading of display data, shift right/left cursor position or display. This instruction is used to
correct or search display data. During 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st
line. Note that display shift is performed simultaneously in all the line. When displayed data is shifted
repeatedly, each line shifted individually. When display shift is performed, the contents of address counter are
not changed.
S/C
L
R/L
L
Description
AC Value
AC=AC-1
AC=AC+1
AC=AC
Shift cursor to the left
L
H
Shift cursor to the right
H
L
Shift display to the left. Cursor follows the display shift
H
H
Shift display to the right. Cursor follows the display shift AC=AC
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Function Set
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
0
0
0
0
1
DL
N
F
x
x
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ST7066U
Ø
DL : Interface data length control bit
When DL = "High", it means 8-bit bus mode with MPU.
When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select
8-bit or 4-bit bus mode.
When 4-bit bus mode, it needs to transfer 4-bit data by two times.
Ø
Ø
N : Display line number control bit
When N = "Low", it means 1-line display mode.
When N = "High", 2-line display mode is set.
F : Display font type control bit
When F = "Low", it means 5 x 8 dots format display mode
When F = "High", 5 x11 dots format display mode.
N
L
F
L
No. of Display Lines Character Font Duty Factor
1
1
2
5x8
5x11
5x8
1/8
L
H
x
1/11
1/16
H
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Set CGRAM Address
RS
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
AC5 AC4 AC3 AC2 AC1 AC0
Code
Set CGRAM address to AC.
This instruction makes CGRAM data available from MPU.
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Set DDRAM Address
RS
0
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Code
Set DDRAM address to AC.
This instruction makes DDRAM data available from MPU.
When 1-line display mode (N = 0), DDRAM address is from "00H" to "4FH".
In 2-line display mode (N = 1), DDRAM address in the 1st line is from "00H" to "27H", and
DDRAM address in the 2nd line is from "40H" to "67H".
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ST7066U
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Read Busy Flag and Address
RS
0
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
Code
When BF = “High”, indicates that the internal operation is being processed.So during this time the next
instruction cannot be accepted.
The address Counter (AC) stores DDRAM/CGRAM addresses, transferred from IR.
After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1.
Write Data to CGRAM or DDRAM
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RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
1
0
D7 D6 D5 D4 D3 D2 D1 D0
Write binary 8-bit data to DDRAM/CGRAM.
The selection of RAM from DDRAM, CGRAM, is set by the previous address set instruction
: DDRAM address set, CGRAM address set. RAM set instruction can also determine the AC
direction to RAM.
After write operation, the address is automatically increased/decreased by 1, according to
the entry mode.
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Read Data from CGRAM or DDRAM
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
1
1
D7 D6 D5 D4 D3 D2 D1 D0
Read binary 8-bit data from DDRAM/CGRAM.
The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not
performed before this instruction, the data that read first is invalid, because the direction of AC is not
determined. If you read RAM data several times without RAM address set instruction before read operation,
you can get correct RAM data from the second, but the first data would be incorrect, because there is no time
margin to transfer RAM data.
In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address
set instruction : it also transfer RAM data to output data register. After read operation address counter is
automatically increased/decreased by 1 according to the entry mode. After CGRAM read operation, display
shift may not be executed correctly.
* In case of RAM write operation, after this AC is increased/decreased by 1 like read operation. In this time,
AC indicates the next address position, but you can read only the previous data by read instruction.
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ST7066U
n Reset Function
Initializing by Internal Reset Circuit
An internal reset circuit automatically initializes the ST7066U when the power is turned on. The
following instructions are executed during the initialization. The busy flag (BF) is kept in the busy state
until the initialization ends (BF = 1). The busy state lasts for 40 ms after VCC rises to 4.5 V.
1. Display clear
2. Function set:
DL = 1; 8-bit interface data
N = 0; 1-line display
F = 0; 5x8 dot character font
3. Display on/off control:
D = 0; Display off
C = 0; Cursor off
B = 0; Blinking off
4. Entry mode set:
I/D = 1; Increment by 1
S = 0; No shift
Note:
If the electrical characteristics conditions listed in the table Power Supply Conditions (Page 31) are not met, the
internal reset circuit will not operate normally and will fail to initialize the ST7066U. For such a case, initialization
must be performed by the MPU as explain by the following figures.
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ST7066U
n Initializing by Instruction
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8-bit Interface (fosc=270KHz)
POWER ON
Wait time >40mS
After Vcc >4.5V
Function set
BF cannot be
checked before
this instruction.
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
N
F
X
X
Wait time >37uS
Function set
BF cannot be
checked before
this instruction.
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
N
F
X
X
Wait time >37uS
Display ON/OFF control
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
1
D
C
B
Wait time >37uS
Display clear
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
1
Wait time >1.52mS
Entry mode set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
I/D
0
0
0
0
0
0
0
1
S
Initialization end
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ST7066U
Ø
Initial Program Code Example For 8051 MPU(8 Bit Interface):
;---------------------------------------------------------------------------------
INITIAL_START:
CALL DELAY40mS
MOV A,#38H
;FUNCTION SET
CALL WRINS_NOCHK ;8 bit,N=1,5*7dot
CALL DELAY37uS
MOV A,#38H
;FUNCTION SET
CALL WRINS_NOCHK ;8 bit,N=1,5*7dot
CALL DELAY37uS
MOV A,#0FH
;DISPLAY ON
CALL WRINS_CHK
CALL DELAY37uS
MOV A,#01H
;CLEAR DISPLAY
CALL WRINS_CHK
CALL DELAY1.52mS
MOV A,#06H
;ENTRY MODE SET
CALL WRINS_CHK
CALL DELAY37uS
;CURSOR MOVES TO RIGHT
;---------------------------------------------------------------------------------
MAIN_START:
XXXX
XXXX
XXXX
XXXX
.
.
.
.
;---------------------------------------------------------------------------------
WRINS_CHK:
CALL CHK_BUSY
WRINS_NOCHK:
CLR
CLR
SETB
RS
RW
E
;EX:Port 3.0
;EX:Port 3.1
;EX:Port 3.2
MOV P1,A
CLR
;EX:Port 1=Data Bus
E
MOV P1,#FFH
RET
;For Check Busy Flag
;---------------------------------------------------------------------------------
CHK_BUSY:
CLR
;Check Busy Flag
RS
SETB RW
SETB
JB
CLR
RET
E
P1.7,$
E
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ST7066U
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4-bit Interface (fosc=270KHz)
POWER ON
Wait time >40mS
After Vcc >4.5V
Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
BF cannot be
checked before
0
0
0
0
1
1
X
X
X
X
Wait time >37uS
Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
BF cannot be
checked before
this instruction.
0
0
0
0
0
N
0
F
1
X
0
X
X
X
X
X
X
X
X
X
Wait time >37uS
Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
BF cannot be
checked before
this instruction.
0
0
0
0
0
N
0
F
1
X
0
X
X
X
X
X
X
X
X
X
Wait time >37uS
Display ON/OFF control
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
1
0
D
0
C
0
B
X
X
X
X
X
X
X
X
Wait time >37uS
Display clear
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
0
0
1
X
X
X
X
X
X
X
X
Wait time >1.52mS
Entry mode set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
1
0
I/D
0
S
X
X
X
X
X
X
X
X
Initialization end
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ST7066U
Ø
Initial Program Code Example For 8051 MPU(4 Bit Interface):
;-------------------------------------------------------------------
INITIAL_START:
;-------------------------------------------------------------------
WRINS_CHK:
CALL DELAY40mS
CALL CHK_BUSY
WRINS_NOCHK:
MOV A,#38H
;FUNCTION SET
PUSH
A
CALL WRINS_ONCE ;8 bit,N=1,5*7dot
CALL DELAY37uS
ANL A,#F0H
CLR RS
;EX:Port 3.0
CLR RW
;EX:Port 3.1
MOV A,#28H
;FUNCTION SET
SETB
E
;EX:Port 3.2
CALL WRINS_NOCHK ;4 bit,N=1,5*7dot
CALL DELAY37uS
MOV P1,A
;EX:Port1=Data Bus
CLR
E
A
POP
MOV A,#28H
;FUNCTION SET
SWAP
A
CALL WRINS_NOCHK ;4 bit,N=1,5*7dot
CALL DELAY37uS
WRINS_ONCE:
ANL A,#F0H
CLR RS
MOV A,#0FH
;DISPLAY ON
CLR RW
CALL WRINS_CHK
CALL DELAY37uS
SETB
MOV P1,A
CLR
E
E
MOV A,#01H
CALL WRINS_CHK
CALL DELAY1.52mS
;CLEAR DISPLAY
;ENTRY MODE SET
MOV P1,#FFH
RET
;-------------------------------------------------------------------
;For Check Bus Flag
CHK_BUSY:
PUSH
;Check Busy Flag
MOV A,#06H
A
CALL WRINS_CHK
CALL DELAY37uS
MOV P1,#FFH
$1
;-------------------------------------------------------------------
CLR RS
MAIN_START:
SETB RW
XXXX
XXXX
XXXX
SETB
MOV A,P1
CLR
E
E
XXXX
MOV P1,#FFH
CLR RS
SETB RW
.
.
.
.
.
.
.
.
.
.
SETB
NOP
CLR
JB
POP
RET
E
E
A.7,$1
A
.
.
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ST7066U
n Interfacing to the MPU
The ST7066U can send data in either two 4-bit operations or one 8-bit operation, thus allowing interfacing with 4-
or 8-bit MPU.
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For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3
are disabled. The data transfer between the ST7066U and the MPU is completed after the 4-bit data has
been transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB4 to
DB7) are transferred before the four low order bits (for 8-bit operation, DB0 to DB3). The busy flag must be
checked (one instruction) after the 4-bit data has been transferred twice. Two more 4-bit operations then
transfer the busy flag and address counter data.
Ø
Example of busy flag check timing sequence
R S
R /W
D e la y
E
(> 8 0 u s )
In te r n a l
o p e r a tio n
F u n c tio n in g
N o t
B u s y
D B 7
IR 7
IR 3
A C 3
A C 3
IR 7
IR 3
In s tr u c tio n w r ite
B u s y fla g c h e c k
B u s y fla g c h e c k
In s tr u c tio n w r ite
Ø
Intel 8051 interface
16
COM1 to COM16
4
P1.0 to P1.3
DB4 to DB7
P3.0
P3.1
P3.2
RS
R/W
E
40
SEG1 to SEG40
Intel 8051 Serial
ST7066U
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ST7066U
l
Ø
For 8-bit interface data, all eight bus lines (DB0 to DB7) are used.
Example of busy flag check timing sequence
R S
R /W
D e la y
E
( > 8 0 u s )
In te r n a l
o p e ra tio n
F u n c tio n in g
N o t
B u s y
D B 7
D a ta
B u s y
B u s y
D a ta
In s tr u c tio n w rite
B u s y fla g c h e c k
B u s y fla g c h e c k
B u s y fla g c h e c k
In s tr u c tio n w r ite
Ø
Intel 8051 interface
16
COM1 to COM16
DB0 to DB7
8
P1.0 to P1.7
P3.0
P3.1
P3.2
RS
R/W
E
40
SEG1 to SEG40
Intel 8051 Serial
ST7066U
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ST7066U
n Supply Voltage for LCD Drive
There are different voltages that supply to ST7066U’s pin (V1 - V5) to obtain LCD drive waveform. The relations
of the bias, duty factor and supply voltages are shown as below:
Duty Factor
1/8, 1/11
1/16
Bias
1/4
1/5
Supply Voltage
V1
V2
V3
V4
V5
Vcc - 1/4VLCD
Vcc - 1/2VLCD
Vcc - 1/2VLCD
Vcc - 3/4VLCD
Vcc - VLCD
Vcc - 1/5VLCD
Vcc - 2/5VLCD
Vcc - 3/5VLCD
Vcc - 4/5VLCD
Vcc- VLCD
VCC(+5V)
VCC(+5V)
VCC
VCC
R
R
R
V1
V1
R
V2
V2
V3
VLCD
VLCD
V3
V4
R
R
R
R
V4
V5
V5
VR
1/4 bias
(1/8, 1/11 duty cycle)
1/5 bias
(1/16 duty cycle)
VR
-5V
-5V
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ST7066U
n Timing Characteristics
l
Writing data from MPU to ST7066U
VIH1
RS
VIL1
tAS
tAH
RW
tPW
tAH
tf
E
tDSW
tH
tr
Valid data
tC
DB0-DB7
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Reading data from ST7066U to MPU
VIH1
RS
VIL1
tAS
tAH
RW
tPW
tAH
tf
E
tDDR
tH
tr
Valid data
tC
DB0-DB7
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ST7066U
l
Interface Timing with External Driver
tct
VOH2
CL1
CL2
D
VOL2
tCWH
tCWH
tCST
tCWL
tct
tDH
tSU
M
tDM
n Power Supply Conditions
Symbol Characteristics
Description
Min. Typ. Max. Unit
Power rise time that will trigger
internal power on reset circuit
The period that I/O is kept low.
tPOR
Power rise time
0.1
100
ms
ms
tIOL
tPW
I/O Low time
40
Enable pulse width
Please refer to the following tables.
1.
2.
During tPOR, VDD noise should be reduced (especially close to 2.0V). Otherwise the
Power-ON-Reset function might be triggered several times and maybe cause unexpected
result.
During tIOL, the I/O ports of the interface (control and data signals) should be kept at “Low”.
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ST7066U
n AC Characteristics
(TA = 25℃, VCC = 2.7V)
Symbol Characteristics
Test Condition
Min. Typ. Max. Unit
Internal Clock Operation
fOSC
OSC Frequency
R = 75KΩ
190
270
350
KHz
External Clock Operation
fEX
External Frequency
Duty Cycle
-
-
-
125
45
-
270
50
-
410
55
KHz
%
TR,TF
Rise/Fall Time
0.2
µs
Write Mode (Writing data from MPU to ST7066U)
TC
TPW
TR,TF
TAS
Enable Cycle Time Pin E
1200
460
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
Enable Pulse Width Pin E
Enable Rise/Fall Time Pin E
25
-
Address Setup Time Pins: RS,RW,E
Address Hold Time Pins: RS,RW,E
0
TAH
10
80
10
-
TDSW
TH
Data Setup Time
Data Hold Time
Pins: DB0 - DB7
Pins: DB0 - DB7
-
-
Read Mode (Reading Data from ST7066U to MPU)
TC
TPW
TR,TF
TAS
Enable Cycle Time Pin E
1200
480
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
Enable Pulse Width Pin E
-
25
-
Enable Rise/Fall Time Pin E
Address Setup Time Pins: RS,RW,E
Address Hold Time Pins: RS,RW,E
0
TAH
10
-
-
TDDR
TH
Data Setup Time
Data Hold Time
Pins: DB0 - DB7
Pins: DB0 - DB7
320
-
10
Interface Mode with LCD Driver(ST7065)
TCWH
TCWL
TCST
TSU
Clock Pulse with High Pins: CL1, CL2
800
800
500
300
300
0
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
Clock Pulse with Low Pins: CL1, CL2
Clock Setup Time Pins: CL1, CL2
-
-
Data Setup Time
Data Hold Time
M Delay Time
Pin: D
Pin: D
Pin: M
-
-
TDH
TDM
2000
V2.2
32/42
2006/05/11
ST7066U
n AC Characteristics
(TA = 25℃, VCC = 5V)
Symbol Characteristics
Test Condition
Min. Typ. Max. Unit
Internal Clock Operation
fOSC
OSC Frequency
R = 91KΩ
190
270
350
KHz
External Clock Operation
fEX
External Frequency
Duty Cycle
-
-
-
125
45
-
270
50
-
410
55
KHz
%
TR,TF
Rise/Fall Time
0.2
µs
Write Mode (Writing data from MPU to ST7066U)
TC
TPW
TR,TF
TAS
Enable Cycle Time Pin E
1200
140
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
Enable Pulse Width Pin E
Enable Rise/Fall Time Pin E
25
-
Address Setup Time Pins: RS,RW,E
Address Hold Time Pins: RS,RW,E
0
TAH
10
40
10
-
TDSW
TH
Data Setup Time
Data Hold Time
Pins: DB0 - DB7
Pins: DB0 - DB7
-
-
Read Mode (Reading Data from ST7066U to MPU)
TC
TPW
TR,TF
TAS
Enable Cycle Time Pin E
1200
140
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
Enable Pulse Width Pin E
-
25
-
Enable Rise/Fall Time Pin E
Address Setup Time Pins: RS,RW,E
Address Hold Time Pins: RS,RW,E
0
TAH
10
-
-
TDDR
TH
Data Setup Time
Data Hold Time
Pins: DB0 - DB7
Pins: DB0 - DB7
100
-
10
Interface Mode with LCD Driver(ST7065)
TCWH
TCWL
TCST
TSU
Clock Pulse with High Pins: CL1, CL2
800
800
500
300
300
0
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
Clock Pulse with Low Pins: CL1, CL2
Clock Setup Time Pins: CL1, CL2
-
-
Data Setup Time
Data Hold Time
M Delay Time
Pin: D
Pin: D
Pin: M
-
-
TDH
TDM
2000
V2.2
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2006/05/11
ST7066U
n Absolute Maximum Ratings
Characteristics
Power Supply Voltage
LCD Driver Voltage
Input Voltage
Symbol
Value
VCC
VLCD
VIN
-0.3 to +7.0
VCC-10.0 to VCC+0.3
-0.3 to VCC+0.3
-40oC to + 90oC
-55oC to + 125oC
Operating Temperature
Storage Temperature
TA
TSTO
n DC Characteristics
( TA = 25℃ , VCC = 2.7 V – 4.5 V )
Symbol Characteristics
Test Condition
Min. Typ. Max. Unit
VCC
Operating Voltage
LCD Voltage
-
2.7
3.0
-
-
4.5
V
V
VLCD
VCC-V5
10.0
fOSC = 270KHz
VCC=3.0V
ICC
VIH1
VIL1
Power Supply Current
-
0.1
0.25
VCC
mA
V
Input High Voltage
(Except OSC1)
-
0.7Vcc
- 0.3
0.7Vcc
-
-
-
-
-
-
-
-
-
Input Low Voltage
(Except OSC1)
-
0.6
V
Input High Voltage
(OSC1)
VIH2
-
VCC
V
Input Low Voltage
(OSC1)
VIL2
-
0.2Vcc
-
V
Output High Voltage
(DB0 - DB7)
0.75
Vcc
VOH1
VOL1
VOH2
VOL2
IOH = -0.1mA
IOL = 0.1mA
IOH = -0.04mA
IOL = 0.04mA
V
Output Low Voltage
(DB0 - DB7)
-
0.2Vcc
VCC
V
Output High Voltage
(Except DB0 - DB7)
0.8VCC
V
Output Low Voltage
(Except DB0 - DB7)
-
0.2VCC
V
RCOM
RSEG
Common Resistance VLCD = 4V, Id = 0.05mA
Segment Resistance VLCD = 4V, Id = 0.05mA
-
-
2
2
20
30
KΩ
KΩ
Input Leakage
VIN = 0V to VCC
Current
ILEAK
IPUP
-1
-
1
µA
µA
Pull Up MOS Current
VCC = 3V
-10
-50
-120
V2.2
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2006/05/11
ST7066U
n DC Characteristics
( TA = 25℃, VCC = 4.5 V - 5.5 V )
Symbol Characteristics
Test Condition
Min. Typ. Max. Unit
VCC
Operating Voltage
LCD Voltage
-
4.5
3.0
-
-
5.5
V
V
VLCD
VCC-V5
10.0
fOSC = 270KHz
VCC=5.0V
ICC
VIH1
VIL1
Power Supply Current
-
0.2
0.5
VCC
0.6
mA
V
Input High Voltage
(Except OSC1)
-
0.7Vcc
-
-
-
-
-
-
-
-
Input Low Voltage
(Except OSC1)
-
-0.3
V
Input High Voltage
(OSC1)
VIH2
-
VCC-1
VCC
1.0
V
Input Low Voltage
(OSC1)
VIL2
-
-
V
Output High Voltage
(DB0 - DB7)
VOH1
VOL1
VOH2
VOL2
IOH = -0.1mA
IOL = 0.1mA
IOH = -0.04mA
IOL = 0.04mA
3.9
VCC
0.4
V
Output Low Voltage
(DB0 - DB7)
-
V
Output High Voltage
(Except DB0 - DB7)
0.9VCC
VCC
0.1VCC
V
Output Low Voltage
(Except DB0 - DB7)
-
V
RCOM Common Resistance VLCD = 4V, Id = 0.05mA
-
-
2
2
20
30
KΩ
KΩ
RSEG
ILEAK
IPUP
Segment Resistance VLCD = 4V, Id = 0.05mA
Input Leakage
VIN = 0V to VCC
Current
-1
-
1
µA
µA
Pull Up MOS Current
VCC = 5V
-50
-110
-180
V2.2
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2006/05/11
ST7066U
n LCD Frame Frequency
l
Assume the oscillation frequency is 270KHZ, 1 clock cycle time = 3.7us, 1/16 duty; 1/5 bias,1 frame
= 3.7us x 200 x 16 = 11840us=11.8ms(84.7Hz)
200 clocks
1
2
3
4
16
1
2
3
4
16
1
2
3
4
16
Vcc
V1
V2
COM1
V3
V4
V5
Vcc
V1
V2
COM2
V3
V4
V5
Vcc
V1
V2
COM16
V3
V4
V5
Vcc
V1
V2
SEGx off
V3
V4
V5
Vcc
V1
V2
SEGx on
V3
V4
V5
1 frame
V2.2
36/42
2006/05/11
ST7066U
l
Assume the oscillation frequency is 270KHZ, 1 clock cycle time = 3.7us, 1/11 duty; 1/4 bias,1 frame
= 3.7us x 400 x 11 = 16280us=16.3ms (61.3Hz)
400 clocks
1
2
3
4
11
1
2
3
4
11
1
2
3
4
11
Vcc
V1
V2
V3
COM1
V4
V5
Vcc
V1
V2
V3
COM2
V4
V5
Vcc
V1
V2
V3
COM11
V4
V5
Vcc
V1
V2
V3
SEGx off
V4
V5
Vcc
V1
V2
V3
SEGx on
V4
V5
1 frame
V2.2
37/42
2006/05/11
ST7066U
l
Assume the oscillation frequency is 270KHZ, 1 clock cycle time = 3.7us, 1/8 duty; 1/4 bias,1 frame =
3.7us x 400 x 8 = 11840us=11.8ms (84.7Hz)
400 clocks
1
2
3
4
8
1
2
3
4
8
1
2
3
4
8
Vcc
V1
V2
V3
COM1
V4
V5
Vcc
V1
V2
V3
COM2
V4
V5
Vcc
V1
V2
V3
COM8
V4
V5
Vcc
V1
V2
V3
SEGx off
V4
V5
Vcc
V1
V2
V3
SEGx on
V4
V5
1 frame
V2.2
38/42
2006/05/11
ST7066U
n I/O Pad Configuration
V
CC
V
CC
V
CC
PMOS
PMOS
NMOS
PMOS
NMOS
Input PAD:E(No Pull up)
Input PAD:RS,R/W(With Pull up)
V
CC
V
CC
PMOS
NMOS
Output PAD:CL1,CL2,M,D
V
CC
V
CC
V
CC
Enable
PMOS
PMOS
PMOS
NMOS
Data
NMOS
I/O PAD:DB0-DB7
V2.2
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2006/05/11
ST7066U
n LCD and ST7066U Connection
1. 5x8 dots, 8 characters x 1 line (1/4 bias, 1/8 duty)
COM1
.
.
.
.
.
.
.
.
COM8
SEG1
LCD Panel: 8 Characters
x 1 line
.
.
.
.
.
SEG40
2. 5x11 dots, 8 characters x 1 line (1/4 bias, 1/11 duty)
COM1
.
.
.
.
.
.
.
.
.
.
.
COM11
LCD Panel: 8 Characters
x 1 line
SEG1
.
.
.
.
.
.
.
.
.
.
SEG40
V2.2
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2006/05/11
ST7066U
3. 5x8 dots, 8 characters x 2 line (1/5 bias, 1/16 duty)
COM1
.
.
.
.
.
.
.
.
COM8
COM9
.
.
.
.
.
.
.
.
COM16
SEG1
LCD Panel: 8 Characters
x 2 line
.
.
.
.
.
.
.
.
.
.
SEG40
4. 5x8 dots, 16 characters x 1 line (1/5 bias, 1/16 duty)
COM1
.
.
.
.
.
.
.
.
COM8
SEG1
.
.
.
.
.
.
LCD Panel: 16
Characters x 1 line
SEG40
COM9
.
.
.
.
.
.
.
.
COM16
V2.2
41/42
2006/05/11
ST7066U
n Application Circuit
V2.2
42/42
2006/05/11
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