ST7063C [SITRONIX]
80CH Segment Driver for Dot Matrix LCD; 80CH段驱动点矩阵LCD
| 型号： | ST7063C |
| 厂家： | 
SITRONIX TECHNOLOGY CO., LTD. |
| 描述： | 80CH Segment Driver for Dot Matrix LCD |
| 文件： | 总12页 (文件大小：304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST
Sitronix
ST7063C
80CH Segment Driver for Dot Matrix LCD
n Functions
n Features
l Dot matrix LCD driver with two 40 channel
outputs
l Display driving bias : static to 1/5
l Power supply for logic : 2.7V ~ 5.5V
l Power supply for LCD voltage (VDD~VEE) :
3V ~ 11V
l Bias voltage (V1 ~ V4)
l input/output signals
n
Input : Serial display data and control
100 Pin QFP package and bare chip available
pulse from controller IC
n
Output : 40 X 2 channels waveform for
LCD driving
n Description
ST7063C is a segment driver for dot matrix type
LCD display. It features 80 channels with 40 X 2
bits bi-directional shift registers, data latches,
LCD drivers and logic control circuits. It is
fabricated by high voltage CMOS process with
low current consumption.
waveforms to the LCD panel. The ST7063C is
designed for general purpose LCD drivers. It can
drive both static and dynamic drive LCD. The LSI
can be used as segment driver.
The ST7063C has pin function compatibility with
the KS0063(B) that allows the user to easily
replace it with an ST7063C.
The ST7063C can convert serial data received
from an LCD controller, such as ST7066U, into
parallel data and send out LCD driving
1/12
V1.3b
2005/11/08
ST7063C
ST7063C Specification Revision History
Date Description
2000/07/31 First Edition
Version
1.1
1.2
2000/11/14 Added QFP Pad Configuration(Page 6)
2001/02/26 Changed Application Circuit(Page 11)
1.2a
1. ST7063 Transition to ST7063C
2001/05/04
1.3
2. Moved QFP Package Dimensions Page 12 to Page 5
1.3a
1.3b
2001/08/29 Added “Substrate connect to VDD”(Page 4)
2005/11/08 Update temperature range
V1.3b
2/12
2005/11/08
ST7063C
n Functional Block Diagram
S1...............................S40
S41...............................S80
SEGMENT DRIVER
V1
V2
V3
SEGMENT DRIVER
V4
V
DD
V
V
SS
EE
DATA LATCH(40bits)
DATA LATCH(40bits)
BIDIRECTIONAL
SHIFTER(40bits)
BIDIRECTIONAL
SHIFTER(40bits)
M
CL1
CL2
CONTOL
DL1 SHL1 DR1
DL2 SHL2 DR2
V1.3b
3/12
2005/11/08
ST7063C
n Pad Arrangement
Substrate connect to VDD.
V1.3b
4/12
2005/11/08
ST7063C
n Package Dimensions
V1.3b
5/12
2005/11/08
ST7063C
n Pin Configuration(QFP 100)
S
3
1
S
3
2
S
3
3
S
3
4
S
3
5
S
3
6
S
3
7
S
3
8
S
3
9
S
4
0
S
8
0
S
7
9
S
7
8
S
7
7
S
7
6
S
7
5
S
7
4
S
7
3
S
7
2
S
7
1
1
0
0
9
9
9
8
9
7
9
6
9
5
9
4
9
3
9
2
9
1
9
0
8
9
8
8
8
7
8
6
8
5
8
4
8
3
8
2
8
1
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S09
S08
S07
S06
S05
S04
S03
S02
S01
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
V
E
E
V
1
V
2
V
3
V
4
V
S
S
C
L
1
S
H
L
1
S
H
L
2
N
C
N
C
V
D
D
C
L
2
D
L
1
D
R
1
D
L
2
D
R
2
N
C
N
C
M
V1.3b
6/12
2005/11/08
ST7063C
n Pad Name and Coordinates
Pad
Name
Pad
Name
Pad
Name
Pad No.
X
Y
Pad No.
X
Y
Pad No.
X
Y
1
S42 -1760 -1160
S43 -1630 -1160
S44 -1500 -1160
S45 -1380 -1160
S46 -1260 -1160
S47 -1140 -1160
S48 -1020 -1160
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
S74
S75
S76
S77
S78
S79
S80
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
1760 -780
1760 -660
1760 -540
1760 -420
1760 -300
1760 -180
1760 -60
1760 60
1760 180
1760 300
1760 420
1760 540
1760 660
1760 780
1760 900
1760 1030
1760 1160
1630 1160
1500 1160
1380 1160
1260 1160
1140 1160
1020 1160
900 1160
780 1160
660 1160
540 1160
420 1160
300 1160
180 1160
60 1160
-60 1160
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
S15
S14
S13
S12
S11
S10
S9
-180 1160
-300 1160
-420 1160
-540 1160
-660 1160
-780 1160
-900 1160
-1020 1160
-1140 1160
-1260 1160
-1380 1160
-1500 1160
-1630 1160
-1760 1160
-1760 1030
2
3
4
5
6
7
8
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
-900 -1160
-780 -1160
-660 -1160
-540 -1160
-420 -1160
-300 -1160
-180 -1160
-60 -1160
60 -1160
180 -1160
300 -1160
420 -1160
540 -1160
660 -1160
780 -1160
900 -1160
1020 -1160
1140 -1160
1260 -1160
1380 -1160
1500 -1160
1630 -1160
1760 -1160
1760 -1030
1760 -900
S8
9
S7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
S6
S5
S4
S3
S2
S1
VEE -1760 900
V1
V2
V3
V4
-1760 780
-1760 660
-1760 540
-1760 420
VSS -1760 300
CL1 -1760 180
SHL1 -1760 60
SHL2 -1760 -60
VDD -1760 -180
CL2 -1760 -300
DL1 -1760 -420
DR1 -1760 -540
DL2 -1760 -660
DR2 -1760 -780
M
-1760 -900
S41 -1760 -1030
V1.3b
7/12
2005/11/08
ST7063C
n Pin Description
Pin Name
VDD
Purpose
POWER
Description
for logic
I/O
N/A
N/A
N/A
I
VSS
GROUND
LCD GND
LCD output
LCD output
segment
for logic
VEE
for LCD driving voltage
used as select voltage level
used as non select voltage level
LCD driver output for part 1
direction control for part 1 segments
V1 V2
V3 V4
S1-S40
SHL1
I
O
direction
I
If SHL1 = 1 then DL1=out, DR1=in
If SHL1 = 0 then DL1=in, DR1=out
DL1, DR1
data in /out
I/O
S41-S80
SHL2
segment
direction
LCD driver output for part 2
O
I
direction control for part 2 segments
If SHL2 = 1 then DL2=out, DR2=in
If SHL2 = 0 then DL2=in, DR2=out
DL2, DR2
data in/out
I/O
M
alternation
latch clock
shift clock
Alternate the LCD driving waveform
latch the data after shift is completed
shift the data into the segments
I
I
I
CL1
CL2
V1.3b
8/12
2005/11/08
ST7063C
n Functional Description
Clock
The CL1 is the clock to latch data on the falling edge. It latches the data input from
the bi-directional shift register at the falling edge of CL1 and transfers its outputs to
the LCD driver circuit. The CL2 is the clock to shift data on the falling edge. It shifts
the serial data at the falling of CL2 and transfers the output of each bit of the register
to the latch circuit.
Shift Registers And Data I/O
The ST7063C supplies two sets of 40-bit shift register, which controls the shift
direction by SHL1 & SHL2. The SHL1 controls the 1st 40-bit shift register, and SHL2
controls the 2nd 40-bit shift register. When SHL1 is connected to VDD, the 1st shift
direction is from S40 to S1; when SHL1 is connected to VSS, the shift direction
changes from S1 to S40. When SHL2 is connected to VDD, the 2nd shift direction is
from S80 to S41; when SHL2 is connected to VSS, the shift direction changes from
S41 to S80.
The DL1, DR1, DL2, DR2 are data input or output option function.
Shift Direction of Channel 1
SHL1
Shift Direction
S1 à S40
DL1
IN
DR1
OUT
IN
0
1
S40 à S1
OUT
Shift Direction of Channel 2
Shift Direction
S41 à S80
SHL2
DL2
IN
DR2
OUT
IN
0
1
S80 à S41
OUT
V1.3b
9/12
2005/11/08
ST7063C
n LCD Output Waveforms
Output of LATCH
(DATA)
M
V2
V2
V4
V4
Output
(S1
~ S80)
V3
V3
V1
V1
n Timing Characteristics
TWCKL
VIH
CL2
VIL
TWCKH
TR
TF
TDH
TSU
Data in
(DL1, DL2)
(DR1, DR2)
TD
Data out
(DL1, DL2)
(DR1, DR2)
VOH
VOL
TSL
TLS
TLS
CL1
TWCKH
TR
TSU
M
V1.3b
10/12
2005/11/08
ST7063C
n D.C Characteristics
Symbol
Parameter
Test Condition Min. Typ. Max. Unit
Applicable pin
VDD
Operating Voltage
-
2.7
3
-
-
5.5
11
V
V
-
-
VLCD
Driver Supply Voltage
VDD-VEE
0.7
VDD
VIH
Input High Voltage
-
-
VDD
V
CL1,CL2,M,SHL1,SHL
0.3
VDD
2
VIL
ILKG
VOH
Input Low Voltage
Input Leakage Current
Output High Voltage
-
0
-
-
-
V
uA
V
DL1,DL2,DR1,DR2
VIN =0 ~ VDD
IOH = -0.4mA
-5
5
VDD
-0.4
-
DL1,DL2,DR1,DR2
V1~V4, S1~S80
VOL
IDD
IV
Output Low Voltage
Operating Current
Leakage Current
IOL = +0.4mA
-
-
-
100
-
0.4
300
10
V
FCL2 = 400KHZ
uA
uA
VDD,VEE
V1 ~ V4
VIN =VDD ~ VEE -10
n A.C Characteristics
Symbol
FCL
Parameter
Test Condition Min. Max. Unit
Applicable pin
CL2
Data Shift Frequency
Clock High Level Width
-
-
-
400
-
KHZ
ns
TWCKH
800
CL1,CL2
TWCKL
Clock Low Level Width
-
800
-
ns
CL2
TSL
TLS
TR/TF
Clock Set-up Time
Clock Set-up Time
Clock Rise/Fall Time
CL2 à CL1
CL1 à CL2
-
500
500
-
-
-
ns
ns
ns
CL1,CL2
CL1,CL2
CL1,CL2
200
TSU
TDH
TD
Data Set-up Time
Data Hold Time
Data Delay Time
-
300
300
-
-
-
ns
ns
ns
DL1,DL2,DR1,DR2
DL1,DL2,DR1,DR2
DL1,DL2,DR1,DR2
-
CL = 15 PF
500
n Maximum Absolute Ratings
Symbol
Parameters
Min.
Max. Unit
VDD
TOPR
TSTG
Supply Voltage
Operating Temperature
Storage Temperature
-0.3
-30
-65
7
V
85
℃
℃
150
V1.3b
11/12
2005/11/08
ST7063C
n Application Circuit : (2Line x 40Word)
V1.3b
12/12
2005/11/08
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