ST7036-0A [ETC]
Dot Matrix LCD Controller/Driver; 点阵LCD控制器/驱动器
| 型号： | ST7036-0A |
| 厂家： | 
ETC |
| 描述： | Dot Matrix LCD Controller/Driver |
| 文件： | 总72页 (文件大小：864K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST
Sitronix
ST7036
Preliminary
Dot Matrix LCD Controller/Driver
Features
z
z
5 x 8 dot matrix possible
z
z
Wide range of instruction functions:
Display clear, cursor home, display on/off,
cursor on/off, display character blink, cursor
shift, display shift, double height font
Automatic reset circuit that initializes the
controller/driver after power on and external
reset pin
Low power operation support:
-- 2.7 to 5.5V
z
z
Range of LCD driver power
-- 2.7 to 7.0V
4-bit, 8-bit, serial or 400kbits/s fast I2C-bus
MPU interface enabled
z
z
80 x 8-bit display RAM (80 characters max.)
10,240-bit character generator ROM for a
total of 256 character fonts(max)
64 x 8-bit character generator RAM(max)
Support two display mode:
16-com x 100-seg and 80 ICON
24-com x 80-seg and 80 ICON
16 x 5 –bit ICON RAM(max)
z
z
Internal oscillator(Frequency=540kHz) and
external clock
Built-in voltage booster and follower circuit
(low power consumption )
z
z
z
z
z
COM/SEG direction selectable
Multi-selectable for CGRAM/CGROM size
Instruction compatible to ST7066U and
KS0066U and HD44780
z
z
Available in COG type
Description
5.5V) of the ST7036 is suitable for any portable
The ST7036 dot-matrix liquid crystal display controller and
driver LSI displays alphanumeric, Japanese kana
characters, and symbols. It can be configured to drive a
dot-matrix liquid crystal display under the control of a 4-/
8-bit, serial or fast I2C interface microprocessor. Since all
the functions such as display RAM, character generator,
and liquid crystal driver, required for driving a dot-matrix
liquid crystal display are internally provided on one chip, a
minimal system can be interfaced with this
battery-driven product requiring low power dissipation.
The ST7036 LCD driver consists of 17 common signal
drivers and 100 segment signal drivers. And the second
mode is consists of 25 common signal and 80 segment
signal drivers. The maximum display RAM size can be
either 80 characters in 1-line display or 40 characters in
2-line display or 16 characters in 3-line. A single ST7036
can display up to one 20-character line or two 20-character
lines or three 16-character lines.
controller/driver.
No extra drivers can be cascaded.
The ST7036 character generator ROM is extended to
generate 256 5x8dot character fonts for a total of 256
different character fonts. The low power supply (2.7V to
product Name
OPR1 OPR2 Support Character
ROM Size
ST7036-0A
-
256
-
1
-
1
-
English / Japan/Europe
-
6800-4bit / 8bit interface
(without IIC interface)
ST7036
Note:
IIC interface
ST7036i
I²C option not available
for EA DOG series !
V1.1
2003/12/24
1/72
ST7036
ST7036 Serial Specification Revision History
Date Description
Version
0.1a
2003/04/28 1st Edition
PAD Dimension:
0.1b
2003/06/03 IC L mark location modified
Chip Size X/Y modified
0.2a
1.0
2003/09/01 1. Include ST7036i
1. Add application circuit for 3 line display.
2. 4 bit interface program example modified.
1. Remove the instruction of frequency adjust.
2. Add the detail of CGRAM/CGROM arrangement.
2003/10/24
2003/12/24
1.1
V1.1
2003/12/24
2/72
ST7036
Pad Dimensions
¾ Chip Size: 5190.0X910.0 µm
¾ Bump Pitch : 55 µm ( min )
¾ Bump Height : 17 µm ( typ. )
¾ Bump Size :
z
z
Pad No.1~52 : 56 x 72 µm
Pad No.53~170 : 35 x 101 µm
V1.1
2003/12/24
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ST7036
Pad Location Coordinates(N3=0 1 line/2 line)
Pad No. Function
X
Y
Pad No. Function
X
Y
1
2
3
4
5
6
7
8
XRESET
OSC
VDD
RS
CSB
RW
1859
1783
1707
1631
1555
1479
1403
1327
1251
1175
1099
1023
947
871
795
719
643
567
491
415
339
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
CLS
CAP1N
CAP1N
VOUT
VOUT
V0
V0
V1
V2
V3
V4
NC
COM[8]
COM[7]
COM[6]
COM[5]
COM[4]
COM[3]
COM[2]
COM[1]
COMI1
SEG[1]
SEG[2]
SEG[3]
SEG[4]
SEG[5]
SEG[6]
SEG[7]
SEG[8]
SEG[9]
SEG[10]
SEG[11]
SEG[12]
SEG[13]
SEG[14]
SEG[15]
SEG[16]
SEG[17]
SEG[18]
SEG[19]
-1181
-1257
-1333
-1409
-1485
-1561
-1637
-1713
-1789
-1865
-1941
-2017
-2125
-2180
-2235
-2290
-2518
-2518
-2518
-2518
-2518
-2518
-2518
-2518
-2518
-2518
-2518
-2518
-2518
-2518
-2253
-2198
-2143
-2088
-2033
-1978
-1923
-1868
-1813
-1758
393
393
393
393
393
393
393
393
393
393
393
393
378
378
378
378
365
310
255
200
145
90
E
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VSS
VSS
VSS
OPF1
OPF2
OPR1
OPR2
SHLC
SHLS
N3
TEST1
VDD
VDD
VDD
VIN
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
263
187
111
35
35
-20
-75
-41
-130
-185
-240
-295
-350
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-117
-193
-269
-345
-421
-497
-573
-649
-725
-801
-877
-953
-1029
-1105
VIN
VOUT
VOUT
PSB
VSS
PSI2B
CAP1P
CAP1P
EXT
VSS
V1.1
2003/12/24
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ST7036
Pad No. Function
X
Y
Pad No. Function
X
Y
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
SEG[20]
SEG[21]
SEG[22]
SEG[23]
SEG[24]
SEG[25]
SEG[26]
SEG[27]
SEG[28]
SEG[29]
SEG[30]
SEG[31]
SEG[32]
SEG[33]
SEG[34]
SEG[35]
SEG[36]
SEG[37]
SEG[38]
SEG[39]
SEG[40]
SEG[41]
SEG[42]
SEG[43]
SEG[44]
SEG[45]
SEG[46]
SEG[47]
SEG[48]
SEG[49]
SEG[50]
SEG[51]
SEG[52]
SEG[53]
SEG[54]
SEG[55]
SEG[56]
SEG[57]
SEG[58]
SEG[59]
-1703
-1648
-1593
-1538
-1483
-1428
-1373
-1318
-1263
-1208
-1153
-1098
-1043
-988
-933
-878
-823
-768
-713
-658
-603
-548
-493
-438
-383
-328
-273
-218
-163
-108
-53
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
SEG[60]
SEG[61]
SEG[62]
SEG[63]
SEG[64]
SEG[65]
SEG[66]
SEG[67]
SEG[68]
SEG[69]
SEG[70]
SEG[71]
SEG[72]
SEG[73]
SEG[74]
SEG[75]
SEG[76]
SEG[77]
SEG[78]
SEG[79]
SEG[80]
SEG[81]
SEG[82]
SEG[83]
SEG[84]
SEG[85]
SEG[86]
SEG[87]
SEG[88]
SEG[89]
SEG[90]
SEG[91]
SEG[92]
SEG[93]
SEG[94]
SEG[95]
SEG[96]
SEG[97]
SEG[98]
SEG[99]
497
552
607
662
717
772
827
882
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-350
-295
-240
-185
-130
-75
937
992
1047
1102
1157
1212
1267
1322
1377
1432
1487
1542
1597
1652
1707
1762
1817
1872
1927
1982
2037
2092
2147
2202
2518
2518
2518
2518
2518
2518
2518
2518
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
2
57
112
167
222
277
332
387
-20
35
442
V1.1
2003/12/24
5/72
ST7036
Pad No. Function
X
Y
Pad No. Function
X
Y
161
162
163
164
165
166
167
168
169
170
SEG[100]
COM[9]
2518
2518
2518
2518
2518
2518
2290
2235
2180
2125
90
145
200
255
310
365
378
378
378
378
COM[10]
COM[11]
COM[12]
COM[13]
COM[14]
COM[15]
COM[16]
COMI2
V1.1
2003/12/24
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ST7036
Pad Location Coordinates(N3=1 3 line)
Pad No. Function
X
Y
Pad No. Function
X
Y
1
2
3
4
5
6
7
8
XRESET
OSC
VDD
RS
CSB
RW
1859
1783
1707
1631
1555
1479
1403
1327
1251
1175
1099
1023
947
871
795
719
643
567
491
415
339
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
393
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
CLS
CAP1N
CAP1N
VOUT
VOUT
V0
V0
V1
V2
V3
V4
NC
COM[12]
COM[11]
COM[10]
COM[9]
COM[8]
COM[7]
COM[6]
COM[5]
NC
COM[4]
COM[3]
COM[2]
COM[1]
COMI1
NC
NC
NC
NC
NC
SEG[1]
SEG[2]
SEG[3]
SEG[4]
SEG[5]
SEG[6]
SEG[7]
SEG[8]
SEG[9]
-1181
-1257
-1333
-1409
-1485
-1561
-1637
-1713
-1789
-1865
-1941
-2017
-2125
-2180
-2235
-2290
-2518
-2518
-2518
-2518
-2518
-2518
-2518
-2518
-2518
-2518
-2518
-2518
-2518
-2518
-2253
-2198
-2143
-2088
-2033
-1978
-1923
-1868
-1813
-1758
393
393
393
393
393
393
393
393
393
393
393
393
378
378
378
378
365
310
255
200
145
90
E
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VSS
VSS
VSS
OPF1
OPF2
OPR1
OPR2
SHLC
SHLS
N3
TEST1
VDD
VDD
VDD
VIN
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
263
187
111
35
35
-20
-75
-41
-130
-185
-240
-295
-350
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-117
-193
-269
-345
-421
-497
-573
-649
-725
-801
-877
-953
-1029
-1105
VIN
VOUT
VOUT
PSB
VSS
PSI2B
CAP1P
CAP1P
EXT
VSS
V1.1
2003/12/24
7/72
ST7036
Pad No. Function
X
Y
Pad No. Function
X
Y
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
SEG[10]
SEG[11]
SEG[12]
SEG[13]
SEG[14]
SEG[15]
SEG[16]
SEG[17]
SEG[18]
SEG[19]
SEG[20]
SEG[21]
SEG[22]
SEG[23]
SEG[24]
SEG[25]
SEG[26]
SEG[27]
SEG[28]
SEG[29]
SEG[30]
SEG[31]
SEG[32]
SEG[33]
SEG[34]
SEG[35]
SEG[36]
SEG[37]
SEG[38]
SEG[39]
SEG[40]
SEG[41]
SEG[42]
SEG[43]
SEG[44]
SEG[45]
SEG[46]
SEG[47]
SEG[48]
SEG[49]
-1703
-1648
-1593
-1538
-1483
-1428
-1373
-1318
-1263
-1208
-1153
-1098
-1043
-988
-933
-878
-823
-768
-713
-658
-603
-548
-493
-438
-383
-328
-273
-218
-163
-108
-53
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
SEG[50]
SEG[51]
SEG[52]
SEG[53]
SEG[54]
SEG[55]
SEG[56]
SEG[57]
SEG[58]
SEG[59]
SEG[60]
SEG[61]
SEG[62]
SEG[63]
SEG[64]
SEG[65]
SEG[66]
SEG[67]
SEG[68]
SEG[69]
SEG[70]
SEG[71]
SEG[72]
SEG[73]
SEG[74]
SEG[75]
SEG[76]
SEG[77]
SEG[78]
SEG[79]
SEG[80]
NC
497
552
607
662
717
772
827
882
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-378
-350
-295
-240
-185
-130
-75
937
992
1047
1102
1157
1212
1267
1322
1377
1432
1487
1542
1597
1652
1707
1762
1817
1872
1927
1982
2037
2092
2147
2202
2518
2518
2518
2518
2518
2518
2518
2518
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
2
57
112
167
222
277
332
387
NC
NC
NC
NC
NC
COM[13]
COM[14]
COM[15]
-20
35
442
V1.1
2003/12/24
8/72
ST7036
Pad No. Function
X
Y
Pad No. Function
X
Y
161
162
163
164
165
166
167
168
169
170
COM[16]
COM[17]
COM[18]
COM[19]
COM[20]
COM[21]
COM[22]
COM[23]
COM[24]
COMI2
2518
2518
2518
2518
2518
2518
2290
2235
2180
2125
90
145
200
255
310
365
378
378
378
378
V1.1
2003/12/24
9/72
ST7036
Block Diagram
OSC
CPG
XRESET
CLS
Reset
circuit
Timing
generator
Instruction
register(IR)
Instruction
decoder
COM1 to
COM16
(OR 24)
Display data
RAM
(DDRAM)
80x8 bits
24-bit
shift
Common
signal
register
driver
RS
RW
E
MPU
COMI
interface
Address
counter
(AC)
CSB
PSB
SEG1 to
SEG100
100-bit
shift
100-bit
latch
Segment
signal
PSI2B
register
circuit
driver
Data
register
(DR)
DB4 to
DB7
V0~V4
VOUT
LCD drive
voltage
Input/
output
buffer
DB0 to
DB3
follower
Busy
flag
Character
generator RAM
(CGRAM)
VIN
Voltage
booster
circuit
Character
Cursor
generator ROM
(CGROM)
and
blink
SHLC
SHLS
CAP1P
CAP1N
64 bytes
controller
10.240 bits
EXT
N3
ICON RAM
80 bits
OPR1,2
OPF1,2
VSS
Parallel/serial converter
and
attribute circuit
VDD
V1.1
2003/12/24
10/72
ST7036
Pin Function
Name
Number I/O Interfaced with
Function
External reset pin. Only if the power on reset be used, the
XRESET pin could be fixed to VDD.
Low active.
XRESET
1
I
MPU
Select registers.
0: Instruction register (for write)
RS
1
I
MPU
Busy flag & address counter (for read)
1: Data register (for write and read)
Select read or write(In parallel mode).
0: Write
R/W
E
1
1
1
I
I
I
MPU
MPU
MPU
1: Read
Starts data read/write. (“E” must connect to “VDD” when
serial mode is selected.)
Chip select in parallel mode and serial interface(Low
active). When the CSB in falling edge state ( in serial
interface ), the shift register and the counter are reset.
DB0~DB3 are four low order bi-directional data bus pins.
DB0~DB3 are used for data transfer and receive between
the MPU and the ST7036.
CSB
These pins are not used during 4-bit operation and must
connect to VDD.
DB4~DB7 are four high order bi-directional data bus pins.
DB4~DB7 are used for data transfer and receive between
the MPU and the ST7036. DB7 can be used as a busy flag.
In serial interface mode DB7 is SI(input data),DB6 is
SCL(serial clock).
DB0 to DB7
8
I/O
MPU
In I2C interface DB7 is slave address A1, DB6 is slave
address A0, DB5 DB4 DB3 are SDA –out, DB2 DB1 are
SDA-in and D0 is SCL.
SDA and SCL must connect to I2C bus ( I2C bus means that
connecting a resister between SDA/SCL and the power of
I2C bus ).
Extension instruction select:
0:enable extension instruction(add contrast/ICON/double
height font/ extension instruction)
1:disable extension instruction(compatible to ST7066U, but
without 5x11dot font)
Interface selection
0:serial mode
Ext
1
1
I
I
ITO option
MPU
PSB
(“E” must connect to “VDD” when serial mode is selected.)
1:parallel mode(4/8 bit)
In I2C interface PSB must connect to VDD
PSB
PSI2B
Interface
No use
0
0
1
1
0
1
0
1
PSI2B
1
I
ITO option
SI4
SI2 ( I2C )
Parallel 68
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ST7036
Name
Number I/O Interfaced with
Function
Character generator select:
OPR1
OPR2
CGROM CGRAM
0
0
1
1
0
1
0
1
240
250
248
256
8
6
8
0
OPR1,OPR2
2
I
ITO option
Common signals direction select:
SHLC
SHLS
1
1
I
I
ITO option
ITO option
LCD
0:Com1~24←Row address 23~0(Invert)
1:Com1~24←Row address 0~23(Normal)
Segment signals direction select:
0:Seg1~100←Column address 99~0(Invert)
1:Seg1~100←Column address 0~99(Normal)
Common signals that are not used are changed
to non-selection waveform. COM9 to COM16
are non-selection waveforms at 1/8 or 1/9 duty factor
ICON common signals
COM1 to
COM16
16
O
COMI2
COMI1
Seg1~Seg10
Seg91~Seg100
1
O
O
LCD
LCD
Select “N3” pin for common or segment waveform output
(follow up table 2 defined)
21
1 line/2 line or 3 line select :
N3
1
I
ITO option
LCD
0:1 line/2 line SEG0~SEG100:normal
1:3 line COMI1,SEG1~SEG5,SEG97~SEG100 re-defined
SEG11 to
SEG90
80
O
Segment signals
The built-in voltage follower circuit selection
OPF1 OPF2
Bias select
0
0
1
1
0
1
0
1
Built-in voltage follower(only use at EXT=0)
Built-in bias resistor(3.3KΩ)
Built-in bias resistor(9.6KΩ)
External bias resistor select
OPF1,OPF2
2
I
ITO option
CAP1P
CAP1N
VIN
2
2
2
-
-
-
Power supply
Power supply
Power supply
For voltage booster circuit(VDD-VSS)
External capacitor about 0.1u~4.7uf
Input the voltage to booster
DC/DC voltage converter. Connect a capacitor between this
terminal and VIN when the built-in booster is used.
Power supply for LCD drive
VOUT
4
-
Power supply
V0 to V4
VDD,VSS
CLS
6
4,5
1
-
-
I
Power supply
Power supply
ITO option
V0-Vss = 7V (Max)
Built-in/external Voltage follower circuit
VDD: 2.7V to 5.5V, VSS: 0V
Internal/External oscillation select
0:external clock
1:internal oscillation
When the pin input is an external clock, it must be input to
OSC.
When the on-chip oscillator is used, it must be connected
to VDD.
OSC
1
1
I
Oscillation
Test pin
TEST1
I/O
TEST1 must connect to VDD.
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EXT option pin difference table
Mode
Normal mode (EXT=1)
Extension mode (EXT=0)
Difference
( Instruction compatible to ST7066U )
Booster
Always OFF
ON/OFF controlled by instruction
Can’t use the follower circuit
Bias (V0~V4)
Only use external resistor or internal resistor(1/5 Follower or internal/external resistor selectable
bias)
1. Controlled by instruction with follower
Contrast adjust
Control by external VR
2. Controlled by external VR with
internal/external resistor
ICON RAM
Can’t be use
RAM size has 80 bit width(S1~S80).
Control extension instruction for low power
consumption.
Instruction
Control normal instruction similar to ST7066U.
Only 5x8 font
Double height font
Can set 5x8 or 5x16 font
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ST7036
Function Description
z
System Interface
This chip has all four kinds of interface type with MPU: 4-bit bus, 8-bit bus, serial and fast I2C interface. 4-bit bus
or 8-bit bus is selected by DL bit in the instruction register.
During read or write operation, two 8-bit registers are used. One is data register (DR), the other is instruction
register(IR).
The data register(DR) is used as temporary data storage place for being written into or read from
DDRAM/CGRAM/ICON RAM, target RAM is selected by RAM address setting instruction. Each internal
operation, reading from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the
data in the next DDRAM/CGRAM/ICON RAM address is transferred into DR automatically. Also after MPU writes
data to DR, the data in DR is transferred into DDRAM/CGRAM/ICON RAM automatically.
The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to
read instruction data.
To select register, use RS input pin in 4-bit/8-bit bus mode.
RS R/W
Operation
L
L
L
H
L
Instruction Write operation (MPU writes Instruction code into IR)
Read Busy Flag(DB7) and address counter (DB0 ~ DB6)
Data Write operation (MPU writes data into DR)
Data Read operation (MPU reads data from DR)
H
H
H
Table 1. Various kinds of operations according to RS and R/W bits.
I2C interface
It just only could write Data or Instruction to ST7036 by the IIC Interface.
It could not read Data or Instruction from ST7036 (except Acknowledge signal).
SCL: serial clock input
SDA_IN: serial data input
SDA_OUT: acknowledge response output
Slaver address could set from “0111100” to “0111111”.
The I2C interface send RAM data and executes the commands sent via the I2C Interface. It could send data in to the RAM.
The I2C Interface is two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA)
and a Serial Clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be
initiated only when the bus is not busy.
BIT TRANSFER
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of
the clock pulse because changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated
in Fig.1.
START AND STOP CONDITIONS
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock
is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined
as the STOP condition (P). The START and STOP conditions are illustrated in Fig.2.
SYSTEM CONFIGURATION
The system configuration is illustrated in Fig.3.
· Transmitter: the device, which sends the data to the bus
· Master: the device, which initiates a transfer, generates clock signals and terminates a transfer
· Slave: the device addressed by a master
· Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message
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ST7036
· Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to
do so and the message is not corrupted
· Synchronization: procedure to synchronize the clock signals of two or more devices.
ACKNOWLEDGE
Acknowledge signal (ACK) is not BF signal in parallel interface.
Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the
transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is
addressed must generate an acknowledge after the reception of each byte. A master receiver must also generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that
acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master
receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been
clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP
condition. Acknowledgement on the I2C Interface is illustrated in Fig.4.
SDA
SCL
data line
stable;
change
of data
allowed
data valid
Fig .1 Bit transfer
SDA
SCL
S
P
START condition
STOP condition
Fig .2 Definition of START and STOP conditions
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER (1)
0111100
SLAVE
RECEIVER (2)
0111101
SLAVE
RECEIVER (3)
0111110
SLAVE
RECEIVER (4)
0111111
SDA
SCL
Fig .3 System configuration
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ST7036
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
8
SCL FROM
MASTER
2
1
9
S
clock pulse for
START
acknowledgement
condition
Fig .4 Acknowledgement on the IIC Interface
I2C Interface protocol
The ST7036 supports command, data write addressed slaves on the bus.
Before any data is transmitted on the I2C Interface, the device, which should respond, is addressed first. Four 7-bit slave
addresses (0111100 to 0111111) are reserved for the ST7036. The R/W is assigned to 0 for Write only.
The I2C Interface protocol is illustrated in Fig.5.
The sequence is initiated with a START condition (S) from the I2C Interface master, which is followed by the slave address.
All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I2C Interface transfer. After
acknowledgement, one or more command words follow which define the status of the addressed slaves.
A command word consists of a control byte, which defines Co and RS, plus a data byte.
The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a
cleared Co bit, only data bytes will follow. The state of the RS bit defines whether the data byte is interpreted as a command
or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte,
depending on the RS bit setting; either a series of display data bytes or command data bytes may follow. If the RS bit is set
to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is
automatically updated and the data is directed to the intended ST7036i device. If the RS bit of the last control byte is set to
logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received
commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the I2C
INTERFACE-bus master issues a STOP condition (P).
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ST7036
Write mode
acknowledgement
from ST7036i
acknowledgement
from ST7036i
acknowledgement
from ST7036i
acknowledgement
from ST7036i
acknowledgement
from ST7036i
R
R
control byte
data byte
control byte
data byte
S 0
1
1
1
1
0
A 1
A
A 0
A
A P
1
0
S
S
n>=0 bytes
MSB.......................LSB
R/W
slave address
1 byte
2n>=0 bytes
command word
Co
Co
R
/
W
C
o
R
S
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0
1
1
1
1
1 0
0 0 0 0 0 0
control byte
data byte
slave address
Fig .5 IIC Interface protocol
Last control byte to be sent. Only a stream of data bytes is allowed to follow.
This stream may only be terminated by a STOP condition.
0
1
Co
Another control byte will follow the data byte unless a STOP condition is received.
During write operation, two 8-bit registers are used. One is data register (DR), the other is instruction
register(IR).
The data register(DR) is used as temporary data storage place for being written into DDRAM/CGRAM/ICON
RAM, target RAM is selected by RAM address setting instruction. Each internal operation, writing into RAM, is
done automatically. So to speak, after MPU writes data to DR, the data in DR is transferred into
DDRAM/CGRAM/ICON RAM automatically.
The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to
read instruction data.
To select register, use RS bit input in IIC interface.
RS R/W
Operation
L
L
L
Instruction Write operation (MPU writes Instruction code into IR)
Data Write operation (MPU writes data into DR)
H
Table 2. Various kinds of operations according to RS and R/W bits.
z
Busy Flag (BF)
When BF = "High”, it indicates that the internal operation is being processed. So during this time the next
instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation),
through DB7 port. Before executing the next instruction, be sure that BF is not High.
z
Address Counter (AC)
Address Counter(AC) stores DDRAM/CGRAM/ICON RAM address, transferred from IR.
After writing into (reading from) DDRAM/CGRAM/ICON RAM, AC is automatically increased (decreased) by 1.
When RS = "Low" and R/W = "High", AC can be read through DB0 ~ DB6 ports.
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z
Display Data RAM (DDRAM)
Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended capacity is 80
x 8 bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used as
general data RAM. See Figure 6 for the relationships between DDRAM addresses and positions on the liquid
crystal display.
The DDRAM address (ADD ) is set in the address counter (AC) as hexadecimal.
¾
1-line display (N3=0,N = 0) (Figure 7)
When there are fewer than 80 display characters, the display begins at the head position. For
example, if using only the ST7036, 20 characters are displayed. See Figure 7.
When the display shift operation is performed, the DDRAM address shifts. See Figure 8.
High order bits
Low order bits
Example : DDRAM Address 4F
AC6 AC5 AC4 AC3 AC2 AC1 AC0
1
0
0
1
1
1
1
Fig. 6 DDRAM Address
Display Position (digit)
1
2
3
4
5
6
78 79 80
DDRAM Address 00 01 02 03 04 05 ........ 4D 4E 4F
Fig. 7 1-Line Display
Display Position
1
2
3
4
20
13
DDRAM Address
00 01 02 03
....
For Shift Left
01 02 03 04
4F 00 01 02
....
....
14
12
For Shift Right
Fig. 8 1-Line by 20-Character Display Example
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¾
2-line display (N3=0,N = 1) (Figure 9)
Case 1: When the number of display characters is less than 40 x 2 lines, the two lines are displayed from the
head. Note that the first line end address and the second line start address are not consecutive. For example,
when just the ST7036 is used, 20 characters x 2 lines are displayed. See Figure 9.
When display shift operation is performed, the DDRAM address shifts. See Figure 10.
Display Position
1
2
3
4
5
6
38 39 40
DDRAM
00 01 02 03 04 05 ........ 25 26 27
Address
(hexadecimal)
40 41 42 43 44 45 ........ 65 66 67
Fig. 9 2-Line Display
Display
Position
1
2
3
4
5
6
7
8
17 18 19 20
10 11 12 13
……………
……………
00 01 02 03 04 05 06 07
DDRAM
Address
40 41 42 43 44 45 46 47
50 51 52 53
……………
……………
01 02 03 04 05 06 07 08
41 42 43 44 45 46 47 48
11 12 13 14
51 52 53 54
For Shift
Left
……………
……………
27 00 01 02 03 04 05 06
67 40 41 42 43 44 45 46
0F 10 11 12
4F 50 51 52
For Shift
Right
Fig. 10 2-Line by 20-Character Display Example
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¾
3-line display (N3=1,N =1) (Figure 11)
Case 1: When the number of display characters is less than 16 x 3 lines, the tree lines are displayed from the
head. For example, when just the ST7036 is used, 16 characters x 3 lines are displayed. See Figure 11.
When display shift operation is performed, the DDRAM address shifts. See Figure 12.
Display Position
1
2
3
4
5
6
14 15 16
DDRAM
00 01 02 03 04 05 ........ 0D 0E 0F
Address
(hexadecimal)
10 11 12 13 14 15 ........ 1D 1E 1F
20 21 22 23 24 25 ........ 2D 2E 2F
Fig. 11 3-Line Display
Display Position
1
2
3
4
5
6
14 15 16
DDRAM
00 01 02 03 04 05 ........ 0D 0E 0F
10 11 12 13 14 15 ........ 1D 1E 1F
20 21 22 23 24 25 ........ 2D 2E 2F
Address
(hexadecimal)
1
2
3
4
5
6
14 15 16
01 02 03 04 05 06 ........ 0E 0F 00
11 12 13 14 15 16 ........ 1E 1F 10
21 22 23 24 25 26 ........ 2E 2F 20
For Shift Left
1
2
3
4
5
6
14 15 16
0F 00 01 02 03 04 ........ 0C 0D 0E
1F 10 11 12 13 14 ........ 1C 1D 1E
2F 20 21 22 23 24 ........ 2C 2D 2E
Fig. 12 3-Line Display
For Shift Right
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z
Character Generator ROM (CGROM)
The character generator ROM generates 5 x 8 dot character patterns from 8-bit character codes. It can generate
240/250/248/256 5 x 8 dot character patterns(select by OPR1/2 ITO pin). User-defined character patterns are
also available by mask-programmed ROM.
z
Character Generator RAM (CGRAM)
In the character generator RAM, the user can rewrite character patterns by program. For 5 x 8 dots, eight
character patterns can be written.
Write into DDRAM the character codes at the addresses shown as the left column of Table 5 to show the
character patterns stored in CGRAM.
See Table 5 for the relationship between CGRAM addresses and data and display patterns. Areas that are not
used for display can be used as general data RAM.
z
ICON RAM
In the ICON RAM, the user can rewrite icon pattern by program.
There are totally 80 dots for icon can be written.
See Table 6 for the relationship between ICON RAM address and data and the display patterns.
z
Timing Generation Circuit
The timing generation circuit generates timing signals for the operation of internal circuits such as
DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU
access are generated separately to avoid interfering with each other. Therefore, when writing data to
DDRAM, for example, there will be no undesirable interference, such as flickering, in areas other than
the display area.
z
LCD Driver Circuit(N3=0)
LCD Driver circuit has 17 common and 100 segment signals for LCD driving. Data from CGRAM/CGROM/ICON
is transferred to 100 bit segment latch serially, and then it is stored to 100 bit shift latch. When each common is
selected by 17 bit common register, segment data also output through segment driver from 100 bit segment
latch. In case of 1-line display mode, COM1 ~ COM8(with COMI) have 1/9 duty, and in 2-line mode, COM1 ~
COM16(with COMI) have 1/17 duty ratio.
z
LCD Driver Circuit(N3=1)
LCD Driver circuit has 25 common and 80 segment signals for LCD driving. Data from CGRAM/CGROM/ICON
is transferred to 80 bit segment latch serially, and then it is stored to 80 bit shift latch. When each common is
selected by 25 bit common register, segment data also output through segment driver from 80 bit segment latch.
In case of 3-line display mode, COM1 ~ COM24(with COMI) have 1/25 duty.
COM/SEG Output pins
COM
[1:8]
SEG
[1:5]
SEG
[6:10]
SEG
SEG
[11:90]
SEG
SEG
[91:96]
SEG
SEG
[97:100]
SEG
COM
[9:16]
COM
N3
COMI1
COMI1
NC
COMI2
COMI2
COMI2
COM
[1:8]
SEG
VSS
VDD
[1:5]
[6:10]
[11:90]
SEG
[91:96]
[97:100]
COM
[9:16]
COM
COM
[5:12]
COM[4:1]
NC
NC
+ COMI1
[1:80]
[13:16]
[17:24]
Table 3. COM/SEG output define
z
Cursor/Blink Control Circuit
It can generate the cursor or blink in the cursor/blink control circuit. The cursor or the blink appears in the digit at
the display data RAM address set in the address counter.
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Table 4 Correspondence between Character Codes and Character Patterns
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CGRAM/CGROM arrangement with (OPR1, OPR2)=
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Character Code
(DDRAM Data)
CGRAM
Address
Character Patterns
(CGRAM Data)
b7 b6 b5 b4 b3 b2 b1 b0 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
1
1
1
1
1
1
0
1
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
-
-
0
0
0
1
-
-
-
-
-
0
0
-
Table 5 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character
patterns (CGRAM Data)
Notes:
1.
2.
Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types).
CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position
and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding to the
cursor display position, at 0 as the cursor display. If the 8th line data is 1, 1 bits will light up the 8th line
regardless of the cursor presence.
3.
4.
Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left).
As shown Table 5, CGRAM character patterns are selected when character code bits 4 to 7 are all 0.
However, since character code bit 3 has no effect, the R display example above can be selected by either
character code 00H or 08H.
5.
6.
“1” for CGRAM data corresponds to display selection and “0” to non-selection,“-“ Indicates no effect.
Different OPR1/2 ITO option can select different CGRAM size.
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When SHLS=1, ICON RAM map refer below table
ICON RAM bits
ICON address
D7
-
D6
-
D5
-
D4
D3
D2
D1
D0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
S1
S2
S3
S4
S5
-
-
-
S6
S7
S8
S9
S10
S15
S20
S25
S30
S35
S40
S45
S50
S55
S60
S65
S70
S75
S80
-
-
-
S11
S16
S21
S26
S31
S36
S41
S46
S51
S56
S61
S66
S71
S76
S12
S17
S22
S27
S32
S37
S42
S47
S52
S57
S62
S67
S72
S77
S13
S18
S23
S28
S33
S38
S43
S48
S53
S58
S63
S68
S73
S78
S14
S19
S24
S29
S34
S39
S44
S49
S54
S59
S64
S69
S74
S79
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
When SHLS=0, ICON RAM map refer below table
ICON address
ICON RAM bits
D7
-
D6
-
D5
-
D4
D3
D2
D1
D0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
S80
S75
S70
S65
S60
S55
S50
S45
S40
S35
S30
S25
S20
S15
S10
S5
S79
S74
S69
S64
S59
S54
S49
S44
S39
S34
S29
S24
S19
S14
S9
S78
S73
S68
S63
S58
S53
S48
S43
S38
S33
S28
S23
S18
S13
S8
S77
S72
S67
S62
S57
S52
S47
S42
S37
S32
S27
S22
S17
S12
S7
S76
S71
S66
S61
S56
S51
S46
S41
S36
S31
S26
S21
S16
S11
S6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
S4
S3
S2
S1
Table 6 ICON RAM map
When ICON RAM data is filled the corresponding position displayed is described as the following table.
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ST7036
Instructions
There are four categories of instructions that:
z
z
z
z
Designate ST7036 functions, such as display format, data length, etc.
Set internal RAM addresses
Perform data transfer with internal RAM
Others
¾
instruction table at “Normal mode”
(when “EXT” option pin connect to VDD, the instruction set follow below table)
Instruction
Instruction Code
Execution Time
Instruction
Description
OSC= OSC= OSC=
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
380kHz 540kHz 700kHz
Clear
Write "20H" to DDRAM. and set
DDRAM address to "00H" from AC
1.08
ms
0.76
ms
0.59
ms
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Display
Set DDRAM address to "00H" from
AC and return cursor to its original
position if shifted. The contents of
DDRAM are not changed.
Return
Home
1.08
ms
0.76
ms
0.59
ms
X
Sets cursor move direction and
specifies display shift. These
operations are performed during
data write and read.
Entry Mode
Set
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
I/D
C
S
B
D=1:entire display on
C=1:cursor on
B=1:cursor position on
Display
D
ON/OFF
S/C and R/L:
Cursor or
Set cursor moving and display shift
control bit, and the direction, without
changing DDRAM data.
0
1
1
S/C R/L
X
X
X
X
Display Shift
DL: interface data is 8/4 bits
N: number of line is 2/1
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
Function Set
Set CGRAM
0
0
0
0
0
0
0
0
1
0
1
DL
N
X
Set CGRAM address in address
counter
AC5 AC4 AC3 AC2 AC1 AC0
Set DDRAM
Address
Set DDRAM address in address
counter
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Whether during internal operation or
not can be known by reading BF.
The contents of address counter
can also be read.
Read Busy
Flag and
Address
0
0
0
0
1
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
Write Data
Write data into internal RAM
(DDRAM/CGRAM)
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
1
1
0
1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
to RAM
Read Data
from RAM
Read data from internal RAM
(DDRAM/CGRAM)
Note:
Be sure the ST7036 is not in the busy state (BF = 0) before sending an instruction from the MPU to the ST7036.
If an instruction is sent without checking the busy flag, the time between the first instruction and next instruction
will take much longer than the instruction time itself. Refer to Instruction Table for the list of each instruction
execution time.
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ST7036
¾
instruction table at “Extension mode”
(when “EXT” option pin connect to VSS, the instruction set follow below table)
Instruction
Instruction Code
Execution Time
Instruction
Description
OSC= OSC= OSC=
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
380kHz 540kHz 700kHz
Clear
Write "20H" to DDRAM. and set
DDRAM address to "00H" from AC
1.08
ms
0.76
ms
0.59
ms
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
x
Display
Set DDRAM address to "00H" from
AC and return cursor to its original
position if shifted. The contents of
DDRAM are not changed.
Return
Home
1.08
ms
0.76
ms
0.59
ms
Sets cursor move direction and
specifies display shift. These
operations are performed during
data write and read.
Entry Mode
Set
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
I/D
C
S
B
D=1:entire display on
C=1:cursor on
B=1:cursor position on
Display
D
ON/OFF
DL: interface data is 8/4 bits
N: number of line is 2/1
DH: double height font
IS[2:1]: instruction table select
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
Function Set
0
0
0
0
0
1
0
1
DL
N
DH IS2 IS1
Set DDRAM
Address
Set DDRAM address in address
counter
AC6 AC5 AC4 AC3 AC2 AC1 AC0
Whether during internal operation or
not can be known by reading BF.
The contents of address counter
can also be read.
Read Busy
Flag and
Address
0
0
0
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
Write Data
Write data into internal RAM
(DDRAM/CGRAM/ICONRAM)
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
1
1
0
1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
to RAM
Read Data
from RAM
Read data from internal RAM
(DDRAM/CGRAM/ICONRAM)
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ST7036
Instruction table 0(IS[2:1]=[0,0])
S/C and R/L:
Cursor or
Set cursor moving and display shift
control bit, and the direction, without
changing DDRAM data.
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
0
0
0
0
0
0
0
1
0
1
S/C R/L
X
X
Display Shift
Set CGRAM address in address
counter
Set CGRAM
AC5 AC4 AC3 AC2 AC1 AC0
Instruction table 1(IS[2:1]=[0,1])
BS=1:1/4 bias
BS=0:1/5 bias
FX FX: fixed on high in 3-line
application and fixed on low in other
applications.
0
0
26.3 µs 18.5 µs 14.3 µs
Bias Set
0
0
0
1
BS
1
0
Set ICON
Address
Set ICON address in address
0
0
0
0
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
0
0
1
1
0
0
0
1
AC3 AC2 AC1 AC0
counter.
Ion: ICON display on/off
Bon: set booster circuit on/off
C5,C4: Contrast set for internal
follower mode.
Power/ICON
Control/
Ion Bon C5 C4
Contrast Set
Fon: set follower circuit on/off
Rab2~0:
Follower
Control
Rab Rab Rab
Fon
0
0
0
0
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
0
0
1
1
1
1
0
1
2
1
0
select follower amplified ratio.
Contrast set for internal follower
mode.
Contrast Set
C3 C2 C1 C0
Instruction table 2(IS[2:1]=[1,0])
Double
Height
Position
Select
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
0
0
0
0
0
0
0
1
0
1
UD
X
x
x
UD: Double height position select
Do not use (reserved for test)
Reserved
X
X
X
X
X
X
Instruction table 3(IS[2:1]=[1,1]):Do not use (reserved for test)
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ST7036
Instruction Description
z
Clear Display
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
1
Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to
"00H" into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge
on first line of the display. Make entry mode increment (I/D = "1").
z
Return Home
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
1
X
Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter.
Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does
not change.
z
Entry Mode Set
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
I/D
0
0
0
0
0
0
0
1
S
Set the moving direction of cursor and display.
¾
¾
I/D : Increment / decrement of DDRAM address (cursor or blink)
When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1.
When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1.
* CGRAM operates the same as DDRAM, when read from or write to CGRAM.
S: Shift of entire display
When DDRAM read (CGRAM read/write) operation or S = "Low", shift of entire display is not performed. If
S = "High" and DDRAM write operation, shift of entire display is performed according to I/D value (I/D =
"1" : shift left, I/D = "0" : shift right).
S
H
H
I/D
H
Description
Shift the display to the left
Shift the display to the right
L
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ST7036
z
Display ON/OFF
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
1
D
C
B
Control display/cursor/blink ON/OFF 1 bit register.
¾
¾
¾
D : Display ON/OFF control bit
When D = "High", entire display is turned on.
When D = "Low", display is turned off, but display data is remained in DDRAM.
C : Cursor ON/OFF control bit
When C = "High", cursor is turned on.
When C = "Low", cursor is disappeared in current display, but I/D register remains its data.
B : Cursor Blink ON/OFF control bit
When B = "High", cursor blink is on, that performs alternate between all the high data and display
character at the cursor position.
When B = "Low", blink is off.
Alternating
display
Every
64 frames
Cursor
z
Cursor or Display Shift
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
S/C R/L
0
0
0
0
0
1
X
X
¾
¾
S/C: Screen/Cursor select bit
When S/C=”High”, Screen is controlled by R/L bit.
When S/C=”Low”, Cursor is controlled by R/L bit.
R/L: Right/Left
When R/L=”High”, set direction to right.
When R/L=”Low”, set direction to left.
Without writing or reading of display data, shift right/left cursor position or display. This instruction is used to
correct or search display data. During 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st
line. Note that display shift is performed simultaneously in all the line. When displayed data is shifted
repeatedly, each line shifted individually. When display shift is performed, the contents of address counter are
not changed.
S/C
L
L
R/L
L
H
Description
AC Value
AC=AC-1
AC=AC+1
AC=AC
Shift cursor to the left
Shift cursor to the right
Shift display to the left. Cursor follows the display shift
H
L
H
H
Shift display to the right. Cursor follows the display shift AC=AC
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ST7036
z
Function Set
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DL DH IS2 IS1
0
0
0
0
1
N
¾
DL : Interface data length control bit
When DL = "High", it means 8-bit bus mode with MPU.
When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select
8-bit or 4-bit bus mode.
When 4-bit bus mode, it needs to transfer 4-bit data by two times.
¾
¾
N : Display line number control bit
When N = "High", 2-line display mode is set.
When N = "Low", it means 1-line display mode.
When “N3” option pin connect to VDD, N must set “N=1”.
DH : Double height font type control bit
When DH = " High " and N= “Low”, display font is selected to double height mode(5x16 dot),RAM address
can only use 00H~27H.
When DH= “High” and N= “High”, it is forbidden.
When DH = " Low ", display font is normal (5x8 dot).
EXT option pin connect to
high
EXT option pin connect to
low
N
DH
Character
Display Lines
Font
Character
Display Lines
Font
L
L
H
H
L
H
L
1
1
2
2
5x8
5x8
5x8
5x8
1
1
2
5x8
5x16
5x8
H
Forbidden
2 line mode normal display (DH=0/N=1)
1 line mode with double height font (DH=1/N=0)
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ST7036
¾
z
¾
IS[2:1]: instruction table select
When IS[2:1]=(0,0): normal instruction be selected(refer instruction table 0)
When IS[2:1]=(0,1):extension instruction be selected(refer instruction table 1 )
When IS[2:1]=(1,0):extension instruction be selected(refer instruction table 2 )
When IS[2:1]=(1,1):Do not use (reserved for test)
Double height position set: IS[2:1]=(1,0)
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
UD
0
0
0
0
0
1
X
X
X
UD: Select double height font display position of screen.(N3=VDD)
When UD = "High", double height font is show on Com1~Com16.
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
AC3 AC2 AC1 AC0
0
0
0
1
0
0
When UD = "Low", double height font is show on Com9~Com24.
DH
H
UD
H
2 LINES(N3=VSS)
Com1~Com16 Double Height
Com1~Com16 Double Height
Normal Display
3 LINES(N3=VDD)
Com1~Com16 Double Height
Com17~Com24 Normal Display
Com1~Com8 Normal Display
Com9~Com24 Double Height
H
L
L
X
Normal Display
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ST7036
3 Line mode normal display (DH = 0 / N = 1 / UD = don`t care )
COM1 ..8 is normal , COM9 .. 24 is a double height font (DH = 1 / N = 1 / UD = 0 )
COM17 ..24 is normal , COM1 .. 16 is a double height font (DH = 1 / N = 1 / UD = 1 )
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ST7036
z
Set CGRAM Address
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
AC5 AC4 AC3 AC2 AC1 AC0
0
0
0
1
Set CGRAM address to AC.
This instruction makes CGRAM data available from MPU.
z
Set DDRAM Address
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 AC6 AC5 AC4 AC3 AC2 AC1 AC0
0
0
Set DDRAM address to AC.
This instruction makes DDRAM data available from MPU.
When 1-line display mode (N = 0), DDRAM address is from "00H" to "4FH".
In 2-line display mode (N = 1), DDRAM address in the 1st line is from "00H" to "27H", and
DDRAM address in the 2nd line is from "40H" to "67H".
In 3-line display mode (N3=1, N=1), DDRAM address in the 1st line is from “00H” to “OFH”, DDRAM in the
2nd line is from “10H” to “1FH”, and DDRAM in the 3rd line is from “20H” to “2FH”.
z
Read Busy Flag and Address
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
0
1
When BF = “High”, indicates that the internal operation is being processed. So during this time the next
instruction cannot be accepted.
The address Counter (AC) stores DDRAM/CGRAM addresses, transferred from IR.
After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1.
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ST7036
z
Write Data to CGRAM,DDRAM or ICON RAM
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
Write binary 8-bit data to CGRAM,DDRAM or ICON RAM
The selection of RAM from DDRAM, CGRAM or ICON RAM, is set by the previous address set instruction
: DDRAM address set, CGRAM address set, ICON RAM address set. RAM set instruction can also determine
the AC
direction to RAM.
After write operation, the address is automatically increased/decreased by 1, according to
the entry mode.
z
Read Data from CGRAM,DDRAM or ICON RAM
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D7 D6 D5 D4 D3 D2 D1 D0
1
1
Read binary 8-bit data from DDRAM/CGRAM./ICON RAM
The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not
performed before this instruction, the data that read first is invalid, because the direction of AC is not
determined. If you read RAM data several times without RAM address set instruction before read operation,
you can get correct RAM data from the second, but the first data would be incorrect, because there is no time
margin to transfer RAM data.
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ST7036
z
Bias Set
¾
BS: bias selection
When BS=”High”, the bias will be 1/4
When BS=”Low”, the bias will be 1/5
BS will be invalid when external bias resistors are used(OPF1=1,OPF2=1)
FX: must be fixed on high in 3-line application and fixed on low in other applications.
¾
z
Set ICON RAM address
Set ICON RAM address to AC.
This instruction makes ICON data available from MPU.
When IS=1 at Extension mode,
The ICON RAM address is from "00H" to "0FH".
z
Power/ICON control/Contrast set(high byte)
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
0
1
I
ON
BON C5 C4
¾
¾
Ion: set ICON display on/off
When Ion = "High", ICON display on.
When Ion = "Low", ICON display off.
Bon: switch booster circuit
Bon can only be set when internal follower is used (OPF1=0,OPF2=0).
When Bon = "High", booster circuit is turn on.
When Bon = "Low", booster circuit is turn off.
¾
C5,C4 : Contrast set(high byte)
C5,C4,C3,C2,C1,C0 can only be set when internal follower is used (OPF1=0,OPF2=0).They can more
precisely adjust the input reference voltage of V0 generator. The details please refer to the supply voltage
for LCD driver.
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ST7036
z
Follower control
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Rab Rab Rab
0
0
0
1
1
0
F
ON
2
1
0
¾
Fon: switch follower circuit
Fon can only be set when internal follower is used (OPF1=0,OPF2=0).
When Fon = "High", internal follower circuit is turn on.
When Fon = "Low", internal follower circuit is turn off.
Note that Fon must be set to “Low” if (OPF1, OPF2) is not (0,0).
¾
z
Rab2,Rab1,Rab0 : V0 generator amplified ratio
Rab2,Rab1,Rab0 can only be set when internal follower is used (OPF1=0,OPF2=0).They can adjust the
amplified ratio of V0 generator. The details please refer to the supply voltage for LCD driver.
Contrast set(low byte)
RS R/W
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C3 C2 C1 C0
0
0
0
1
1
1
¾
C3,C2,C1,C0:Contrast set(low byte)
C5,C4,C3,C2,C1,C0 can only be set when internal follower is used (OPF1=0,OPF2=0).They can more
precisely adjust the input reference voltage of V0 generator. The details please refer to the supply voltage
for LCD driver.
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ST7036
Reset Function
Initializing by Internal Reset Circuit
An internal reset circuit automatically initializes the ST7036 when the power is turned on. The
following instructions are executed during the initialization. The busy flag (BF) is kept in the busy state (BF = 1)
until the initialization ends. The busy state lasts for 40 ms after VDD rises to stable.
1.
2.
Display clear
Function set:
DL = 1; 8-bit interface data
N = 0; 1-line display
DH=0; normal 5x8 font
IS[2:1]=(0,0); use instruction table 0
Display on/off control:
D = 0; Display off
3.
4.
C = 0; Cursor off
B = 0; Blinking off
Entry mode set:
I/D = 1; Increment by 1
S = 0; No shift
5.
6.
7.
3 line: FX=1
1/2 line: FX=0
ICON control
Ion=0; ICON off
Power control
BS=0; 1/5bias
Bon=0; booster off
Fon=0; follower off
(C5,C4,C3,C2,C1,C0)=(1,0,0,0,0,0)
(Rab2,Rab1,Rab0)=(0,1,0)
Double Height Position Select
UD=0, double height font is show on Com9~Com24.
8.
Note:
If the electrical characteristics conditions listed under the table Power Supply Conditions Using
Internal Reset Circuit are not met, the internal reset circuit will not operate normally and will fail
to initialize the ST7036.
When internal Reset Circuit not operate,ST7036 can be reset by XRESET pin from MPU control signal.
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ST7036
Initializing by Instruction
z
z
8-bit Interface (fosc=380kHz)
P O W E R O N o r external reset
W ait tim e > 40m S
A fter V D D stab le
F u n ctio n set
B F can n ot b e
R S
0
R /W D B 7 D B 6 D B 5 D B 4 D B 3 D B 2 D B 1 D B 0
ch ecked b efo re
this in stru ctio n .
0
0
0
1
1
N
D H
IS 2
IS 1
W ait tim e > 26.3 μ S
F u n ctio n set
B F can n ot b e
R S
0
R /W D B 7 D B 6 D B 5 D B 4 D B 3 D B 2 D B 1 D B 0
ch ecked b efo re
this in stru ctio n .
0
0
0
1
1
N
D H
IS 2
IS 1
W ait tim e > 26.3 μ S
In tern al O S C freq u en cy
R S
0
R /W D B 7 D B 6 D B 5 D B 4 D B 3 D B 2 D B 1 D B 0
B S F2 F 1 F 0
0
0
0
0
1
W ait tim e > 26.3 μ S
C o n trast set
R S
0
R /W D B 7 D B 6 D B 5 D B 4 D B 3 D B 2 D B 1 D B 0
C 2
C 1
C 0
0
0
1
1
1
C 3
W ait tim e > 26.3 μ S
P o w er/IC O N /C o n trast co n tro l
R S
0
R /W D B 7 D B 6 D B 5 D B 4 D B 3 D B 2 D B 1 D B 0
0
B on
C 5
C 4
0
1
0
1
Ion
W ait tim e > 26.3 μ S
F o llo w er co n tro l
R S
0
R /W D B 7 D B 6 D B 5 D B 4 D B 3 D B 2 D B 1 D B 0
R a b2
R ab 1
R a b0
0
0
1
1
0
F on
W ait tim e > 26.3 μ S
D isp lay O N /O F F co n tro l
R S
0
R /W D B 7 D B 6 D B 5 D B 4 D B 3 D B 2 D B 1 D B 0
0
0
0
0
0
1
D
C
B
W ait tim e > 26.3 μ S
Initialization end
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ST7036
¾
Initial Program Code Example For 8051 MPU(8 Bit Interface):
;---------------------------------------------------------------------------------
INITIAL_START:
CALL DELAY40mS
MOV A,#38H
;FUNCTION SET
CALL WRINS_NOCHK ;8 bit, N=1,5*7dot
CALL DELAY30uS
MOV A,#38H
;FUNCTION SET
CALL WRINS_NOCHK ;8 bit, N=1,5*7dot
CALL DELAY30uS
MOV A,#14H
;set bias
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#78H
;Contrast set adjustment
;Power/ICON/Contrast control
;Follower control
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#5EH
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#6AH
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#0CH
;DISPLAY ON
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#01H
;CLEAR DISPLAY
CALL WRINS_CHK
CALL DELAY2mS
MOV A,#06H
;ENTRY MODE SET
CALL WRINS_CHK
CALL DELAY30uS
;CURSOR MOVES TO RIGHT
;---------------------------------------------------------------------------------
MAIN_START:
XXXX
XXXX
XXXX
XXXX
;---------------------------------------------------------------------------------
WRINS_CHK:
CALL CHK_BUSY
WRINS_NOCHK:
CLR
RS
RW
E
;EX: Port 3.0
CLR
;EX: Port 3.1
SETB
;EX:Port 3.2
MOV P1,A
;EX:Port 1=Data Bus
CLR
E
MOV P1,#FFH
RET
;For Check Busy Flag
;---------------------------------------------------------------------------------
CHK_BUSY:
CLR
;Check Busy Flag
RS
SETB RW
SETB
JB
E
P1.7,$
E
CLR
RET
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z
4-bit Interface (fosc=380kHz)
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¾
Initial Program Code Example For 8051 MPU(4 Bit Interface):
;-------------------------------------------------------------------
INITIAL_START:
XXXX
;-------------------------------------------------------------------
WRINS_CHK:
CALL DELAY40mS
MOV
CALL
CALL
A,#30H
; FUNCTION SET
CALL CHK_BUSY
WRINS_ONCE ; 8 bit, DL = 1
DELAY2mS
WRINS_NOCHK:
PUSH
A
ANL A,#F0H
CLR RS
MOV
CALL
CALL
A,#30H
; FUNCTION SET
;EX: Port 3.0
WRINS_ONCE ; 8 bit, DL = 1
DELAY30uS
CLR RW
;EX: Port 3.1
SETB
E
;EX: Port 3.2
MOV P1,A
;EX:Port1=Data Bus
MOV
CALL
CALL
A,#30H
; FUNCTION SET
CLR
E
A
WRINS_ONCE ; 8 bit, DL = 1
DELAY30uS
POP
SWAP
A
WRINS_ONCE:
CALL
MOV
CALL
CALL
CHK_BUSY
ANL A,#F0H
CLR RS
A,#20H
; FUNCTION SET
WRINS_ONCE ; 4 bit, DL = 0
DELAY30uS
CLR RW
SETB
E
MOV P1,A
MOV
CALL
A,#29H
; FUNCTION SET
CLR
E
WRINS_CHK ; 4 bit, DL = 0, N = 1,
MOV P1,#FFH
RET
;For Check Bus Flag
CALL DELAY30uS
; IS2 = 0, IS1 = 1
;bias
;-------------------------------------------------------------------
MOV A,#14H
CHK_BUSY:
PUSH
;Check Busy Flag
CALL WRINS_CHK
CALL DELAY30uS
A
MOV P1,#FFH
$1
MOV A,#78H
;Contrast set
CLR RS
CALL WRINS_CHK
CALL DELAY30uS
SETB RW
SETB
E
MOV A,P1
MOV
A,#5EH
;Power/ICON/Contrast
;Follower control
;DISPLAY ON
CLR
E
CALL WRINS_CHK
CALL DELAY30uS
MOV P1,#FFH
CLR RS
SETB RW
MOV A,#6AH
SETB
NOP
CLR
JB
E
CALL WRINS_CHK
CALL DELAY30uS
E
A.7,$1
A
MOV A,#0CH
POP
RET
CALL WRINS_CHK
CALL DELAY30uS
MOV A,#01H
;CLEAR DISPLAY
;ENTRY MODE SET
CALL WRINS_CHK
CALL DELAY2mS
MOV A,#06H
CALL WRINS_CHK
CALL DELAY30uS
;-------------------------------------------------------------------
MAIN_START:
XXXX
XXXX
XXXX
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z
Serial interface & IIC interface ( fosc = 380kHz )
POWER ON and external reset
Wait time >40mS
After VDD stable
Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
N
DH IS2 IS1
Wait time >26.3μS
Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
N
DH IS2 IS1
Wait time >26.3μS
Internal OSC frequency
Power/ICON/Contrast control
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
BS F2 F1 F0
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
1
Bon
C5
C4
0
0
1
0
1
Ion
Wait time >26.3μS
Wait time >26.3μS
Contrast set
Follower control
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
1
1
C3
C2
C1
C0
Rab2 Rab1 Rab0
0
0
0
1
1
0
Fon
Wait time >26.3μS
Wait time >200mS
(for power stable)
Display ON/OFF control
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
1
D
C
B
Wait time >26.3μS
Initialization end
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¾
Initial Program Code Example For 8051 MPU ( Serial Interface ) :
;---------------------------------------------------------------------------------
INITIAL_START:
CALL HARDWARE_RESET
CALL DELAY40mS
MOV A,#38H
;FUNCTION SET
CALL WRINS_NOCHK ;8 bit, N=1,5*7dot
CALL DELAY30uS
MOV A,#39H
;FUNCTION SET
CALL WRINS_NOCHK ;8 bit, N=1,5*7dot,IS=1
CALL DELAY30uS
MOV A,#14H
;bias
CALL WRINS_NOCHK
CALL DELAY30uS
MOV A,#78H
;Contrast set
CALL WRINS_NOCHK
CALL DELAY30uS
MOV A,#5EH
;Power/ICON/Contrast control
;Follower control
CALL WRINS_NOCHK
CALL DELAY30uS
MOV A,#6AH
CALL WRINS_NOCHK
CALL DELAY200mS
MOV A,#0CH
;for power stable
;DISPLAY ON
CALL WRINS_NOCHK
CALL DELAY30uS
MOV A,#01H
;CLEAR DISPLAY
CALL WRINS_NOCHK
CALL DELAY2mS
MOV A,#06H
;ENTRY MODE SET
CALL WRINS_NOCHK ;CURSOR MOVES TO RIGHT
CALL DELAY30uS
;---------------------------------------------------------------------------------
MAIN_START:
XXXX
XXXX
XXXX
XXXX
.
.
.
;---------------------------------------------------------------------------------
WRINS_NOCHK:
PUSH
MOV
CLR
1
R1,#8
RS
$1
RLC
A
MOV SI,C
SETB SCL
NOP
CLR
SCL
DJNZ R1,$1
POP
1
CALL DLY1.5mS
RET
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Interfacing to the MPU
The ST7036 can send data in two 4-bit operations/one 8-bit operation, serial 1 bit operation or fast I2C operation,
thus allowing interfacing with 4-bit, 8-bit or I2C MPU.
z
For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3
are disabled. The data transfer between the ST7036 and the MPU is completed after the 4-bit data has been
transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB4 to DB7)
are transferred before the four low order bits (for 8-bit operation, DB0 to DB3). The busy flag must be
checked (one instruction) after the 4-bit data has been transferred twice. Two more 4-bit operations then
transfer the busy flag and address counter data.
¾
Example of busy flag check timing sequence
CSB
RS
R/W
E
Internal
Functioning
operation
Not
IR7
IR3
AC3
AC3
IR7
IR3
DB7
Busy
Instruction write
Busy flag check
Busy flag check
Instruction write
¾
Intel 8051 interface(4 Bit)
16/24
COM1 to
COM16/24
4
P1.0 to P1.3
DB4 to DB7
P3.0
P3.1
P3.2
P3.3
RS
R/W
E
CSB
SEG1 to 100/80
SEG100/80
Intel 8051 Serial
ST7036
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z
For 8-bit interface data, all eight bus lines (DB0 to DB7) are used.
¾
Example of busy flag check timing sequence
CSB
RS
R/W
E
Internal
Functioning
operation
Not
Data
Busy
Busy
Data
DB7
Busy
Instruction
write
Busy flag
check
Busy flag
check
Busy flag
check
Instruction
write
¾
Intel 8051 interface(8 Bit)
16/24
COM1 to
COM16/24
8
P1.0 to P1.7
DB0 to DB7
P3.0
P3.1
P3.2
P3.3
RS
R/W
E
SEG1 to 100/80
SEG100/80
CSB
Intel 8051 Serial
ST7036
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z
For serial interface data, only two bus lines (DB6 to DB7) are used.
¾
Example of timing sequence
CSB
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
SI
SCL
RS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
¾
Intel 8051 interface ( Serial 4-line )
16/24
COM1 to
COM16/24
2
P1.6 to P1.7
SI , SCL
P3.0
P3.3
RS
CSB
SEG1 to 100/80
SEG100/80
Intel 8051 Serial
ST7036
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z
For I2C interface data, all eight bus lines (DB0 to DB7) are used.
¾
Example of timing sequence
. . . . . . .
ACK
ACK
SDA
SCL
D7
1
D6
2
D5
3
D4
4
D3
5
D2
6
D1
7
D0
8
D0
. . . . . .
9
¾
Intel 8051 interface ( I2C interface )
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ST7036
Supply Voltage for LCD Drive
z
When external bias resistors are used
(OPF1=1,OPF2=1)
VCC (2.7~ 5.5V)
VCC (2.7~ 5.5V)
Vext
Vext
OPF1 OPF2
OPF1 OPF2
VDD
V0
VDD
V0
VOUT
VR
VR
VOUT
VIN
VIN
R
R
V1
V2
CAP1P
CAP1N
CAP1P
CAP1N
V1
R
R
R
R
R
V2
V3
VLCD
VLCD
V3
V4
V4
R
VSS
VSS
1/4 bias
1/5 bias
GND
GND
z
When built-in bias resistors(9.6KΩ) are used
(OPF1=1,OPF2=0)
VCC(2.7~5.5V)
Vext
OPF1
VOUT
VDD
V0
VR
VIN
V1
V2
CAP1P
CAP1N
VLCD
V3
V4
VSS
OPF2
GND
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z
When built-in bias resistors(3.3KΩ) are used
(OPF1=0,OPF2=1)
VCC (2.7~ 5.5V)
Vext
OPF2
VOUT
VDD
V0
VR
VIN
V1
V2
CAP1P
CAP1N
VLCD
V3
V4
VSS
OPF1
GND
z
When built-in voltage followers with external Vout are used
(OPF1=0,OPF2=0 and instruction setting Bon=0,Fon=1)
VCC (2.7~ 5.5V)
Vext ≧ V0
Don't need to connect stable capacitor when
use internal follower circuit
VOUT
VIN
VDD
V0
V1
V2
CAP1P
CAP1N
VLCD
V3
V4
VSS
OPF1 OPF2
GND
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z
When built-in booster and voltage followers are used(OPF1=0,OPF2=0)
VCC (2.7~ 3.5V)
Don't need to connect stable capacitor when
use internal follower circuit
VIN
VDD
V0
VOUT
VOUT≦2xVDD
VDD=2.7~3.5V
VSS=0V
V1
V2
CAP1P
CAP1N
VLCD
V3
V4
2 x step-up voltage relationships
VSS
OPF1 OPF2
GND
Note:
Ensure V0 level stable, that must let |Vout-V0| over 0.5V(if panel size over 4.5”,the |Vout-V0| propose over 0.8V).
|Vout-V0|>0.5V(minimum)
Vout
V
0
V
CC
V
DD
GND
(System side)
V
SS
(ST7036Side)
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ST7036
¾
V0 voltage follower value calculation
VDD
Vout(≧VDD)
Vref
Ra
Rb
Ra
x
V0=(1+
)
Vref
V0
α+36
x
While Vref=VDD
(
)
100
Rb
VSS
C5
0
0
C4
0
0
C3
0
0
C2
C1
0
0
C0
0
1
α
0
1
2
Rab2 Rab1 Rab0 1+Rb/Ra
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1.25
1.5
1.8
2
2.5
3
3.75
0
0
0
0
0
0
1
0
:
:
:
:
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
61
62
63
8
7
6
5
4
3
2
1
0
1
3
5
7
9
11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63
V0 level (Condition:Booster on, Follower on, VIN=3.5V, VDD=3.0V,Display off)
The recommended curve: follower = 04H
Notes:
1.
Vout ≧V0 ≧V1 ≧V2 ≧V3 ≧V4 ≧Vss must be maintained.
2.
3.
If the calculation value of V0 is higher than Vout, the real V0 value will saturate to Vout.
internal built-in booster can only be used when OPF1=0,OPF2=0.
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8
7
6
5
4
3
2
1
0
0 2 4 6 8 10 12 14 1618 20 2224 26 2830 32 34 3638 40 4244 46 4850 52 54 5658 60 62
(Condition: VDD=5.0V, external Vout=7.0V)
V0 level
The recommended curve: followe=01H
Notes:
1.
Vout ≧V0 ≧V1 ≧V2 ≧V3 ≧V4 ≧Vss must be maintained.
2.
3.
If the calculation value of V0 is higher than Vout, the real V0 value will saturate to Vout.
internal built-in booster can only be used when OPF1=0,OPF2=0.
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ST7036
AC Characteristics
z
68 Interface
RS
R/W
tAW6
tAH6
CSB
tCYC6
tEWH
tEWL
E
tDS6
tDH6
tOH6
D0 to D7
(Write)
tACC6
D0 to D7
(Read)
(Ta =25°C )
VDD=2.7 to 4.5V
Rating
VDD=4.5 to 5.5V
Rating
Item
Signal
Symbol
Condition
Units
Min.
Max.
Min.
Max.
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
RS
RS
tAH6
tAW6
tCYC6
tDS6
20
20
400
100
40
-
-
20
20
280
80
20
-
-
—
—
—
ns
ns
ns
-
-
RS
-
-
D0 to D7
D0 to D7
D0 to D7
-
-
-
-
tDH6
Access time
tACC6
500
400
CL = 100 pF
ns
Output disable time
Enable H pulse time
Enable L pulse time
D0 to D7
tOH6
tEWH
tEWL
300
200
150
-
-
-
150
120
130
-
-
-
E
E
—
—
ns
ns
Note: All timing is specified using 20% and 80% of VDD as the reference.
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z
Serial Interface
tCSS
tCSH
CSB
RS
tSAS
tSAH
tSCYC
tSLW
tSHW
SCL
SI
tSDS
tSDH
(Ta = 25°C )
VDD=2.7 to 4.5V
Rating
VDD=4.5 to 5.5V
Rating
Item
Signal
Symbol
Condition
Units
Min.
Max.
Min.
Max.
Serial Clock Period
SCL “H” pulse width
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
200
20
160
10
250
10
10
-
-
-
-
-
-
-
-
-
100
20
120
10
150
10
20
-
-
-
-
-
-
-
-
-
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
SCL
—
ns
RS
SI
—
—
—
ns
ns
ns
Data hold time
20
20
CS-SCL time
CS
350
200
*1 All timing is specified using 20% and 80% of VDD as the standard.
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z
I2C interface
SDA
tBUF
tHIGH
tSU;DAT
tLOW
SCL
SDA
tf
tDH;STA
tr
tHD;DAT
tSU;STA
SU;STO
( Ta = 25°C )
VDD=2.7 to 4.5V VDD=4.5 to 5.5V
Rating Rating
Units
Item
Signal Symbol Condition
Min.
Max.
Min. Max.
SCL clock frequency
SCL clock low period
SCL clock high period
Data set-up time
Data hold time
SCL,SDA rise time
SCL,SDA fall time
fSCLK
DC
2.5
0.6
1800
0
300K
—
DC
1.3
0.6
700
0
400 kHz
—
µs
—
SCL
SDA
—
—
tLOW
tHIGH
tSU;DAT
tHD:DAT
tr
—
—
0.5
ns
—
0.5
µs
20+0.1Cb 300 20+0.1Cb 300
20+0.1Cb 300 20+0.1Cb 300
SCL,
SDA
—
—
ns
pf
tf
Capacitive load represent by each bus
Cb
—
400
—
400
line
Setup time for a repeated START
tSU;STA
tHD;STA
tSU;STO
—
—
0.6
1.8
—
—
0.6
1.0
—
—
µs
µs
condition
SDA
SCL
Start condition hold time
Setup time for STOP condition
—
0.6
—
0.6
—
µs
Bus free time between a Stop and
START condition
tBUF
—
1.3
—
1.3
—
µs
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ST7036
z
Internal Power Supply Reset
2.7V/4.5V
0.2V
0.2V
0.2V
trcc
tOFF
0.1mS≦trcc≦10mS
tOFF≧1mS
Notes:
tOFF compensates for the power oscillation period caused by momentary power supply
oscillations.
Specified at 4.5V for 5V operation, and at 2.7V for 3V operation.
For if 2.7V/4.5V is not reached during 3V/5V operation, internal reset circuit will not
operate normally.
z
Hardware reset(XRESET)
tr≦100nS
2.7V/4.5V
0.2V
tL>100uS
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ST7036
Absolute Maximum Ratings
Characteristics
Power Supply Voltage
LCD Driver Voltage
Input Voltage
Symbol
Value
VDD
VLCD
VIN
-0.3 to +7.0
7.0- Vss to -0.3+Vss
-0.3 to VDD+0.3
-40oC to + 90oC
-55oC to + 125oC
Operating Temperature
Storage Temperature
TA
TSTO
DC Characteristics
( TA = 25℃ , VDD = 2.7 V)
Symbol Characteristics
Test Condition
Min. Typ. Max. Unit
VDD
VLCD
VIN
Operating Voltage
LCD Voltage
Power Supply
-
2.7
2.7
-
-
-
-
4.5
7.0
3.5
V
V
V
V0-Vss
-
VDD=3.0V
ICC
VIH1
VIL1
VIH2
VIL2
VOH
VOL
Power Supply Current
(Use internal
-
160
230
VDD
0.8
uA
V
booster/follower circuit)
Input High Voltage
(Except OSC1)
0.7
-
-
-
-
-
-
-
VDD
Input Low Voltage
(Except OSC1)
-
- 0.3
V
Input High Voltage
(OSC1)
0.7
-
VDD
V
VDD
Input Low Voltage
(OSC1)
0.2
-
-
V
VDD
Output High Voltage
(DB0 - DB7)
0.7
IOH = -1.0mA
IOL = 1.0mA
-
V
VDD
Output Low Voltage
(DB0 - DB7)
-
0.8
V
RCOM Common Resistance VLCD = 4V, Id = 0.05mA
-
-
2
2
20
30
KΩ
KΩ
RSEG
Segment Resistance VLCD = 4V, Id = 0.05mA
Input Leakage
VIN = 0V to VDD
Current
ILEAK
-1
-
1
µA
IPUP
Pull Up MOS Current
Oscillation frequency
VDD = 3V
20
30
40
µA
fOSC
VDD = 3V,1/17duty
350
540
1100
kHz
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ST7036
DC Characteristics
( TA = 25℃, VDD = 4.5 V)
Symbol Characteristics
Test Condition
Min. Typ. Max. Unit
VDD
VLCD
VIN
Operating Voltage
-
4.5
2.7
-
-
-
-
5.5
7.0
3.5
V
V
V
LCD Voltage
V0-Vss
Power Supply
-
VDD=5.0V
(Use internal
ICC
VIH1
VIL1
VIH2
VIL2
VOH
VOL
Power Supply Current
-
240
340
VDD
0.8
µA
V
booster/follower circuit)
Input High Voltage
(Except OSC1)
0.7
-
-
-
-
-
-
-
VDD
Input Low Voltage
(Except OSC1)
-
-0.3
V
Input High Voltage
(OSC1)
0.7
-
VDD
1.0
V
VDD
Input Low Voltage
(OSC1)
-
-
V
Output High Voltage
(DB0 - DB7)
0.8
IOH = -1.0mA
IOL = 1.0mA
VDD
0.8
V
VDD
Output Low Voltage
(DB0 - DB7)
-
V
RCOM Common Resistance VLCD = 4V, Id = 0.05mA
-
-
2
2
20
30
KΩ
KΩ
RSEG
Segment Resistance VLCD = 4V, Id = 0.05mA
Input Leakage
VIN = 0V to VDD
Current
ILEAK
-1
-
1
µA
IPUP
Pull Up MOS Current
Oscillation frequency
VDD = 5V
65
95
125
µA
fOSC
VDD = 5V,1/17duty
350
540
1100
kHz
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ST7036
LCD Frame Frequency
z
1/16 Duty(ST7066U normal mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time
= 1.85us, 1/16 duty; 1/5 bias,1 frame =1.85us x 200 x 16 = 5.92ms=168.9Hz(SHLC and SHLS connect
to High)
200 clocks
1
2
3
4
16
1
2
3
4
16
1
2
3
4
16
V0
V1
V2
COM1
V3
V4
Vss
V0
V1
V2
COM2
V3
V4
Vss
V0
V1
V2
COM16
V3
V4
Vss
V0
V1
V2
SEGx off
V3
V4
Vss
V0
V1
V2
SEGx on
V3
V4
Vss
1 frame
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ST7036
z
1/17 Duty(Extension mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time =
1.85us, 1/17 duty; 1/5 bias,1 frame =1.85us x 200 x 17 = 6.29ms=159Hz(SHLC and SHLS connect to
High)
200 clocks
1
2
3
4
17
1
2
3
4
17
1
2
3
4
17
V0
V1
V2
COM1
V3
V4
Vss
V0
V1
V2
COM2
V3
V4
Vss
V0
V1
V2
COM17
V3
V4
Vss
V0
V1
V2
SEGx off
V3
V4
Vss
V0
V1
V2
SEGx on
V3
V4
Vss
1 frame
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ST7036
z
1/8 Duty(ST7066U normal mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time =
1.85us, 1/8 duty; 1/4 bias,1 frame = 1.85us x 400 x 8 = 5.92ms=168.9Hz(SHLC and SHLS connect to
High)
400 clocks
1
2
3
4
8
1
2
3
4
8
1
2
3
4
8
V0
V1
V2
V3
COM1
V4
Vss
V0
V1
V2
V3
COM2
V4
Vss
V0
V1
V2
V3
COM8
V4
Vss
V0
V1
V2
V3
SEGx off
V4
Vss
V0
V1
V2
V3
SEGx on
V4
Vss
1 frame
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ST7036
z
1/9 Duty(Extension mode); Assume the oscillation frequency is 540KHZ, 1 clock cycle time =
1.85us, 1/9 duty; 1/4 bias,1 frame = 1.85us x 400 x 9 = 6.66ms=150Hz(SHLC and SHLS connect to
High)
400 clocks
1
2
3
4
9
1
2
3
4
9
1
2
3
4
9
V0
V1
V2
V3
COM1
V4
Vss
V0
V1
V2
V3
COM2
V4
Vss
V0
V1
V2
V3
COM9
V4
Vss
V0
V1
V2
V3
SEGx off
V4
Vss
V0
V1
V2
V3
SEGx on
V4
Vss
1 frame
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ST7036
z
1/25 Duty( Extension mode and 3-line ); Assume the oscillation frequency is 540KHZ, 1 clock cycle
time = 1.85us, 1/25 duty; 1/4 bias,1 frame = 1.85us x 160 x 25 = 7.40ms=135.1Hz(SHLC and SHLS
connect to High)
z
160 clocks
1
2
3
4
25
1
2
3
4
25
1
2
3
4
25
V0
V1
V2
V3
COM1
V4
Vss
V0
V1
V2
V3
COM2
V4
Vss
V0
V1
V2
V3
COM25
V4
Vss
V0
V1
V2
V3
SEGx off
V4
Vss
V0
V1
V2
V3
SEGx on
V4
Vss
1 frame
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ST7036
I/O Pad Configuration
VDD
VDD
VDD
PMOS
PSB
PMOS
NMOS
NMOS
Input PAD (No Pull up):
RS, R/W, XRESET, CSB,
PSB, OPFx, OPRx, SHLx,
CLS, EXT
PSB=1==>E(Floating)
PSB=0==>E(Pull up)
VDD
VDD
VDD
Enable
PMOS
PMOS
PMOS
NMOS
Data
NMOS
I/O PAD (Pull up):
DB0-DB5
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ST7036
LCD and ST7036 Connection
SHLC/SHLS ITO option pin can select at different direction for LCD panel
z
z
z
z
Com normal direction/Seg normal direction
3 line x 16 characters, SHLC=1 SHLS=1
Com normal direction/Seg reverse direction
3 line x 16 characters, SHLC=1, SHLS=0
Com reverse direction/Seg normal direction
3 line x 16 characters, SHLC=0, SHLS=1
Com reverse direction/Seg reverse direction
3 line x 16 characters, SHLC=0, SHLS=0
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ST7036
Application Circuit ( Normal mode )
¾ Use internal resistor(9.6K ohm) and contrast adjust with external VR.
¾ Booster always off.
¾ Has 240 character of CGROM.
¾ Internal oscillator.
Dot Matrix LCD Panel
VDD
Vext
VDD
Com 1-24
Seg 1-80
VOUT
VIN
CLS
SHLC
SHLS
N3
CAP1N
EXT
OPF1
OPF2
OPR1
OPR2
CAP1P
ST7036
V0
V1
V2
V3
V4
RS,R/W,E,CSB,DB0-DB7,XRESET
To MPU
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ST7036
Application Circuit(Extension mode)
¾ Use internal follower circuit.
¾ Booster has 2 times pump.
¾ Has 240 character of CGROM.
¾ Internal oscillator.
Dot Matrix LCD Panel
Vext
VDD
Com 1-24
Seg 1-80
VOUT
VIN
CLS
SHLC
SHLS
N3
CAP1N
CAP1P
V0
V1
V2
V3
V4
EXT
ST7036
OPF1
OPF2
OPR1
OPR2
RS,R/W,E,CSB,DB0-DB7,XRESET
To MPU
z
When the heavy load is applied, the dotted line part could be added.
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ST7036
Application Circuit ( for glass layout )
z
ST7036 over Glass,6800 serial 8bit interface, with booster and follower circuit on
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ST7036
z
ST7036 over Glass,6800 serial 4bit interface, with booster and follower circuit on
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ST7036
z
ST7036 over Glass, serial interface, with booster and follower circuit on
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ST7036
z
ST7036 over Glass, I2C interface, with booster and follower circuit on
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