S3C72C8 [SAMSUNG]
The S3C72C8 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrangeable M; 该S3C72C8单芯片CMOS微控制器是专为高性能的采用三星最新的4位CPU内核， SAM47 （三星可布置M
| 型号： | S3C72C8 |
| 厂家： | 
SAMSUNG |
| 描述： | The S3C72C8 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrangeable M |
| 文件： | 总37页 (文件大小：233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3C72C8/P72C8
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
OVERVIEW
The S3C72C8 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With an up-to-96-dot LCD direct drive capability flexible 16-bit timer/counter, and 4-chanel comparator, the
S3C72C8 offers an excellent design solution for a low CDP and a card reader.
Up to 28 pins of the 44-pin QFP or up to 26 pins of the 42-pin SDIP package can be dedicated to I/O. Eight
vectored interrupts provide fast response to internal and external events. In addition, the S3C72C8's advanced
CMOS technology provides for low power consumption.
OTP
The S3C72C8 microcontroller is also available in OTP (One Time Programmable) version, S3P72C8. S3P72C8
microcontroller has an on-chip 8K-byte one-time-programable EPROM instead of masked ROM.
The S3P72C8 is comparable to S3C72C8, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C72C8/P72C8
FEATURES
Memory
Interrupts
•
•
•
Four internal vectored interrupts
•
•
512 ´ 4-bit RAM (including LCD display RAM)
8,192 ´ 8-bit ROM
Five external vectored interrupts
Two quasi-interrupts
28 I/O Pins
Bit Sequential Carrier
•
•
I/O: 26 pins (44-pin QFP, 42-pin SDIP)
Output only: 2 pins (44-pin QFP)
•
Supports 16-bit serial data transfer in arbitrary
format
LCD Controller/Driver
Memory-Mapped I/O Structure
Data memory bank 15
•
12 segments and 8 common terminals
(3, 4, and 8 common selectable)
Internal resistor circuit for LCD bias
All dot can be switched on/off
•
•
•
Power-Down Modes
•
•
•
Idle mode (only CPU clock stops)
Stop mode (main system oscillation stops)
Sub system clock stop mode
8-bit Basic Timer
•
•
4 interval timer functions
Watch-dog timer
Oscillation Sources
•
•
•
•
•
Crystal, ceramic, or RC for main system clock
Crystal oscillator for subsystem clock
16-bit Timer/Counter 1
•
•
•
•
•
•
Programmable 16-bit timer/counter
Arbitrary clock output
Main system clock frequency: 0.4 MHz-6 MHz
Subsystem clock frequency: 32.768 kHz
CPU clock divider circuit (by 4, 8, or 64)
External event counter
External clock signal divider
Configurable as two 8-bit timer/counters
Serial I/O interface clock generator
Instruction Execution Times
•
•
•
0.67, 1.33, 10.7 µs at 6 MHz (main)
0.95, 1.91, 15.3 µs at 4.19 MHz (main)
122 µs at 32.768 kHz (subsystem)
Watch Timer
•
Time interval generation: 0.5 s, 3.9 ms
at 32768 Hz
Operating Temperature
•
•
Four frequency outputs to BUZ pin
Clock source generation for LCD
° °
– 40 C to 85 C
•
Operating Voltage Range
1.8 V to 5.5 V
8-bit Serial I/O Interface
•
•
•
•
•
8-bit transmit/receive mode
Package Type
44-pin QFP, 42-pin SDIP
8-bit receive mode
•
LSB-first or MSB-first transmission selectable
Internal or external clock source
Comparator
•
4 channel mode: internal reference (4-bit
resolution)
•
3 channel mode: external reference
1-2
S3C72C8/P72C8
PRODUCT OVERVIEW
BLOCK DIAGRAM
Watch Dog
Timer
8-Bit Timer/
Counter1A
16-Bit
Timer/
Counter
Basic Timer
XIN
XOUT
8-Bit Timer/
Counter1B
RESET
XTIN XTOUT
Watch Timer
P2.0/CIN0/K0
P2.1/CIN1/K1
P2.2/CIN2/K2
P2.3/CIN3/K3
I/O Port 2
I/O Port 3
I/O Port 5
I/O Port 6
I/O Port 7
COM0-COM3
Interrupt
Control
Block
Instruction
Register
Clock
COM4-COM7/
SEG15-SEG12
LCD
Driver/
Controller
SEG0-SEG3/
P5.0-P5.3
P3.0/INTP30
P3.1/INTP31
SEG4-SEG7/
P6.0-P6.3
Program
Counter
Internal
Interrupts
SEG8-SEG11/
P7.0-P7.3
P5.0-P5.3/
SEG0-SEG3
SIO
Instruction Decoder
Program
Status Word
P6.0-P6.3/
SEG4-SEG7
SCK
P0.0/
P0.1/SO
P0.2/SI
Arithmetic
and
Logic Unit
I/O Port 0
I/O Port 1
P0.3/BTCO
Stack
Pointer
P7.0-P7.3/
SEG8-SEG11
P1.0/TCLO1/INT0
P1.1/TCL1/INT1
P1.2/CLO/INT2
P1.3/BUZ/INT4
512 x 4-Bit
Data
Memory
8 K Byte
Program
Memory
P4.0
P4.1
Comparator
Output Port 4
44 QFP Only
Figure 1-1. S3C72C8 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
S3C72C8/P72C8
PIN ASSIGNMENTS
COM5/SEG14
COM6/SEG13
COM7/SEG12
SEG11/P7.3
SEG10/P7.2
SEG9/P7.1
SEG8/P7.0
SEG7/P6.3
SEG6/P6.2
SEG5/P6.1
SEG4/P6.0
33
32
31
30
29
28
27
26
25
24
23
P2.0/CIN0/K0
1
2
3
4
5
6
7
8
P2.1/CIN1/K1
P2.2/CIN2/K2
P2.3/CIN3/K3
VDD
S3C72C8
(44-QFP-1010B)
VSS
XOUT
XIN
TEST
XTIN
XTOUT
9
10
11
Figure 1-2. S3C72C8 44-QFP Pin Assignment Diagram
1-4
S3C72C8/P72C8
PRODUCT OVERVIEW
COM2
COM3
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
COM1
COM0
1
2
3
4
5
6
7
8
COM4/SEG15
COM5/SEG14
COM6/SEG13
COM7/SEG12
SEG11/P7.3
SEG10/P7.2
SEG9/P7.1
SEG8/P7.0
SEG7/P6.3
SEG6/P6.2
SEG5/P6.1
SEG4/P6.0
SEG3/P5.3
SEG2/P5.2
SEG1/P5.1
SEG0/P5.0
P3.0/INTP30
P3.1/INTP31
P0.0/SCK
P1.0/TCLO1/INT0
P1.1/TCL1/INT1
P1.2/CLO/INT2
P1.3/BUZ/INT4
P2.0/CIN0/K0
P2.1/CIN1/K1
P2.2/CIN2/K2
P2.3/CIN3/K3
VDD
9
10
11
12
13
14
15
16
17
18
19
20
21
VSS
XOUT
XIN
TEST
XTIN
XTOUT
RESET
P0.3/BTCO
P0.2/SI
P0.1/SO
Figure 1-3. S3C72C8 42-SDIP Pin Assignment Diagram
1-5
PRODUCT OVERVIEW
S3C72C8/P72C8
Share Pin
Table 1-1. S3C72C8 Pin Descriptions
Description
Pin Name
Pin
Type
Circuit Number
Type
P0.0
P0.1
P0.2
P0.3
I/O 4-bit I/O port.
1-bit and 4-bit read/write and test are possible.
E–1
16 (22)
15 (21)
14 (20)
13 (19)
SCK
SO
SI
Individual pins are software configurable as
input or output; Individual pins are software
configurable as open-drain or push-pull output;
Individual pull-up resistors are software
assignable; pull-up resistors are automatically
disabled for output pins.
BTCO
P1.0
P1.1
P1.2
P1.3
I/O Same as port 0.
E–1
F–8
E–3
39 (3)
40 (4)
41 (5)
42 (6)
TCLO1/INT0
TCL1/INT1
CLO/INT2
BUZ/INT4
P2.0
P2.1
P2.2
P2.3
I/O Same as port 0 except that port 2 is not
configurable as n-channel open drain and is
configurable as analog input pin.
1 (7)
2 (8)
3 (9)
4 (10)
K0/CIN0
K1/CIN1
K2/CIN2
K3/CIN3
P3.0
P3.1
I/O 2-bit I/O port
18 (24)
17 (23)
INTP30
INTP31
1-bit and 4-bit read/write and test is possible.
Individual pins are software configurable as
input or output; Individual pins are software
configurable as open-drain or push-pull output;
2-bit pull-up resistors are software assignable;
pull-up resistors are automatically disabled for
output pins.
P4.0
P4.1
O
2-bit output port.
E-2
44
43
1-bit and 4-bit read/write and test is possible.
Individual pins are software configurable as
open-drain or push-pull output.
P5.0-P5.3
I/O 4-bit I/O port.
1-bit and 4-bit read/write and test is possible.
H-13
19-22
(25-28)
SEG0-SEG3
Individual pins are software configurable as
input or output; Individual pins are software
configurable as open-drain or push-pull output;
4-bit pull-up resistors are software assignable;
pull-up resistors are automatically disabled for
output pins.
P6.0-P6.3
P7.0-P7.3
I/O Same as port5
H-13
H-13
23-26
(29-32)
SEG4-SEG7
SEG8-SEG11
I/O Same as port5
27-30
(33-36)
1-6
S3C72C8/P72C8
PRODUCT OVERVIEW
Table 1-1. S3C72C8 Pin Descriptions (Continued)
Pin Name
SEG0-SEG3
SEG4-SEG7
SEG8-SEG11
SEG12-SEG15
COM0-COM3
Pin
Type
Description
Circuit Number
Type
Share Pin
P5.0-P5.3
P6.0-P6.3
P7.0-P7.3
COM7-COM4
–
I/O LCD segment display signal output pins
H–13
19-22
(25-28)
23-26
(29-32)
27-30
(33-36)
O
O
LCD segment display output pins
LCD common signal output pins
H–6
H–4
31-34
(37-40)
38-35
(2-1,
42-41)
COM4-COM7
I/O LCD common signal output pins
I/O Serial interface clock signal
H–6
E–1
34-31
(40-37)
SEG12–
SEG15
16 (22)
P0.0
SCK
SO
I/O Serial data output
E–1
E–1
E–1
E–1
E–1
E–1
E–1
B
15 (21)
14 (20)
13 (19)
39 (3)
P0.1
P0.2
SI
I/O Serial data input
BTCO
TCLO1
TCL1
CLO
BUZ
I/O Basic timer overflow signal
I/O Timer/counter external clock output
I/O Timer/counter external clock input
I/O Clock output
P0.3
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
–
40 (4)
41 (5)
I/O Frequency output to buzzer
42 (6)
I
12 (18)
RESET
System RESET pin
X
X
–
Clock input and output pins for main system
clock
–
8-7
(14-13)
–
in, out
XT XT
in, out
–
I
Clock input and output pins for subsystem
clock
–
10-11
(16-17)
–
CIN0–CIN3
K0–K3
Analog input port for Comparator
F–8
F–8
E–1
1-4
(7-10)
P2.0/K0
-P2.3/K3
I/O External interrupts. The triggering edge is
selectable.
1-4
(7-10)
P2.0/CIN0
-P2.3/CIN3
INT0
INT1
I
External interrupts. The triggering edge for
INT0 and INT1 is selectable.
39 (3)
40 (4)
P1.0/TCLO1
-P1.1/TCL1
1-7
PRODUCT OVERVIEW
S3C72C8/P72C8
Table 1-1. S3C72C8 Pin Descriptions (Continued)
Pin Name
INT2
Pin
Type
Description
Circuit Number
Type
Share Pin
P1.2/CLO
P1.3/BUZ
P3.0, P3.1
I
Quasi-interrupt with detection of rising or
falling edges.
E-1
41 (5)
42 (6)
INT4
I
I
External interrupt with detection of rising or
falling edges.
E-1
E-3
INTP30
INTP31
Key scan interrupts inputs.
18-17
(24-23)
TEST
VDD
I
System test pin
–
–
9 (15)
5 (11)
–
–
–
Power supply pin
VSS
–
Ground pin
–
6 (12)
–
NOTES:
1. Parentheses indicate pin number for 42-SDIP package.
2. Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
1-8
S3C72C8/P72C8
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
Pull-Up
Resistor
In
Schmitt Trigger Input
Figure 1-4. Pin Circuit Type B
VDD
Pull-up
Resistor
Pull-Up
Resistor
Enable
P-CH
VDD
PNE
Data
I/O
Output
DIsable
Figure 1-5. Pin Circuit Type E-1
1-9
PRODUCT OVERVIEW
S3C72C8/P72C8
VDD
PNE
Data
Out
Figure 1-6. Pin Circuit Type E-2
VDD
Pull-Up
Resistor
Pull-Up
Resistor
Enable
P-CH
PNE
Circuit
Type E-4
Ouput
Disable
I/O
Data
LCON.1
Figure 1-7. Pin Circuit Type E-3
1-10
S3C72C8/P72C8
PRODUCT OVERVIEW
VDD
PNE
Data
Out
Figure 1-8. Pin Circuit Type E-4
VDD
VLC1
COM Data
Out
LPOT.3
VLC4
VSS
Figure 1-9. Pin Circuit Type H-4
1-11
PRODUCT OVERVIEW
S3C72C8/P72C8
VDD
VLC1
VLC2
SEG/COM Data
Out
LPOT.3
VLC3
VLC4
VSS
Figure 1-10. Pin Circuit Type H-6
1-12
S3C72C8/P72C8
PRODUCT OVERVIEW
VDD
VLC2
SEG Data
Output Disable
Out
VLC3
VSS
Figure 1-11. Pin Circuit Type H-7
1-13
PRODUCT OVERVIEW
S3C72C8/P72C8
VDD
Pull-Up
Resistor
Enable
P-CH
Circuit
SEG
Type H-7
Output
DIsable
Circuit
Type E-4
Data
PNE
Figure 1-12. Pin Circuit Type H-13
1-14
S3C72C8/P72C8
PRODUCT OVERVIEW
VDD
Pull-up
Resistor
Pull-Up
Resistor
Enable
P-CH
VDD
Data
I/O
Output
DIsable
(Digital)
(Analog)
INTK
External REF
(P2.3 only)
+
-
Comparator
REF
Digital or Analog can be seleted
by software.
Figure 1-13. Pin Circuit Type F-8
1-15
S3C72C8/P72C8
ELECTRICAL DATA
15 ELECTRICAL DATA
OVERVIEW
In this section, information on S3C72C8 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— Comparator electrical characteristics
— A.C. electrical characteristics
— Operating voltage range
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
Miscellaneous Timing Waveforms
— A.C timing measurement points
— Clock timing measurement at X
in
— Clock timing measurement at XT
in
— TCL1 timing
— Input timing for RESET signal
— Input timing for external interrupts and quasi-interrupts
— Serial data transfer timing
15-1
ELECTRICAL DATA
S3C72C8/P72C8
Table 15-1. Absolute Maximum Ratings
°
(T = 25 C)
A
Parameter
Symbol
Conditions
Rating
Units
Supply Voltage
Input Voltage
VDD
VI
–
– 0.3 to + 6.5
V
All I/O pins active
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
– 15
V
V
Output Voltage
Output Current High
VO
IOH
–
One I/O pin active
mA
All I/O pins active
One I/O pin active
– 35
Output Current Low
IOL
+ 30 (Peak value)
mA
+ 15 *
Total for ports 0, 2–9
+ 100 (Peak value)
+ 60 *
Operating Temperature
Storage Temperature
TA
–
–
– 40 to + 85
°
°
C
Tstg
– 65 to + 150
C
* The values for Output Current Low ( IOL ) are calculated as Peak Value ´
Duty .
Table 15-2. D.C. Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
°
°
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input High
VIH1
0.8 VDD
–
VDD
V
Ports 0, 1, 2, 3, 5, 6, 7, RESET
Voltage
Input Low
Voltage
VIH2
VIL1
VIL2
VOH
Xin, Xout, XTin, and XTout
VDD – 0.1
–
VDD
0.2 VDD
0.1
–
–
V
V
Ports 0, 1, 2, 3, 5, 6, 7, RESET
Xin, Xout, XTin, and XTout
Output High
Voltage
VDD = 4.5 V to 5.5 V
IOH = – 1 mA
VDD – 1.0
–
Ports 0, 1, 2, 3, 4, 5, 6, 7
Output Low
Voltage
VOL
VDD = 4.5 V to 5.5 V
IOL = 15 mA
–
–
2.0
0.4
V
Ports 0, 1, 2, 3, 4, 5, 6, 7
VDD = 1.8 V to 5.5 V
IOL = 1.6 mA
15-2
S3C72C8/P72C8
ELECTRICAL DATA
Table 15-2. D.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input High
Leakage
Current
ILIH1
VI = VDD
All input pins except those
specified below for ILIH2
–
–
3
µA
ILIH2
ILIL1
VI = VDD
Xin, Xout, XTin, and XTout
20
Input Low
Leakage
Current
VI = 0 V
–
–
– 3
µA
All input pins except RESET, Xin,
Xout, XTin, and XTout
ILIL2
ILOH
VI = 0 V
Xin, Xout, XTin, and XTout
– 20
3
Output High
Leakage
Current
VO = VDD
All output pins
–
–
–
–
µA
µA
kW
Output Low
Leakage
Current
ILOL
VO = 0 V
All output pins
– 3
Pull-Up
Resistor
RLI
VI = 0 V; VDD = 5 V
Ports 0-3, 5-7 expect
25
47
100
RESET
VDD = 3 V
50
95
200
400
RL2
RLCD
VDC
100
220
V = 0 V; VDD = 5 V, RESET
I
VDD = 3 V
200
60
450
80
800
100
LCD Voltage
Dividing
Resistor
°
kW
Ta = 25 C
V
– 15 µA per common pin
– 15 µA per segment pin
–
–
–
–
120
120
mV
|
LC1-COMi|
Voltage Drop
(i = 0–7
V
VDS
|
LC1-SEGx|
Voltage Drop
(x = 0–15)
V
VLC1
VDD = 1.8 V to 5.5 V, 1/5 bias
LCD clock = 0 Hz, VLCD = VDD
0.8 VDD
0.2
–
0.8 VDD
0.8 VDD
0.2
+
V
LC1 Output
Voltage
V
VLC2
VLC3
VLC4
0.6 VDD
0.2
–
–
–
0.6 VDD
0.4 VDD
0.2 VDD
0.6 VDD
0.2
+
+
+
LC2 Output
Voltage
V
0.4 VDD
0.2
0.4 VDD
0.2
LC3 Output
Voltage
V
0.2 VDD
0.2
0.2 VDD
0.2
LC4 Output
Voltage
15-3
ELECTRICAL DATA
S3C72C8/P72C8
Table 15-2. D.C. Electrical Characteristics (Concluded)
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
DD
A
Parameter
Symbol
Conditions
Min
Typ
Max
Units
(2)
Supply
Current (1)
V
= 5 V ± 10%
6.0 MHz
4.19 MHz
–
3.0
2.3
8.0
5.5
mA
I
DD
DD1
Crystal oscillator
C1 = C2 = 22 pF
V
DD
= 3 V ± 10%
6.0 MHz
4.19 MHz
1.5
1.0
4.0
3.0
(2)
Idle mode
= 5 V ± 10%
6.0 MHz
4.19 MHz
1.3
1.2
2.5
1.8
I
DD2
V
DD
Crystal oscillator
C1 = C2 = 22 pF
V
DD
= 3 V ± 10%
6.0 MHz
4.19 MHz
0.5
0.44
1.5
1.0
(3)
(3)
V
= 3 V ± 10%
–
15.0
5.0
30
15
5
µA
I
I
DD
DD3
32 kHz crystal oscillator
Idle mode; V = 3 V ± 10%
DD
32 kHz crystal oscillator
DD4
I
Stop mode; SCMOD =
= 5 V ± 10%
2.5
DD5
V
0000B
XTin = 0V
DD
Stop mode;
0.5
3
V
DD
= 3 V ± 10%
V
= 5 V ± 10%
SCMOD =
0100B
0.2
0.1
3
2
DD
V
DD
= 3 V ± 10%
NOTES:
1. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
comparator, output port drive currents.
2. Data includes power consumption for subsystem clock oscillation.
3. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
4. Every values in this table is measured when the power control register (PCON) is set to "0011B".
15-4
S3C72C8/P72C8
ELECTRICAL DATA
Table 15-3. Main System Clock Oscillator Characteristics
°
°
(T = – 40 C + 85 C, V
= 1.8 V to 5.5 V)
DD
A
Oscillator
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max Units
Oscillation frequency (1)
Ceramic
Oscillator
–
0.4
–
6.0
MHz
Xin Xout
C1
C2
Stabilization time (2)
Stabilization occurs
–
–
–
4
ms
when V
is equal to
DD
the minimum
oscillator voltage
range; V
= 3.0 V.
DD
Oscillation frequency (1)
Crystal
Oscillator
–
0.4
6.0
MHz
Xin
Xout
C1
C2
Stabilization time (2)
V
V
= 2.7 V to 5.5 V
= 1.8 V to 5.5 V
–
–
–
–
–
–
10
30
ms
DD
DD
X input frequency (1)
in
External
Clock
0.4
6.0
MHz
Xin
Xout
X input high and low
in
–
83.3
–
–
2
1250
–
ns
level width (t , t
)
XH XL
RC
Frequency
MHz
Xin
Xout
R = 25 kW,
= 5 V
Oscillator
V
DD
R
–
1
–
R = 40 kW,
= 3 V
V
DD
NOTES:
1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
15-5
ELECTRICAL DATA
S3C72C8/P72C8
Table 15-4. Recommended Oscillator Constants
°
°
(T = – 40 C + 85 C, V
= 1.8 V to 5.5 V)
DD
A
Manufacturer
Series
Number (1)
Frequency Range
Load Cap (pF)
Oscillator Voltage
Range (V)
Remarks
C1
C2
MIN
2.0
MAX
5.5
TDK
3.58 MHz–6.0 MHz
3.58 MHz–6.0 MHz
33
33
Leaded Type
FCR” ðÿM5
(2)
(2)
2.0
5.5
On-chip C
FCR” ðÿMC5
Leaded Type
(3)
(3)
3.58 MHz–6.0 MHz
2.0
5.5
On-chip C
SMD Type
CCR” ðÿMC3
NOTES:
1. Please specify normal oscillator frequency.
2. On-chip C: 30pF built in.
3. On-chip C: 38pF built in.
Table 15-5. Subsystem Clock Oscillator Characteristics
°
°
(T = – 40 C + 85 C, V
= 1.8 V to 5.5 V)
DD
A
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max
Units
Configuration
Crystal
Oscillator
Oscillation frequency
(1)
–
32
32.768
35
kHz
XTin XTout
C1
C2
Stabilization time (2)
V
V
= 2.7 V to 5.5 V
–
–
1.0
–
2
s
DD
= 1.8 V to 5.5 V
–
10
DD
External
Clock
XT input frequency
in
(1)
32
–
100
kHz
XTin XTout
XT input high and
in
–
5
–
15
µs
low level width (t
,
XTL
t
)
XTH
NOTES:
1. Oscillation frequency and XT input frequency data are for oscillator characteristics only.
in
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
15-6
S3C72C8/P72C8
ELECTRICAL DATA
Table 15-6. Input/Output Capacitance
°
(TA = 25 C, VDD = 0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
Capacitance
CIN
f = 1 MHz; Unmeasured
pins are returned to VSS
–
–
15
pF
Output
Capacitance
COUT
CIO
–
–
–
–
15
15
pF
pF
I/O Capacitance
Table 15-7. Comparator Electrical Characteristics
(TA = – 40 C + 85 C, VDD = 4.0 V to 5.5 V, VSS = 0 V)
°
°
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input Voltage Range
–
–
0
–
V
V
DD
DD
Reference Voltage Range
VREF
VCIN1
–
–
–
–
0
–
–
–
–
–
V
V
Internal
mV
mV
mA
± 150
± 150
3
Input Voltage
Accuracy
External
VCIN2
–
Input Leakage Current
ICIN, IREF
– 3
15-7
ELECTRICAL DATA
S3C72C8/P72C8
Table 15-8. A.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Instruction Cycle
Time (note)
tCY
VDD = 2.7 V to 5.5 V
0.67
–
64
µs
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
1.33
0
64
TCL1 Input
Frequency
fTI1
–
–
–
1.5
MHz
µs
VDD = 1.8 V to 5.5 V
1
–
TCL1 Input High,
Low Width
tTIH1, tTIL1 VDD = 2.7 V to 5.5 V
0.48
VDD = 1.8 V to 5.5 V
1.8
tKCY
VDD = 2.7 V to 5.5 V; Input
800
–
–
ns
SCK Cycle Time
Output
650
VDD = 1.8 V to 5.5 V; Input
3200
Output
3800
325
tKH, tKL
VDD = 2.7 V to 5.5 V; Input
–
ns
SCK High, Low
Width
Output
tKCY/2 – 50
1600
VDD = 1.8 V to 5.5 V; Input
Output
tKCY/2 – 150
100
SI Setup Time to
tSIK
VDD = 2.7 V to 5.5 V; Input
–
–
–
–
ns
ns
SCK High
VDD = 2.7 V to 5.5 V; Output
VDD = 1.8 V to 5.5 V; Input
VDD = 1.8 V to 5.5 V; Output
VDD = 2.7 V to 5.5 V; Input
150
150
500
400
SI Hold Time to
t
KSI
SCK High
VDD = 2.7 V to 5.5 V; Output
VDD = 1.8 V to 5.5 V; Input
VDD = 1.8 V to 5.5 V; Output
400
600
500
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.
15-8
S3C72C8/P72C8
ELECTRICAL DATA
Table 15-8. A.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Output Delay for
tKSO
VDD = 2.7 V to 5.5 V; Input
–
–
300
ns
SCK to SO
VDD = 2.7 V to 5.5 V; Output
VDD = 1.8 V to 5.5 V; Input
VDD = 1.8 V to 5.5 V; Output
250
1000
1000
–
Interrupt Input
High, Low Width
tINTH, tINTL INT0, INT1, INT2, INT4,
K0– K3, INTP30, INTP31
10
10
–
–
µs
µs
tRSL
Input
–
RESET Input Low
Width
NOTE: Minimum value for INT0 is based on a clock of 2t
or 128 / fx as assigned by the IMOD0 register setting.
CY
Main Oscillator Frequency
(Divided by 4)
CPU CLOCK
1.5 MHz
6 MHz
1.05 MHz
0.75 MHz
4.2 MHz
3.0 MHz
15.6 kHz
1
2
3
4
5
6
7
1.8
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, or 64)
Figure 15-1. Standard Operating Voltage Range
15-9
ELECTRICAL DATA
S3C72C8/P72C8
Table 15-9. RAM Data Retention Supply Voltage in Stop Mode
°
°
(TA = – 40 C to + 85 C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply voltage
VDDDR
–
1.8
–
5.5
10
V
Data retention supply current
IDDDR
VDDDR = 1.8 V
–
0.1
µA
Release signal set time
tSREL
tWAIT
–
0
–
–
–
–
µs
217 / fx
Oscillator stabilization wait
ms
Released by RESET
(1)
time
(2)
Released by interrupt
–
–
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
15-10
S3C72C8/P72C8
ELECTRICAL DATA
TIMING WAVEFORMS
Internal Reset
Operation
Idle Mode
Stop Mode
Operating Mode
Data Retention Mode
VDD
VDDDR
Execution of
STOP Instruction
RESET
tWAIT
tSREL
Figure 15-2. Stop Mode Release Timing When Initiated By RESET
Idle Mode
Normal
Operating
Mode
Stop Mode
Data Retention Mode
VDD
VDDDR
tSREL
Execution of
STOP Instruction
tWAIT
Power-down Mode Terminating Signal
(Interrupt Request)
Figure 15-3. Stop Mode Release Timing When Initiated By Interrupt Request
15-11
ELECTRICAL DATA
S3C72C8/P72C8
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Measurement
Points
Figure 15-4. A.C. Timing Measurement Points (Except for XIN and XTIN)
1/fx
tXL
tXH
XIN
VDD - 0.1 V
0.1 V
Figure 15-5. Clock Timing Measurement at XIN
1/fxt
tXTL
tXTH
XTIN
VDD - 0.1 V
0.1 V
Figure 15-6. Clock Timing Measurement at XT
IN
15-12
S3C72C8/P72C8
ELECTRICAL DATA
1/fTI
tTIL
tTIH
TCL1
0.7 VDD
0.3 VDD
Figure 15-7. TCL1 Timing
tRSL
RESET
0.2 VDD
Figure 15-8. Input Timing for RESET Signal
tINTL
tINTH
INT0, 1, 2, 4
K0 to K3
INTP30, INTP31
0.8 VDD
0.2 VDD
Figure 15-9. Input Timing for External Interrupts and Quasi-Interrupts
15-13
ELECTRICAL DATA
S3C72C8/P72C8
tKCY
tKL
tKH
SCK
0.8 VDD
0.2 VDD
tSIK
tKSI
0.8 VDD
0.2 VDD
SI
Input Data
tKSO
SO
Output Data
Figure 15-10. Serial Data Transfer Timing
15-14
S3C72C8/P72C8
MECHANICAL DATA
16 MECHANICAL DATA
OVERVIEW
This section contains the following information about the device package:
— Package dimensions in millimeters
— Pad diagram
#42
#22
0-15
42-SDIP-600
#1
#21
39.50 MAX
39.10 ± 0.2
0.50 ± 0.1
1.00 ± 0.1
1.78
(1.77)
NOTE: Dimensions are in millimeters.
Figure 16-1. 42-SDIP-600 Package Dimensions
16-1
MECHANICAL DATA
S3C72C8/P72C8
13.20 ± 0.3
10.00 ± 0.2
0-8
+ 0.10
- 0.05
0.15
0.10 MAX
44-QFP-1010B
#44
+ 0.10
0.35 - 0.05
#1
0.05 MIN
0.80
(1.00)
2.05 ± 0.10
2.30 MAX
NOTE: Dimensions are in millimeters.
Figure 16-1. 44-QFP-1010B Package Dimensions
16-2
S3C72C8/P72C8
S3P72C8 OTP
17 S3P72C8 OTP
OVERVIEW
The S3P72C8 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C72C8
microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data
format.
The S3P72C8 is fully compatible with the S3C72C8, both in function and in pin configuration. Because of its
simple programming requirements, the S3P72C8 is ideal for use as an evaluation chip for the S3C72C8.
COM5/SEG14
COM6/SEG13
COM7/SEG12
SEG11/P7.3
SEG10/P7.2
SEG9/P7.1
SEG8/P7.0
SEG7/P6.3
SEG6/P6.2
SEG5/P6.1
SEG4/P6.0
33
32
31
30
29
28
27
26
25
24
23
P2.0/CIN0/K0
P2.1/CIN1/K1
SDAT/P2.2/CIN2/K2
SCLK/P2.3/CIN3/K3
VDD/VDD
1
2
3
4
5
6
7
8
VSS/VSS
S3P72C8
XOUT
XIN
VPP/TEST
XTIN
9
10
11
XTOUT
Figure 17-1. S3P72C8 44-QFP Pin Assignments
17-1
S3P72C8 OTP
S3C72C8/P72C8
COM2
COM3
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
COM1
COM2
1
2
3
4
5
6
7
8
COM4/SEG15
COM5/SEG14
COM6/SEG13
COM7/SEG12
SEG11/P7.3
SEG10/P7.2
SEG9/P7.1
SEG8/P7.0
SEG7/P6.3
SEG6/P6.2
SEG5/P6.1
SEG4/P6.0
SEG3/P5.3
SEG2/P5.2
SEG1/P5.1
SEG0/P5.1
P3.0/INTP30
P3.1/INTP31
P0.0/SCK
P1.0/TCLO1/INT0
P1.1/TCL1/INT1
P1.2/CLO/INT2
P1.3/BUZ/INT4
P2.0/CIN0/K0
P2.1/CIN1/K1
SDAT/P2.2/CIN2/K2
SCLK/P2.3/CIN3/K3
VDD/VDD
9
10
11
12
13
14
15
16
17
18
19
20
21
VSS/VSS
XOUT
XIN
VPP/TEST
XTIN
XTOUT
RESET/RESET
P0.3/BTCO
P0.2/SI
P0.1/SO
Figure 17-2. S3P72C8 42-SDIP Pin Assignments
17-2
S3C72C8/P72C8
S3P72C8 OTP
Table 17-1. Descriptions of Pins Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
P2.2
Pin Name
Pin No.
I/O
Function
SDAT
3 (9)
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input/push-pull output port.
P2.3
SCLK
4 (10)
9 (15)
I/O
I
Serial clock pin. Input only pin.
VPP(TEST)
TEST
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing
mode). When 12.5 V is applied, OTP is in
writing mode and when 5 V is applied, OTP is in
reading mode. (Option)
12 (18)
I
I
Chip initialization
RESET
RESET
VDD/VSS
VDD/VSS
Logic power supply pin. VDD should be tied to
+ 5 V during programming.
5/6 (11/12)
NOTE: Parentheses indicate pin number for 42-SDIP package.
Table 17-2. Comparison of S3P72C8 and S3C72C8 Features
S3P72C8
Characteristic
Program Memory
Operating Voltage (VDD
S3C72C8
8 Kbyte mask ROM
8 Kbyte EPROM
1.8 V to 5.5 V
)
1.8 V to 5.5 V
VDD = 5 V, VPP(TEST)=12.5V
OTP Programming Mode
Pin Configuration
44-QFP, 42-SDIP
44-QFP, 42-SDIP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP(TEST) pin of the S3P72C8, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 17-3 below.
Table 17-3. Operating Mode Selection Criteria
VDD
VPP (TEST)
REG/MEM
Address
(A15-A0)
R/W
Mode
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
17-3
S3P72C8 OTP
S3C72C8/P72C8
Table 17-4. D.C. Electrical Characteristics
°
°
(T = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
A
Parameter
Symbol
Conditions
VDD = 5 V ± 10%
Min
Typ
Max
Units
(2)
Supply
Current (1)
6.0 MHz
–
3.0
2.3
8.0
5.5
mA
IDD1
4.19 MHz
Crystal oscillator
C1 = C2 = 22 pF
VDD = 3 V ± 10%
6.0 MHz
4.19 MHz
1.5
1.0
4.0
3.0
(2)
Idle mode
VDD = 5 V ± 10%
6.0 MHz
4.19 MHz
1.3
1.2
2.5
1.8
IDD2
Crystal oscillator
C1 = C2 = 22 pF
VDD = 3 V ± 10%
6.0 MHz
4.19 MHz
0.5
0.44
1.5
1.0
(3)
VDD = 3 V ± 10%
–
15.0
5.0
30
15
5
mA
IDD3
32 kHz crystal oscillator
Idle mode; VDD = 3 V ± 10%
32 kHz crystal oscillator
(3)
IDD4
IDD5
Stop mode;
SCMOD =
2.5
VDD = 5 V ± 10%
0000B
XTIN = 0V
Stop mode;
0.5
3
VDD = 3 V ± 10%
VDD = 5 V ± 10%
SCMOD =
0100B
0.2
0.1
3
2
VDD = 3 V ± 10%
NOTES:
1. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
comparator, output port drive currents.
2. Data includes power consumption for subsystem clock oscillation.
3. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
4. Every values in this table is measured when the power control register (PCON) is set to "0011B".
17-4
S3C72C8/P72C8
S3P72C8 OTP
Main Oscillator Frequency
(Divided by 4)
CPU CLOCK
1.5 MHz
6 MHz
1.05 MHz
0.75 MHz
4.2 MHz
3.0 MHz
15.6 kHz
1
2
3
4
5
6
7
1.8
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, or 64)
Figure 17-3 Standard Operating Voltage Range
17-5
S3P72C8 OTP
S3C72C8/P72C8
NOTES
17-6
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