S3C72G9XX-QX [SAMSUNG]
Microcontroller, 4-Bit, MROM, 4.19MHz, CMOS, PQFP100, 14 X 20 MM, QFP-100;
| 型号： | S3C72G9XX-QX |
| 厂家： | 
SAMSUNG |
| 描述： | Microcontroller, 4-Bit, MROM, 4.19MHz, CMOS, PQFP100, 14 X 20 MM, QFP-100 时钟 微控制器 外围集成电路 |
| 文件： | 总26页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3C72G9/P72G9
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
OVERVIEW
The S3C72G9 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With an up-to-896-dot LCD direct drive capability, and flexible 8-bit timer/counters, the S3C72G9 offers an
excellent design solution for a high-end LCD game.
Up to 12 pins of the 100-pin QFP package can be dedicated to I/O. Seven vectored interrupts provide fast
response to internal and external events. In addition, the S3C72G9's advanced CMOS technology provides for
low power consumption.
OTP
The S3C72G9 microcontroller is also available in OTP (One Time Programmable) version, S3P72G9. S3P72G9
microcontroller has an on-chip 32 K-byte one-time-programmable EPROM instead of masked ROM. The
S3P72G9 is comparable to S3C72G9, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C72G9/P72G9
FEATURES
Memory
Interrupts
•
•
•
Three Internal vectored interrupt
•
•
768 ´ 4-bit RAM (excluding LCD display RAM)
32,768 ´ 8-bit ROM
Four external vectored interrupts
Two quasi-interrupts
12 I/O Pins
Memory-Mapped I/O Structure
Data memory bank 15
•
I/O: 12 pins
•
LCD Controller/Driver
Power-Down Modes
•
56 segments and 16 common terminals
(8, 12 and 16 common selectable)
Capacitor bias for LCD output.
Voltage booster and regulator
•
•
•
Idle mode (only CPU clock stops)
Stop mode (main system oscillation stops)
Subsystem clock stop mode
•
•
•
All dots can be switched on/off
Oscillation Sources
•
•
•
•
•
Crystal, ceramic, or RC for main system clock
Crystal oscillator for subsystem clock
8-bit Basic Timer
•
•
4 interval timer functions
Watch-dog timer
Main system clock frequency: 0.4-4.19 MHz
Subsystem clock frequency: 32.768 kHz
CPU clock divider circuit (by 4, 8, or 64)
One 16-bit Timer/Counter 1
•
•
Programmable 16-bit timer
Instruction Execution Times
Arbitrary clock output (TCLO1)
•
•
0.95, 1.91, 15.3 µs at 4.19 MHz (main)
122 µs at 32.768 kHz (subsystem)
•
•
Inverted clock output (TCLO1)
Configurable two 8-bit timer/counters
Operating Temperature
Watch Timer
° °
– 40 C to 85 C
•
•
Time interval generation: 0.5 s, 3.9 ms
at 32768 Hz
Operating Voltage Range
2.2 V to 3.4 V (0.4 MHz to 4.19 MHz)
•
•
Four frequency outputs to BUZ pin and BUZ pin
•
Clock source generation for LCD
Package Type
100-pin QFP or pellet
Battery Level Detector
•
•
•
Programmable low voltage detector
One criteria voltage (2.4 V)
1-2
S3C72G9/P72G9
PRODUCT OVERVIEW
BLOCK DIAGRAM
X
IN
X
OUT
Basic
(Watchdog)
Timer
RESET
XTIN
XTOUT
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
Interrupt
Control
Block
Instruction
Register
I/O Port 1
Watch
Timer
Clock
P0.3/BUZ/K3
P0.2/ BUZ/K2
P0.1/ TCLO1/K1
P0.0/TCLO1/K0
Program
Counter
TEST 2
CA
I/O Port 0
I/O Port 2
Voltage
Regulator/
Booster
Internal
Interrupts
CB
P2.0/CLO
P2.1/TCL1
P2.2
Program
Status Word
Instruction Decoder
SEG0-SEG55
COM0-COM15
VLC1-VLC5
LCD Driver/
Controller
P2.3
8-bit Timer
Counter 1A
Arithmetic
and
Logic Unit
16-bit
Timer
Counter 1
Stack
Pointer
Battery
Level
Detector
8-bit Timer
Counter 1B
768 x 4-bit
Data
Memory
32-Kbyte
Program
Memory
Figure 1-1. S3C72G9 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
S3C72G9/P72G9
PIN ASSIGNMENTS
SEG18
SEG19
SEG21
SEG22
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VLC3
VLC4
VLC5
CA
CB
TEST2
1
2
3
4
5
6
7
8
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
BUZ/P0.3/K3
BUZ/P0.2/K2
TCLO1/P0.1/K1
TCLO1/P0.0/K0
VDD
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
XOUT
XIN
TEST1
XTIN
XTOUT
RESET
CLO/P2.0
TCL1/P2.1
P2.2
P2.3
COM15
COM14
COM13
COM12
Figure 1-2. S3C72G9 100-QFP Pin Assignment Diagram
1-4
S3C72G9/P72G9
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C72G9 Pin Descriptions
Description
Pin Name
P0.0
P0.1
P0.2
P0.3
Pin Type
Number
Share Pin
I/O
4-bit I/O port.
14
13
12
11
TCLO1/K0
1-bit and 4-bit read/write and test are possible.
Individual pins are software configurable as input or
output.
Individual pins are software configurable as open-
drain or push-pull output.
TCLO1/K1
BUZ/K2
BUZ/K3
Individual pull-up resistors are software assignable;
pull-up resistors are automatically disabled for output
pins.
P1.0
P1.1
P1.2
P1.3
I/O
I/O
Same as port 0
10
9
8
INT0
INT1
INT2
INT4
7
P2.0
P2.1
P2.2
P2.3
Same as port 0
23
24
25
26
CLO
TCL1
INT0, INT1
I/O
I/O
I/O
I/O
I/O
External interrupts. The triggering edge for INT0 and
INT1 is selectable.
10, 9
P1.0, P1.1
P1.2
INT2
Quasi-interrupt with detection of rising or falling
edges.
8
INT4
External interrupt with detection of rising and falling
edges.
7
P1.3
BUZ
2 kHz, 4 kHz, 8 kHz or 16 kHz frequency output for
buzzer signal.
11
12
P0.3/K3
P0.2/K2
Inverted BUZ signal
BUZ
CLO
TCL1
I/O
I/O
I/O
Clock output
23
24
13
P2.0
P2.1
External clock input for timer/counter 1
Timer/counter 1 inverted clock output
P0.1/K1
TCLO1
TCLO1
I/O
O
Timer/counter 1 clock output
LCD common signal output
LCD segment signal output
14
P0.0/K0
COM0–COM15
SEG0–SEG55
42-27
98-43
–
–
O
1-5
PRODUCT OVERVIEW
S3C72G9/P72G9
Table 1-1. S3C72G9 Pin Descriptions (Continued)
Pin Name
K0–K3
Pin Type
Description
External interrupt (triggering edge is selectable)
Main power supply
Number
14–11
15
Share Pin
P0.0–P0.3
–
I/O
–
VDD
VSS
–
I
Ground
16
22
–
–
Reset signal
RESET
CA, CB
–
–
Capacitor terminal for voltage boosting
LCD power supply
4, 5
–
–
VCL1–VCL2
VCL3–VCL5
99–100
1–3
Test input (must be connected VSS
)
TEST2
I
6
–
–
XIN
X
OUT
–
Crystal, ceramic or RC oscillator pins for system
clock
18, 17
,
XTIN XT
,
–
I
Crystal oscillator pins for subsystem clock
20, 21
19
–
–
OUT
(2)
TEST1
Test input (must be connected to VSS
)
NOTES
1. Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
2. Refer to chapter 16 for OTP version.
Table 1-2. Overview of S3C72G9 Pin Data
Pin Name
P0.0–P0.3
Share Pins
I/O Type
Reset Value
Circuit Type
I/O
Input
E-2
TCLO1/K0, TCLO1/K1
BUZ/K2, BUZ/K3
P1.0–P1.3
P2.0–P2.1
P2.2–P2.3
COM0–COM15
SEG0–SEG55
VDD
INT0, INT1, INT2, INT4
I/O
I/O
I/O
O
Input
Input
Input
Low
Low
–
E-2
E-2
E-2
H-6
H-6
–
CLO, TCL1
–
–
–
–
O
–
VSS
–
–
–
I
–
–
–
B
RESET
CA
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CB
VLC1–VLC5
XIN
X
OUT
,
XTIN XT
–
–
–
I
–
–
–
–
,
OUT
TEST1, 2
1-6
S3C72G9/P72G9
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
Pull-up
Resistor
PNE
VDD
V
DD
Resistor
Enable
I/O
P-Channel
N-Channel
Data
In
Output
Disable
Schmitt Trigger
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type E-2
VLC1
VLC2
VDD
VLC3/VLC4
Pull-up Resistor
Out
SEG/COM Data
VLC3/VLC4
IN
Schmitt Trigger
VLC5
VSS
Figure 1-4. Pin Circuit Type B
Figure 1-6. Pin Circuit Type H-6
1-7
S3C72G9/P72G9
ELECTRICAL DATA
14 ELECTRICAL DATA
OVERVIEW
In this section, information on S3C72G9 electrical characteristics is presented as tables and graphics.
The information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— Battery level detector characteristics
— Voltage booster characteristics
— A.C. electrical characteristics
— Operating voltage range
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at XIN
— Clock timing measurement at XTIN
— Input timing for RESET signal
— Input timing for external interrupts and quasi-interrupts
14-1
ELECTRICAL DATA
S3C72G9/P72G9
Table 14-1. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
Conditions
Rating
Units
V
VDD
VI
Supply Voltage
Input Voltage
–
– 0.3 to + 4.5
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
Ports 0–2
V
VO
IOH
Output Voltage
Output Current High
–
V
One I/O pin active
– 15
mA
All I/O pins active
One I/O pin active
– 30
IOL
Output Current Low
+ 30 (Peak value)
mA
+ 15 (note)
+ 100 (Peak value)
+ 60 (note)
Total for pins 0, 1
TA
°
Operating Temperature
Storage Temperature
–
–
– 40 to + 85
C
Tstg
°
C
– 65 to + 150
Duty .
NOTE: The values for Output Current Low ( I ) are calculated as Peak Value ´
OL
Table 14-2. D.C. Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 2.2 V to 3.4 V)
°
°
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VIH1
0.8 VDD
VDD
Input High
Voltage
–
V
Ports 0, 1, 2, and RESET
VIH2
XIN, XOUT, and XTIN
VDD – 0.1
–
VDD
V
IL1
0.2 VDD
Input Low
Voltage
–
V
Ports 0, 1, 2, and RESET
V
XIN, XOUT, and XTIN
0.1
–
IL2
V
OH
VDD = 2.2 V to 3.4 V
IOH = – 1 mA
VDD – 1.0
Output High
Voltage
–
–
V
V
Ports 0, 1, 2
V
VDD = 2.2 V to 3.4 V
IOL = 5 mA
Output Low
Voltage
–
1.0
OL
Ports 0, 1, 2
14-2
S3C72G9/P72G9
ELECTRICAL DATA
Table 14-2. D.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 2.2 V to 3.4 V)
Parameter
Input High
Symbol
Conditions
Min
Typ
Max
Units
ILIH1
VI = VDD
–
–
3
µA
Leakage Current
All input pins except those specified
below for ILIH2
ILIH2
VI = VDD
20
RESET, XIN, XOUT, XTIN and XTOUT
ILIL1
VI = 0 V
Input Low
–
–
– 3
µA
Leakage Current
All input pins except RESET, XIN,
XOUT, XTIN and XTOUT
ILIL2
VI = 0 V
– 20
XIN, XOUT, XTIN and XTOUT
ILOH
ILOL
VO = VDD
Output High
Leakage Current
–
–
–
–
3
µA
µA
kW
All output pins
VO = 0 V
Output Low
Leakage Current
– 3
All output pins
VI = 0 V; VDD = 3 V, Ports 0–2
RL1
RL2
Pull-up Resistor
50
100
450
200
800
200
VI = 0 V; VDD = 3 V, RESET
|VLCD–COMi|
Voltage Drop
(i = 0–15)
VDC
VLCD = 5.0 V
–
–
–
120
mV
– 15 µA per common pin
|VLCD–SEGx|
Voltage Drop
(i = 0–55)
VDS
VLCD = 5.0 V
–
120
– 15 µA per common pin
14-3
ELECTRICAL DATA
S3C72G9/P72G9
Table 14-2. D.C. Electrical Characteristics (Concluded)
°
°
(TA = – 40 C to + 85 C, VDD = 2.2 V to 3.4 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
IDD1
VDD = 3 V ± 10%
Supply
Current (1)
4.19 MHz
(PCON = 3H)
–
1.2
3
mA
crystal oscillator
C1 = C2 = 22 pF
IDD2
Idle mode; VDD = 3 V ± 10%
4.19 MHz
–
0.4
1
mA
(PCON = 3H)
crystal oscillator
C1 = C2 = 22 pF
(2)
VDD = 3 V ± 10%
–
–
–
15
6
30
15
3
mA
mA
mA
IDD3
32 kHz crystal oscillator
Idle mode; VDD = 3 V ± 10%
(2)
IDD4
32 kHz crystal oscillator (LCD off)
IDD5
Stop mode; VDD = 3 V ± 10%
SCMOD =
0000B,
0.5
XTIN = 0 V
Stop mode; VDD = 3 V ± 10%
SCMOD =
0000B
0.2
2
NOTES:
1. Data includes power consumption for subsystem clock oscillation.
2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
3. Current in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage booster circuit, and
output port drive currents.
14-4
S3C72G9/P72G9
ELECTRICAL DATA
Table 14-3. Main System Clock Oscillator Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 2.2 V to 3.4 V)
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
Oscillation frequency (1)
Ceramic
–
0.4
–
4.19
MHz
XIN
XOUT
Oscillator
C1
C2
Stabilization time (2)
Stabilization occurs
when VDD is equal
–
–
–
4
ms
to the minimum
oscillator voltage
range; VDD = 3 V
Crystal
–
0.4
4.19
MHz
XIN
XOUT
Oscillation frequency (1)
Oscillator
C1
C2
Stabilization time (2)
VDD = 3 V
–
–
–
–
10
ms
External
Clock
0.4
4.19
MHz
X
IN
X
OUT
XIN input frequency (1)
XIN input high and low
level width (tXH, tXL)
–
83.3
0.4
–
–
1250
2
ns
VDD = 3 V
RC
Frequency
MHz
XIN
XOUT
Oscillator
R
NOTES:
1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
14-5
ELECTRICAL DATA
S3C72G9/P72G9
Table 14-4. Recommended Oscillator Constants
°
°
(T = – 40 C + 85 C, V
= 2.2 V to 3.4 V)
DD
A
Manufacturer
Series
Number (1)
Frequency Range
Load Cap (pF)
Oscillator Voltage
Range (V)
Remarks
C1
33
(2)
C2
33
(2)
MIN
2.2
MAX
3.4
TDK
3.58 MHz–6.0 MHz
3.58 MHz–6.0 MHz
Leaded Type
FCR” ðÿM5
2.2
3.4
On-chip C
FCR” ðÿMC5
Leaded Type
(3)
(3)
3.58 MHz–6.0 MHz
2.2
3.4
On-chip C
SMD Type
CCR” ðÿMC3
NOTES:
1. Please specify normal oscillator frequency.
2. On-chip C: 30pF built in.
3. On-chip C: 38pF built in.
Table 14-5. Subsystem Clock Oscillator Characteristics
(T = – 40 C to + 85 C, VDD = 2.2 V to 3.4 V)
°
°
A
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
Oscillation frequency (1)
Crystal
–
32
32.768
35
kHz
XTIN XTOUT
Oscillator
C1
C2
Stabilization time (2)
VDD = 3.0 V
–
–
1.0
–
3
s
XTIN input frequency (1)
External
Clock
32
100
kHz
IN
OUT
XT XT
XTIN input high and low
–
5
–
15
µs
level width (tXTL, XTH)
t
NOTES:
1. Oscillation frequency and XT input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
14-6
S3C72G9/P72G9
ELECTRICAL DATA
Table 14-6. Input/Output Capacitance
°
(TA = 25 C, VDD = 0 V )
Parameter
Input
Capacitance
Symbol
Condition
Min
Typ
Max
Units
CIN
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
pF
COUT
CIO
Output
Capacitance
–
–
–
–
15
15
pF
pF
I/O Capacitance
Table 14-7. Battery Level Detector Characteristics
°
°
(T = – 40 C to + 85 C, VDD = 2.2 V to 3.4 V)
A
Parameter
Symbol
Condition
Min
Typ
Max
Units
BLD Voltage
VB0
BLC = 0
2.2
2.4
2.6
V
(when BREF = #05H)
BLD Circuit
Response Time
TB
fw = 32.768 kHz
–
–
–
–
1
ms
BLD Operating
Current
IBL
–
10
mA
14-7
ELECTRICAL DATA
S3C72G9/P72G9
Table 14-8. Voltage Booster Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 2.2 V to 3.4 V, C1 = C2 = C3 = C4 = 0.1 mF, CA/CB = 0.1 mF)
Parameter
Symbol
Conditions
Connect a 1 MW load
resistance between VSS and
Min
Typ
Max
Units
VLC5
Liquid Crystal
Drive Voltage (1)
LCR = 0
Typ
´ 0.9
0.85
Typ
´ 1.1
V
VLC5 (2) (no panel load)
LCR = 1
LCR = 2
LCR = 3
LCR = 4
LCR = 5
LCR = 6
LCR = 7
0.90
0.95
1.00
1.05
1.10
1.15
1.20
–
VLC4/3
VLC2
VLC1
IVB
Connect a 1 MW load resistance between 2 ´ VLC5
VSS and VLC4/3 (2) (no panel load)
2 ´ VLC5
´ 1.1
´ 0.9
–
–
Connect a 1 MW load resistance between 3 ´ VLC5
3 ´ VLC5
´ 1.1
VSS and VLC2 (2) (no panel load)
´ 0.9
Connect a 1 MW load resistance between 4 ´ VLC5
4 ´ VLC5
´ 1.1
VSS and VLC1 (2) (no panel load)
´ 0.9
VDD = 3 V
Voltage Regulator
& Booster
Consumed
Current
–
5.0
10
mA
LCR = 7
Display on (LCON = 3H)
NOTES:
1. The operating voltage of booster ranges from 2.4 V to 3.4 V.
2. The 1 MW load resistance is connected only to selected symbol (VLC1–VLC5) conditions to measure the properties
of the circuit.
Table 14-9. A.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, VDD = 2.2 V to 3.4 V)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Units
tCY
VDD = 2.2 V to 3.4 V
Instruction Cycle
Time (note)
0.95
–
64
µs
With subsystem clock (fxt)
114
10
122
–
125
–
fINTH, INTL
f
Interrupt Input
High, Low Width
INT0–INT2, INT4
K0–K3, TLC1
ms
ms
tRSL
Input
10
–
–
RESET Input Low
Width
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.
14-8
S3C72G9/P72G9
ELECTRICAL DATA
Main Oscillator Frequency
(Divided by 4)
CPU Clock
1.05 MHz
4.2 MHz
15.6 kHz
1
2
3
4
5
6
7
2.2
3.4
Supply Voltage (V)
CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 14-1. Standard Operating Voltage Range
Table 14-10. RAM Data Retention Supply Voltage in Stop Mode
°
°
(TA = – 40 C to + 85 C)
Parameter
Symbol
Conditions
Min
2.2
–
Typ
–
Max
3.4
10
–
Unit
V
VDDDR
Data retention supply voltage
Data retention supply current
Release signal set time
–
IDDDR
tSREL
tWAIT
VDDDR = 2.2 V
0.1
–
µA
µs
–
0
217/fx
Oscillator stabilization wait
time (1)
–
–
ms
Released by RESET
(2)
Released by interrupt
–
–
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
14-9
ELECTRICAL DATA
S3C72G9/P72G9
TIMING WAVEFORMS
Internal RESET
Operation
Idle Mode
Stop Mode
Normal Mode
Data Retention Mode
VDD
VDDDR
Execution of
STOP Instrction
RESET
tWAIT
tSREL
Figure 14-2. Stop Mode Release Timing When Initiated by RESET
Idle Mode
Normal
Mode
Stop Mode
Data Retention Mode
VDD
VDDDR
tSREL
Execution of
STOP Instrction
tWAIT
Power-down Mode Terminating Signal
(Interrupt Request)
Figure 14-3. Stop Mode Release Timing When Initiated by Interrupt Request
14-10
S3C72G9/P72G9
ELECTRICAL DATA
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Measurement
Points
Figure 14-4. A.C. Timing Measurement Points (Except for XIN and XTIN)
1/fx
tXL
tXH
XIN
VDD - 0.1 V
0.1 V
Figure 14-5. Clock Timing Measurement at XIN
1/fxt
tXTL
tXTH
XTIN
VDD - 0.1 V
0.1 V
Figure 14-6. Clock Timing Measurement at XTIN
14-11
ELECTRICAL DATA
S3C72G9/P72G9
t
RSL
RESET
0.2 VDD
Figure 14-7. Input Timing for RESET Signal
t
INTL
tINTH
INT0, 1, 2, 4,
K0 to K3
TCL1
0.8 VDD
0.2 VDD
Figure 14-8. Input Timing for External Interrupts
14-12
S3C72G9/P72G9
MECHANICAL DATA
15 MECHANICAL DATA
OVERVIEW
This section contains the following information about the device package:
— Package dimensions in millimeters
15-1
MECHANICAL DATA
S3C72G9/P72G9
23.90
20.00
0-8
+ 0.10
0.15 - 0.05
0.10 MAX
100-QFP-1420C
#100
+ 0.10
0.30 - 0.05
#1
0.05 MIN
2.65
0.65
0.15 MAX
(0.58)
3.00 MAX
0.80
NOTE: Dimensions are in millimeters.
Figure 15-1. 100-QFP-1420C Package Dimensions
15-2
S3C72G9/P72G9
S3P72G9 OTP
16 S3P72G9 OTP
OVERVIEW
The S3P72G9 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C72G9
microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data
format.
The S3P72G9 is fully compatible with the S3C72G9, both in function and in pin configuration.
Because of its simple programming requirements, the S3P72G9 is ideal for use as an evaluation chip for the
S3C72G9.
16-1
S3P72G9 OTP
S3C72G9/P72G9
SEG18
SEG19
SEG21
SEG22
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VLC3
VLC4
VLC5
CA
CB
TEST2
1
2
3
4
5
6
7
8
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
BUZ/P0.3/K3
BUZ/P0.2/K2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SDAT/TCLO1/P0.1/K1
SCLK/TCLO1/P0.0/K0
VDD/VDD
VSS/VSS
XOUT
XIN
VPP/TEST1
XTIN
XTOUT
RESET/RESET
CLO/P2.0
TCL1/P2.1
P2.2
P2.3
COM15
COM14
COM13
COM12
Figure 16-1. S3P72G9 Pin Assignments (100-QFP Package)
16-2
S3C72G9/P72G9
S3P72G9 OTP
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
P0.1
Pin Name
Pin No.
I/O
Function
SDAT
13
I/O
Serial data pin. Output port when reading and input
port when writing. Can be assigned as a Input/push-
pull output port.
P0.0
SCLK
14
19
I/O
I
Serial clock pin. Input only pin.
VPP (TEST1)
TEST
Power supply pin for EPROM cell writing (indicates
that OTP enters into the writing mode). When 12.5
V is applied, OTP is in writing mode and when 5 V
is applied, OTP is in reading mode. (Option)
22
I
I
Chip initialization
RESET
RESET
VDD/VSS
VDD/VSS
15/16
Logic power supply pin. VDD should be tied to +5 V
during programming.
Table 16-2. Comparison of S3P72G9 and S3C72G9 Features
S3P72G9
Characteristic
S3C72G9
Program Memory
32 Kbyte EPROM
2.2 V to 3.4 V
32 Kbyte mask ROM
2.2 V to 3.4 V
Operating Voltage (VDD
)
VDD = 5 V, VPP (TEST1) = 12.5 V
OTP Programming Mode
–
Pin Configuration
100 QFP
100 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP(TEST1) pin of the S3P72G9, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 16-3 below.
Table 16-3. Operating Mode Selection Criteria
VDD
VPP
(TEST1)
REG/MEM
Address
(A15–A0)
R/W
Mode
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
16-3
S3P72G9 OTP
S3C72G9/P72G9
Table 16-4. D.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, VDD = 2.2 V to 3.4 V)
A
Parameter
Symbol
Conditions
Min
Typ
Max Units
IDD1
VDD = 3 V ± 10%
Supply
Current (1)
–
1.2
3.0
mA
4.19 MHz (PCON = 3H) crystal oscillator
C1 = C2 = 22 pF
IDD2
Idle mode; VDD = 3 V ± 10%
0.4
1.0
4.19 MHz (PCON = 3H) crystal oscillator
C1 = C2 = 22 pF
(2)
VDD = 3 V ± 10%
–
15
6
30
1.5
3
µA
IDD3
32 kHz crystal oscillator
Idle mode; VDD = 3 V ± 10%
32 kHz crystal oscillator
(2)
IDD4
IDD5
Stop mode; VDD = 3 V ± 10%
SCMOD = 0000B,
XTIN = 0 V
0.5
0.2
Stop mode; VDD = 3 V ± 10%
SCMOD = 0100B
2
NOTES:
1. Data includes power consumption for subsystem clock oscillation.
2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
3. Current in the following circuits are not included; on-chip pull-up resistors, voltage boosting capacitors, and output
port drive currents.
16-4
S3C72G9/P72G9
S3P72G9 OTP
Main Oscillator Frequency
(Divided by 4)
CPU Clock
1.05 MHz
4.2 MHz
15.6 kHz
1
2
3
4
5
6
7
2.2
3.4
Supply Voltage (V)
CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 16-2. Standard Operating Voltage Range
16-5
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