S3C72I9XX-QX [SAMSUNG]
Microcontroller, 4-Bit, MROM, 6MHz, CMOS, PQFP100, 14 X 20 MM, QFP-100;
| 型号： | S3C72I9XX-QX |
| 厂家： | 
SAMSUNG |
| 描述： | Microcontroller, 4-Bit, MROM, 6MHz, CMOS, PQFP100, 14 X 20 MM, QFP-100 时钟 微控制器 外围集成电路 |
| 文件： | 总32页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3C72I9/P72I9
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
OVERVIEW
The S3C72I9 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With an up-to-896-dot LCD direct drive capability, 8-bit timer/counter 0, 16-bit timer/counter 1, and serial I/O, the
S3C72I9 offers an excellent design solution for a wide variety of applications which require LCD functions.
Up to 39 pins of the 100-pin QFP package can be dedicated to I/O. Eight vectored interrupts provide fast
response to internal and external events. In addition, the S3C72I9's advanced CMOS technology provides for low
power consumption and a wide operating voltage range.
OTP
The S3C72I9 microcontroller is also available in OTP (One Time Programmable) version, S3P72I9. S3P72I9
microcontroller has an on-chip 32 K-byte one-time-programable EPROM instead of masked ROM. The S3P72I9
is comparable to S3C72I9, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C72I9/P72I9
FEATURES SUMMARY
Memory
Watch Timer
•
Time interval generation: 0.5 s, 3.9 ms
at 32.768 Hz
•
•
8,192 ´ 4-bit RAM (excluding LCD display RAM)
32,768 ´ 8-bit ROM
•
•
4 frequency outputs to BUZ pin
Clock source generation for LCD
39 I/O Pins
•
•
I/O: 35 pins
Interrupts
Input only: 4 pins
•
•
•
Four internal vectored interrupts
LCD Controller/Driver
Four external vectored interrupts
Two quasi-interrupts
•
•
•
•
56 segments and 16 common terminals
8 and 16 common selectable
Bit Sequential Carrier
Supports 16-bit serial data transfer in arbitrary
format
Internal resistor circuit for LCD bias
All dot can be switched on/off
•
8-bit Basic Timer
Power-Down Modes
•
•
4 interval timer functions
Watchdog timer
•
•
Idle mode (only CPU clock stops)
Stop mode (main system clock and CPU clock
stop)
8-bit Timer/Counter 0
•
Sub-system clock stop mode
•
•
•
•
•
Programmable 8-bit timer
External event counter
Oscillation Sources
Arbitrary clock frequency output
External clock signal divider
Serial I/O interface clock generator
•
•
•
•
•
Crystal, ceramic, or RC for main system clock
Crystal oscillator for subsystem clock
Main system clock frequency: 0.4 - 6 MHz
Subsystem clock frequency: 32.768 kHz
CPU clock divider circuit (by 4, 8, or 64)
16-Bit Timer/Counter 1
•
•
•
•
Programmable 16-bit timer
External event counter
Instruction Execution Times
Arbitrary clock frequency output
External clock signal divider
•
•
•
0.67, 1.33, 10.7 µs at 6 MHz
0.95, 1.91, 15.3 µs at 4.19 MHz
122 µs at 32.768 kHz
8-bit Serial I/O Interface
•
•
•
•
8-bit transmit/receive mode
Operating Temperature
8-bit receive mode
° °
- 40 C to 85 C
•
LSB-first or MSB-first transmission selectable
Internal or external clock source
Operating Voltage Range
1.8 V to 5.5 V (3.0 MHz @ 1.8 V)
•
Memory-Mapped I/O Structure
Package Type
100-pin QFP
•
Data memory bank 15
•
1-2
S3C72I9/P72I9
PRODUCT OVERVIEW
BLOCK DIAGRAM
Basic
Timer
Watch
Timer
X
X
OUT
IN
XT XT
IN
RESET
OUT
P1.0-P1.3/
INT0-INT4
VLC1-VLC5
Input Port 1
COM0-COM7
Interrupt
Control
Block
Instruction
Register
LCD
Driver/
Controller
P2.0/CLO
P2.1/LCDCK
P2.2/LCDSY
Clock
P4.0-P5.3/
COM8-COM15
I/O Port 2
I/O Port 3
SEG0-SEG39
P3.0/TCLO0
P3.1/TCLO1
P3.2/TCL0
P3.3/TCL1
P9.3-P6.0/
Internal
SEG40-SEG55
Interrupts
Serial I/O
P4.0-P4.3/
COM8-COM11
I/O Port 4
I/O Port 5
Instruction
P5.0-P5.3/
COM12-COM15
Program
Status Word
P0.0/SCK/KO
P0.1/SO/K1
P0.2/SI/K2
I/O
Port 0
P6.0-P6.3
SEG55-SEG52
KS4-KS7
Arithmetic
and
Logic Unit
P0.3/BUZ/K3
I/O Port 6
I/O Port 7
Stack
Pointer
8-Bit
Timer/
Counter 0
P7.0-P7.3
SEG51-SEG48
P8.0-P8.3
SEG47-SEG44
I/O Port 8
I/O Port 9
8192 x 4-Bit
Data
Memory
32 K Byte
Program
Memory
16-Bit
TImer/
Counter 1
P9.0-P9.3
SEG43-SEG40
Figure 1-1. S3C72I9 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
S3C72I9/P72I9
PIN ASSIGNMENTS
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
P9.3/SEG40
P9.2/SEG41
P9.1/SEG42
P9.0/SEG43
P8.3/SEG44
P8.2/SEG45
P8.1/SEG46
P8.0/SEG47
P7.3/SEG48
P7.2/SEG49
P7.1/SEG50
P7.0/SEG51
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG4
SEG3
SEG2
SEG1
SEG0
VLC5
VLC4
VLC3
VLC2
1
2
3
4
5
6
7
8
9
VLC1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P0.0/SCK/K0
P0.1/SO/K1
P0.2/SI/K2
P0.3/BUZ/K3
VDD
S3C72I9
(100-QFP-1420C)
VSS
XOUT
XIN
TEST
XTIN
XTOUT
RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P2.0/CLO
P2.1/LCDCK
P2.2/LCDSY
P3.0/TCLO0
P6.3/SEG52/K7
P6.2/SEG53/K6
P6.1/SEG54/K5
Figure 1-2. S3C72I9 100-QFP Pin Assignment Diagram
1-4
S3C72I9/P72I9
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C72I9 Pin Descriptions
Description
Pin Name
P0.0
P0.1
P0.2
P0.3
Pin Type
I/O
Number
Share Pin
4-bit I/O port.
11
12
13
14
SCK/K0
SO/K1
SI/K2
1-bit and 4-bit read/write and test are possible.
Individual pins are software configurable as input or
output.
Individual pins are software configurable as open-
drain or push-pull output.
BUZ/K3
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
P1.0
P1.1
P1.2
P1.3
I
4-bit input port.
1-bit and 4-bit read and test are possible.
4-bit pull-up resistors are assignable by software.
23
24
25
26
INT0
INT1
INT2
INT4
P2.0
P2.1
P2.2
I/O
I/O
Same as port 0 except that port 2 is 3-bit I/O port.
Same as port 0.
27
28
29
CLO
LCDCK
LCDSY
P3.0
P3.1
P3.2
P3.3
30
31
32
33
TCLO0
TCLO1
TCL0
TCL1
P4.0-P4.3
I/O
I/O
4-bit I/O ports.
42-45
COM8-
COM11
COM12-
COM15
1-, 4-bit or 8-bit read/write and test are possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
P5.0-P5.3
46-49
P6.0-P6.3
P7.0-P7.3
Same as P4, P5.
50-53
54-57
SEG55/K4-
SEG52/K7
SEG51-
SEG48
P8.0-P8.3
P9.0-P9.3
I/O
I/O
Same as P4, P5.
58-61
62-65
SEG47-
SEG44
SEG43-
SEG40
Serial I/O interface clock signal.
11
P0.0/K0
SCK
SO
I/O
I/O
I/O
Serial data output.
Serial data input.
12
13
14
P0.1/K1
P0.2/K2
P0.3/K3
SI
BUZ
2 kHz, 4 kHz, 8 kHz or 16 kHz frequency output for
buzzer signal.
INT0, INT1
I
External interrupts. The triggering edge for INT0 and
INT1 is selectable.
23, 24
P1.0, P1.1
1-5
PRODUCT OVERVIEW
S3C72I9/P72I9
Table 1-1. S3C72I9 Pin Descriptions (Continued)
Pin Name
Pin Type
Description
Number
Share Pin
INT2
I
Quasi-interrupt with detection of rising or
falling edges.
25
P1.2
INT4
I
External interrupt with detection of rising or
falling edges.
26
P1.3
CLO
I/O
I/O
I/O
Clock output .
27
28
29
P2.0
P2.1
P2.2
LCDCK
LCDSY
LCD clock output for display expansion.
LCD synchronization clock output for display
expansion.
TCLO0
I/O
I/O
I/O
I/O
O
Timer/counter 0 clock output.
30
31
P3.0
P3.1
TCLO1
Timer/counter 1 clock output.
TCL0
External clock input for timer/counter 0.
External clock input for timer/counter 1.
LCD common signal output.
32
P3.2
TCL1
33
P3.3
COM0-COM7
COM8-COM11
COM12-COM15
SEG0-SEG39
34-41
42-45
46-49
–
I/O
P4.0-P4.3
P5.0-P5.3
–
O
LCD segment signal output.
5-1,
100-66
SEG40-SEG43
SEG44-SEG47
SEG48-SEG51
SEG52-SEG55
K0-K3
I/O
65-62
61-58
57-54
53-50
11-14
P9.3-P9.0
P8.3-P8.0
P7.3-P7.0
P6.3/K7-P6.0/K4
P0.0-P0.3
I/O
External interrupt. The triggering edge is
selectable.
K4-K7
50-53
15
P6.0-P6.3
V
DD
–
–
I
Main power supply.
Ground.
–
–
–
V
SS
16
Reset signal.
22
RESET
V
V
–
–
LCD power supply.
10-6
–
–
LC1- LC5
X
X
Crystal, Ceramic or RC oscillator pins for
system clock.
18, 17
in, out
XT XT
in,
–
I
Crystal oscillator pins for subsystem clock.
20, 21
19
–
–
out
Test signal input. (must be connected to V
)
TEST
SS
NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
1-6
S3C72I9/P72I9
PRODUCT OVERVIEW
Table 1-2. Overview of S3C72I9 Pin Data
Pin Names
Share Pins
I/O Type
I/O
Reset Value
Input
Circuit Type
P0.1, P0.3
P0.0, P0.2
SO/K1, BUZ/K3
E-1
E-2
I/O
Input
SCK/K0, SI/K2
P1.0-P1.3
P2.0-P2.2
P3.0-P3.1
P3.2-P3.3
INT0-INT2, INT4
CLO, LCDCK, LCDSY
TCLO0, TCLO1
TCL0, TCL1
I
Input
Input
Input
Input
Input
A-3
E
I/O
I/O
I/O
I/O
E
E-1
H-13
P4.0-P4.3
P5.0-P5.3
COM8-COM11
COM12-COM15
I/O
H-16
P6.0-P6.3
P7.0-P7.3
SEG55/K4-SEG52/K7
SEG51-SEG48
Input
Input
Input
I/O
I/O
H-13
H-13
P8.0-P8.3
P9.0-P9.3
SEG47-SEG44
SEG43-SEG40
COM0-COM7
SEG0-SEG39
VDD
–
–
–
O
O
–
High
High
–
H-3
H-15
–
VSS
–
–
–
–
–
–
–
I
–
–
–
–
–
–
–
B
–
–
–
–
RESET
VLC1
V
LC5
–
–
–
I
-
XIN, XOUT
XTIN, XTOUT
TEST
1-7
PRODUCT OVERVIEW
S3C72I9/P72I9
PIN CIRCUIT DIAGRAMS
VDD
VDD
Pull-Up
Resistor
P-Channel
N-Channel
In
In
Schmitt Trigger
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type B
VDD
VDD
Pull-Up
Resistor
P-Channel
Pull-Up
Resistor
Enable
Data
P-Channel
In
Out
N-Channel
Output
DIsable
Schmitt Trigger
Figure 1-4. Pin Circuit Type A-3
Figure 1-6. Pin Circuit Type C
1-8
S3C72I9/P72I9
PRODUCT OVERVIEW
VDD
Pull-up
Resistor
PNE
VDD
Pull-up
Resistor
Enable
P-CH
I/O
Data
N-CH
Output
DIsable
Figure 1-7. Pin Circuit Type E
VDD
Pull-up
Resistor
PNE
VDD
Pull-up
Resistor
Enable
P-CH
N-CH
I/O
Data
Output
DIsable
Schmitt Trigger
Figure 1-8. Pin Circuit Type E-1
1-9
PRODUCT OVERVIEW
S3C72I9/P72I9
VDD
Pull-up
Resistor
PNE
VDD
Pull-up
Resistor
Enable
P-CH
I/O
Data
N-CH
Output
DIsable
Schmitt Trigger
Figure 1-9. Pin Circuit Type E-2
1-10
S3C72I9/P72I9
PRODUCT OVERVIEW
VDD
VLC1
Out
COM
VLC4
VLC5
Figure 1-10. Pin Circuit Type H-3
VDD
VLC2
Out
SEG
VLC3
VLC5
Figure 1-11. Pin Circuit Type H-15
1-11
PRODUCT OVERVIEW
S3C72I9/P72I9
VDD
Pull-up
Resistor
Pull-up
Resistor
Enable
P-CH
COM/SEG
Type H-3
Output
Disable
Data
Type C
I/O
Figure 1-12. Pin Circuit Type H-13
VDD
Pull-up
Resistor
Pull-up
Resistor
Enable
P-CH
SEG
Type H-15
Type C
Output
Disable
Data
I/O
Schmitt Trigger
Figure 1-13. Pin Circuit Type H-16
1-12
S3C72I9/P72I9
ELECTRICAL DATA
14 ELECTRICAL DATA
OVERVIEW
In this section, information on S3C72I9 electrical characteristics is presented as tables and graphics.
The information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at XIN
— Clock timing measurement at XTIN
— TCL timing
— Input timing for RESET
— Input timing for external interrupts
— Serial data transfer timing
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
14-1
ELECTRICAL DATA
S3C72I9/P72I9
Table 14-1. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
Conditions
Rating
Units
V
VDD
VI
Supply Voltage
Input Voltage
–
- 0.3 to + 6.5
- 0.3 to VDD + 0.3
- 0.3 to VDD + 0.3
Ports 0-9
V
VO
IOH
Output Voltage
Output Current High
–
V
One I/O pin active
- 15
mA
All I/O pins active
One I/O pin active
- 35
IOL
Output Current Low
+ 30 (Peak value)
mA
+ 15 (note)
+ 100 (Peak value)
+ 60 (note)
Total for ports 0, 2-9
TA
°
Operating Temperature
Storage Temperature
–
–
- 40 to + 85
C
Tstg
°
C
- 65 to + 150
Duty .
NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value ´
Table 14-2. D.C. Electrical Characteristics
(TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
°
°
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VIH1
0.7 VDD
VDD
Input High
Voltage
All input pins except those
specified below for VIH2-VIH3
–
V
VIH2
0.8 VDD
VDD
Ports 0, 1, 6, P3.2, P3.3, and
RESET
VIH3
VIL1
XIN, XOUT, and XTIN
VDD - 0.1
–
VDD
0.3 VDD
Input Low
Voltage
All input pins except those
specified below for VIL2-VIL3
–
V
VIL2
0.2 VDD
Ports 0, 1, 6, P3.2, P3.3, and
RESET
VIL3
VOH
XIN, XOUT, and XTIN
0.1
–
VDD = 4.5 V to 5.5 V
IOH = - 1 mA
VDD - 1.0
Output High
Voltage
–
–
V
V
Ports 0, 2-9
VOL
VDD = 4.5 V to 5.5 V
IOL = 15 mA
Output Low
Voltage
–
2.0
Ports 0, 2-9
14-2
S3C72I9/P72I9
ELECTRICAL DATA
Table 14-2. D.C. Electrical Characteristics (Continued)
°
°
(TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
ILIH1
VI = VDD
All input pins except those
Input High
Leakage
Current
–
–
3
µA
specified below for I
LIH2
ILIH2
VI = VDD
20
- 3
XIN, XOUT, XTIN and RESET
,
ILIL1
V = 0 V
I
Input Low
Leakage
–
–
µA
All input pins except those
specified below for I
LIH2
Current
ILIL2
ILOH
V = 0 V
I
XIN, XOUT, and XTIN
- 20
3
VO = VDD
Output High
Leakage
Current
–
–
–
–
µA
µA
kW
All output pins
ILOL
VO = 0 V
Output Low
Leakage
Current
- 3
All output pins
RLI
V = 0 V; VDD = 5 V
I
Pull-Up
25
47
100
Resistor
Port 0-9
VDD = 3 V
50
95
200
400
RL2
RLCD
VDC
100
220
V = 0 V; VDD = 5 V, RESET
I
VDD = 3 V
200
25
450
55
800
80
LCD Voltage
Dividing
Resistor
TA = 25 °C
kW
V
- 15 µA per common pin
- 15 µA per segment pin
LCD clock = 0 Hz, VLC5 = 0 V
–
–
–
–
120
120
mV
|
DD-COMi|
Voltage Drop
(i = 0-15)
V
VDS
|
DD-SEGx|
Voltage Drop
(x = 0-55)
V
VLC1
VLC2
VLC3
VLC4
0.8 VDD - 0.2 0.8 VDD 0.8 VDD + 0.2
0.6 VDD - 0.2 0.6 VDD 0.6 VDD+ 0.2
0.4 VDD - 0.2 0.4 VDD 0.4 VDD + 0.2
0.2 VDD - 0.2 0.2 VDD 0.2 VDD + 0.2
V
LC1 Output
Voltage
V
LC2 Output
Voltage
V
LC3 Output
Voltage
V
LC4 Output
Voltage
14-3
ELECTRICAL DATA
S3C72I9/P72I9
Table 14-2. D.C. Electrical Characteristics (Concluded)
°
°
(TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
VDD = 5 V ± 10%
Min
Typ
Max
Units
(2)
Supply
Current
6.0 MHz
–
5.1
3.9
10.0
7.5
mA
IDD1
4.19 MHz
Crystal oscillator
C1 = C2 = 22 pF
VDD = 3 V ± 10%
6.0 MHz
4.19 MHz
2.5
1.8
4.0
3.0
(2)
Idle mode;
VDD = 5 V ± 10%
6.0 MHz
4.19 MHz
1.3
1.2
2.5
1.8
IDD2
Crystal oscillator
C1 = C2 = 22 pF
VDD = 3 V ± 10%
6.0 MHz
4.19 MHz
0.5
0.44
1.5
1.0
(3)
VDD = 3 V ± 10%
–
22.8
6.4
2.5
0.5
0.2
0.1
35
15
5
µA
IDD3
32 kHz crystal oscillator
Idle mode; VDD = 3 V ± 10%
32 kHz crystal oscillator
(3)
IDD4
Stop mode;
VDD = 5 V ± 10%
IDD5
SCMOD =
0000B
XT = 0V
Stop mode;
VDD = 3 V ± 10%
3
Stop mode;
VDD = 5 V ± 10%
SCMOD =
0100B
3
Stop mode;
2
VDD = 3 V ± 10%
NOTES:
1. Data includes power consumption for subsystem clock oscillation.
2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
3. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
output port drive currents.
14-4
S3C72I9/P72I9
ELECTRICAL DATA
Table 14-3. Main System Clock Oscillator Characteristics
°
°
(TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V)
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
Oscillation frequency (1)
Ceramic
Oscillator
–
0.4
–
6.0
MHz
XIN
XOUT
C1
C2
Stabilization time (2)
Stabilization occurs
when VDD is equal
–
–
–
4
ms
to the minimum
oscillator voltage
range; VDD = 3.0 V.
Oscillation frequency (1)
Crystal
Oscillator
–
0.4
6.0
MHz
XIN
XIN
XIN
XOUT
C1
C2
Stabilization time (2)
VDD = 3.0 V
–
–
–
–
–
10
30
ms
VDD = 2.0 V to 5.5 V
–
XIN input frequency (1)
External
Clock
0.4
6.0
MHz
XOUT
XIN input high and low
level width (tXH, tXL)
–
83.3
–
–
2
1250
–
ns
RC
Oscillator
Frequency
MHz
R = 20 kW,
XOUT
VDD = 5 V
R
–
1
–
R = 39 kW,
VDD = 3 V
NOTES:
1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
14-5
ELECTRICAL DATA
S3C72I9/P72I9
Table 14-4. Recommended Oscillator Constants
°
°
(TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V)
Manufacturer
Series
Number (1)
Frequency Range
Load Cap (pF)
Oscillator Voltage
Range (V)
Remarks
C1
33
(2)
C2
33
(2)
MIN
2.0
MAX
5.5
TDK
3.58 MHz-6.0 MHz
3.58 MHz-6.0 MHz
Leaded Type
FCR” ðÿM5
2.0
5.5
On-chip C
FCR” ðÿMC5
Leaded Type
(3)
(3)
3.58 MHz-6.0 MHz
2.0
5.5
On-chip C
SMD Type
CCR” ðÿMC3
NOTES:
1. Please specify normal oscillator frequency.
2. On-chip C: 30pF built in.
3. On-chip C: 38pF built in.
14-6
S3C72I9/P72I9
ELECTRICAL DATA
Table 14-5. Subsystem Clock Oscillator Characteristics
°
°
(T = - 40 C + 85 C, V
= 1.8 V to 5.5 V)
DD
A
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max
Units
Configuration
Crystal
Oscillator
Oscillation
frequency (1)
–
32
32.768
35
kHz
XTIN XTOUT
C1
C2
Stabilization time (2)
VDD = 2.7 V to 5.5 V
VDD = 2.0 V to 5.5 V
–
–
–
1.0
–
2
s
10
XTIN input
frequency (1)
External
Clock
32
–
100
kHz
IN
OUT
XT XT
XTIN input high and
low level width
–
5
–
15
µs
(tXTL, XTH)
t
NOTES:
1. Oscillation frequency and XT input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
Table 14-6. Input/Output Capacitance
°
(TA = 25 C, VDD = 0 V )
Parameter
Input
Capacitance
Symbol
Condition
Min
Typ
Max
Units
CIN
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
pF
COUT
CIO
Output
Capacitance
–
–
–
–
15
15
pF
pF
I/O Capacitance
14-7
ELECTRICAL DATA
S3C72I9/P72I9
Table 14-7. A.C. Electrical Characteristics
°
°
(TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
tCY
VDD = 2.7 V to 5.5 V
Instruction Cycle
Time (note)
0.67
–
64
µs
VDD = 2.0 V to 5.5 V
VDD = 2.7 V to 5.5 V
0.95
0
64
fTI0, TI1
f
TCL0, TCL1 Input
Frequency
–
–
1.5
MHz
µs
VDD = 2.0 V to 5.5 V
VDD = 2.7 V to 5.5 V
1
–
tTIH0, TIL0
t
TCL0, TCL1 Input
High, Low Width
0.48
tTIH1, TIL1
t
VDD = 2.0 V to 5.5 V
1.8
800
tKCY
VDD = 2.7 V to 5.5 V; Input
–
–
–
–
ns
ns
SCK Cycle Time
650
Internal SCK source; Output
VDD = 2.0 V to 5.5 V; Input
3200
3800
325
Internal SCK source; Output
t
, t
KH KL
VDD = 2.7 V to 5.5 V; Input
SCK High, Low
Width
tKCY/2-
50
Internal SCK source; Output
VDD = 2.0 V to 5.5 V; Input
1600
tKCY/2-
150
Internal SCK source; Output
tSIK
VDD = 2.7 V to 5.5 V; Input
SI Setup Time to
100
–
–
–
–
ns
ns
SCK High
VDD = 2.7 V to 5.5 V; Output
VDD = 2.0 V to 5.5 V; Input
VDD = 2.0 V to 5.5 V; Output
VDD = 2.7 V to 5.5 V; Input
150
150
500
400
tKSI
SI Hold Time to
SCK High
VDD = 2.7 V to 5.5 V; Output
VDD = 2.0 V to 5.5 V; Input
VDD = 2.0 V to 5.5 V; Output
400
600
500
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.
14-8
S3C72I9/P72I9
ELECTRICAL DATA
Table 14-7. A.C. Electrical Characteristics (Continued)
°
°
(TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
tKSO
VDD = 2.7 V to 5.5 V; Input
Output Delay for
–
–
300
ns
SCK to SO
VDD = 2.7 V to 5.5 V; Output
VDD = 2.0 V to 5.5 V; Input
VDD = 2.0 V to 5.5 V; Output
250
1000
1000
–
tINTH, INTL
t
Interrupt Input
High, Low Width
INT0, INT1, INT2, INT4,
K0-K7
10
10
–
–
µs
µs
tRSL
Input
–
RESET Input Low
Width
NOTE: Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting.
Main Oscillator Frequency
(Divided by 4)
CPU Clock
1.5 MHz
6 MHz
1.05 MHz
750 kHz
4.2 MHz
3 MHz
15.6 kHz
1
2
3
4
5
6
7
1.8 V
Supply Voltage (V)
CPU clock = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 14-1. Standard Operating Voltage Range
14-9
ELECTRICAL DATA
S3C72I9/P72I9
Table 14-8. RAM Data Retention Supply Voltage in Stop Mode
°
°
(TA = - 40 C to + 85 C)
Parameter
Symbol
Conditions
Min
1.8
–
Typ
–
Max
5.5
10
Unit
V
VDDDR
Data retention supply voltage
Data retention supply current
–
IDDDR
VDDDR = 1.8 V
0.1
µA
tSREL
tWAIT
Release signal set time
–
0
–
–
–
–
µs
217/fx
Oscillator stabilization wait
time (1)
ms
Released by RESET
(2)
Released by interrupt
–
–
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
14-10
S3C72I9/P72I9
ELECTRICAL DATA
TIMING WAVEFORMS
Internal RESET
Operation
Idle Mode
Stop Mode
Normal Mode
Data Retention Mode
VDD
VDDDR
Execution of
STOP Instrction
RESET
tWAIT
tSREL
Figure 14-2. Stop Mode Release Timing When Initiated by RESET
Idle Mode
Normal Mode
Stop Mode
Data Retention Mode
VDD
VDDDR
tSREL
Execution of
STOP Instrction
tWAIT
Power-down Mode Terminating Signal
(Interrupt Request)
Figure 14-3. Stop Mode Release Timing When Initiated by Interrupt Request
14-11
ELECTRICAL DATA
S3C72I9/P72I9
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Measurement
Points
Figure 14-4. A.C. Timing Measurement Points (Except for XIN and XTIN)
1/fx
tXL
tXH
XIN
VDD - 0.1 V
0.1 V
Figure 14-5. Clock Timing Measurement at XIN
1/fxt
tXTL
tXTH
XTIN
VDD - 0.1 V
0.1 V
Figure 14-6. Clock Timing Measurement at XTIN
14-12
S3C72I9/P72I9
ELECTRICAL DATA
1/fTI
tTIL
tTIH
TCL0
0.8 VDD
0.2 VDD
Figure 14-7. TCL Timing
tRSL
RESET
0.2 VDD
Figure 14-8. Input Timing for RESET Signal
tINTL
tINTH
INT0, 1, 2, 4,
K0 to K7
0.8 VDD
0.2 VDD
Figure 14-9. Input Timing for External Interrupts and Quasi-Interrupts
14-13
ELECTRICAL DATA
S3C72I9/P72I9
tKCY
tKL
tKH
SCK
0.8 VDD
0.2 VDD
tSIK
tKSI
0.8 VDD
0.2 VDD
SI
Input Data
tKSO
SO
Output Data
Figure 14-10. Serial Data Transfer Timing
14-14
S3C72I9/P72I9
MICHANICAL DATA
15 MICHANICAL DATA
OVERVIEW
The S3C72I9 microcontrollers are available in a 100-QFP-1420C package.
23.90 ± 0.3
20.00 ± 0.2
0-8
0.15+0.10
-0.05
0.10 MAX
100-QFP-1420C
#100
#1
0.65
0.3 ± 0.1
(0.58)
0.05 MIN
2.65 ± 0.10
3.00 MAX
0.10 MAX
0.80 ± 0.20
NOTE: Dimensions are in millimeters.
Figure 15-1. 100-QFP Package Dimension
15-1
S3C72I9/P72I9
S3P72I9 OTP
16 S3P72I9 OTP
OVERVIEW
The S3P72I9 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C72I9
microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data
format.
The S3P72I9 is fully compatible with the S3C72I9, both in function and in pin configuration. Because of its simple
programming requirements, the S3P72I9 is ideal for use as an evaluation chip for the S3C72I9.
16-1
S3P72I9 OTP
S3C72I9/P72I9
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
P9.3/SEG40
P9.2/SEG41
P9.1/SEG42
P9.0/SEG43
P8.3/SEG44
P8.2/SEG45
P8.1/SEG46
P8.0/SEG47
P7.3/SEG48
P7.2/SEG49
P7.1/SEG50
P7.0/SEG51
P6.3/SEG52/K7
P6.2/SEG53/K6
P6.1/SEG54/K5
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG4
SEG3
SEG2
SEG1
SEG0
VLC5
VLC4
VLC3
VLC2
1
2
3
4
5
6
7
8
9
VLC1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P0.0/SCK/K0
P0.1/SO/K1
SDAT/P0.2/SI/K2
SCLK/P0.3/BUZ/K3
VDD/VDD
S3P72I9
(100-QFP-1420C)
VSS/VSS
XOUT
XIN
VPP/TEST
XTIN
XTOUT
RESET/RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P2.0/CLO
P2.1/LCDCK
P2.2/LCDSY
P3.0/TCLO0
NOTE: The bolds indicate an OTP pin name.
Figure 16-1. S3P72I9 Pin Assignments (100-QFP Package)
16-2
S3C72I9/P72I9
S3P72I9 OTP
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
P0.2
Pin Name
Pin No.
I/O
Function
SDAT
13
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input/push-pull output port.
P0.3
SCLK
14
19
I/O
I
Serial clock pin. Input only pin.
VPP (TEST)
TEST
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing
mode). When 12.5 V is applied, OTP is in writing
mode and when 5 V is applied, OTP is in reading
mode. (Option)
22
I
I
Chip initialization
RESET
RESET
VDD/VSS
VDD/VSS
Logic power supply pin. VDD should be tied to
+ 5 V during programming.
15/16
Table 16-2. Comparison of S3P72I9 and S3C72I9 Features
S3P72I9
Characteristic
S3C72I9
Program Memory
32 Kbyte EPROM
32 Kbyte mask ROM
1.8 V to 5.5 V
Operating Voltage (V
)
DD
1.8 V to 5.5 V
VDD = 5 V, VPP (TEST) = 12.5 V
OTP Programming Mode
Pin Configuration
100 QFP
100 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP(TEST) pin of the S3P72I9, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 16-3 below.
Table 16-3. Operating Mode Selection Criteria
VDD
VPP
(TEST)
REG/
MEM
Address
(A15-A0)
R/W
Mode
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
16-3
S3P72I9 OTP
S3C72I9/P72I9
Table 16-4. D.C. Electrical Characteristics
°
°
(TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
VDD = 5 V ± 10%
Min
Typ
Max
Units
(2)
Supply
Current
6.0 MHz
–
5.1
3.9
10.0
7.5
mA
IDD1
4.19 MHz
Crystal oscillator
C1 = C2 = 22 pF
VDD = 3 V ± 10%
6.0 MHz
4.19 MHz
2.5
1.8
4.0
3.0
(2)
Idle mode;
VDD = 5 V ± 10%
6.0 MHz
4.19 MHz
1.3
1.2
2.5
1.8
IDD2
Crystal oscillator
C1 = C2 = 22 pF
VDD = 3 V ± 10%
6.0 MHz
4.19 MHz
0.5
0.44
1.5
1.0
(3)
VDD = 3 V ± 10%
–
22.8
6.4
2.5
0.5
0.2
0.1
35
15
5
µA
IDD3
32 kHz crystal oscillator
Idle mode; VDD = 3 V ± 10%
32 kHz crystal oscillator
(3)
IDD4
IDD5
Stop mode;
VDD = 5 V ± 10%
SCMOD =
0000B
XT = 0V
Stop mode;
VDD = 3 V ± 10%
3
Stop mode;
VDD = 5 V ± 10%
SCMOD =
0100B
3
Stop mode;
2
VDD = 3 V ± 10%
NOTES:
1. Data includes power consumption for subsystem clock oscillation.
2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
3. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
output port drive currents.
16-4
S3C72I9/P72I9
S3P72I9 OTP
Main Oscillator Frequency
(Divided by 4)
CPU Clock
1.5 MHz
6 MHz
1.05 MHz
750 kHz
4.2 MHz
3 MHz
15.6 kHz
1
2
3
4
5
6
7
1.8 V
Supply Voltage (V)
CPU clock = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 16-2. Standard Operating Voltage Range
16-5
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