S3C72H8 [SAMSUNG]
The S3C72H8 single-chip CMOS microcontroller has been designed for very high performance using Samsungs state-of-the-art 4-bit product development app; 该S3C72H8单芯片CMOS微控制器一直采用国家最先进的三星4位的产品开发应用程序专为非常高的性能
| 型号： | S3C72H8 |
| 厂家： | 
SAMSUNG |
| 描述： | The S3C72H8 single-chip CMOS microcontroller has been designed for very high performance using Samsungs state-of-the-art 4-bit product development app |
| 文件： | 总24页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3C72H8/P72H8
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
OVERVIEW
The S3C72H8 single-chip CMOS microcontroller has been designed for very high performance using Samsung's
state-of-the-art 4-bit product development approach, SAM47 (Samsung Arrangeable Microcontrollers). Its main
features are an up-to-13-digit LCD direct drive capability, 2-channel comparator inputs and outputs, and versatile
8-counter/ timers and 16-bit frequency counter. The S3C72H8 gives you an excellent design solution for a variety
of LCD-related applications, specially thermostat control application.
Up to 21 pins of the available 64-pin QFP packages can be dedicated to I/O. And six vectored interrupts provide
fast response to internal and external events.
In addition, the S3C72H8's advanced CMOS technology provides for low power consumption and a wide oper-
ating voltage range.
1-1
PRODUCT OVERVIEW
S3C72H8/P72H8
FEATURES
Architecture
LCD Controller/Driver
–
SAM47 4-bit CPU core
–
–
–
–
26 segment and 4 common terminals
Maximum 13-digit LCD direct drive capability
Display modes: Static, 1/2, 1/3, 1/4 duty
Memory
–
–
Data Memory: 512 ´ 4 bits
Voltage regulator and booster (1/3 bias: 1, 2, or
3V, 1/2 bias: 1.5, 3V)
Program Memory: 8196 ´ 8 bits
(Including LCD display RAM)
Analog Comparator
2 Ch Comparator (Each CnP, CnN, CnOUT pins)
Memory-Mapped I/O Structure
Data memory bank 15
–
–
Bit Sequential Carrier
Interrupts
–
Support 16-bit serial data transfer in arbitrary
format
–
–
–
Three internal vectored interrupts
Three external vectored interrupts
Two quasi-interrupts
I/O Ports
–
–
–
–
21 pins for standard I/O
8-Bit Timer/Counter (T0)
26 pins for LCD segment output
4 pins for LCD common output
Two input pins for external interrupts
–
–
–
–
Programmable 8-bit timer
External event counter
Arbitrary clock frequency output
External clock signal divider
Oscillation Sources
–
–
–
–
–
Crystal, ceramic, or RC for main system clock
Crystal or external oscillator for subsystem clock
Main system clock frequency: 4.19 MHz (typical)
Subsystem clock frequency: 32.768 kHz
16-Bit Frequency Counter (FC)
–
–
–
a 16-bit binary up-counter
External event counter
Gate function control
CPU clock divider circuit (by 4, 8, or 64 main, and
by 4 for sub clock)
Watch-Dog TIMER and Basic Timer
–
–
8-bit counter + 3-bit counter
Power Down Mode
Overflow signal of 8-bit counter makes a basic
timer interrupt. And control the oscillation warm-
up time
–
–
Idle mode (only CPU clock stops)
Stop mode (main or sub-system oscillation stops)
Voltage Level Detector
–
Overflow signal of 3-bit counter makes a system
reset
–
–
VDD level detection circuit (2.2, 2.4, 3, or 4.0V)
External pin level detect mode
Watch Timer
–
–
–
Real-time and interval time measurement
Operating Voltage Range
Four frequency outputs to buzzer sound
Clock source generation for LCD
–
–
1.8V to 5.5V at 3 MHz
2.0V to 5.5V at 4.19 MHz
Package Type
64-pin QFP
–
1-2
S3C72H8/P72H8
PRODUCT OVERVIEW
BLOCK DIAGRAM
SCLK
PP
V
/
TEST
XIN XTIN
SDAT
INT0, INT1 RESET
OUT
OUT
XT
X
P0.0/ExtRef
P0.1/SDAT
P0.2/SCLK
Watch
Timer
I/O Port 0
I/O Port 2
I/O Port 3
Interrupt
Control
Block
Instruction
Register
OTP
Block
Clock
P2.0/INT0
P2.1/INT1
P2.2/TCL0
P2.3/FCL
Basic
Timer
Watchdog
Timer
FCL
Program
Counter
P3.0/TCLO0
P3.1/BTCO
P3.2/CLO
16-Bit FREQ
Counter
Internal
Interrupts
C0OUT
C1OUT
P3.3/BUZ
8-Bit
Timer
TCL0
Program
Status
Word
P4.0/C0P
P4.1/C0N
P4.2/C0OUT
P4.3/C1OUT
P5.0/C1P
Instruction Decoder
TCLO0
I/O Port 4,5
I/O Port 6
COM0-COM3
SEG0-SEG25
LCD Driver/
Controller
Arithmetic
and
Logic Unit
P5.1/C1N
Stack
Pointer
CA, CB
Voltage
Booster
P6.0/KS0
P6.1/KS1
P6.2/KS2
P6.3/KS3
VLC0-VLC2
512 x 4-Bit
Data
Memory
8 K Byte
Program
Memory
Voltage
Level
Detector
Two Analog
Comparator
ExtRef
CnP
CnN
OUT
Cn
Figure 1-1. S3C72H8 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
S3C72H8/P72H8
PIN ASSIGNMENTS
CA
CB
VLC0
VLC1
VLC2
1
2
3
4
5
6
7
8
51
50
43
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
P5.1/C1N
P5.0/C1P
P0.0/ExtRef
SDAT/P0.1
SCLK/P0.2
VDD/VDD
VSS/VSS
XOUT
XIN
VPP/TEST
XTIN
9
S3C72H8
(TOP VIEW)
10
11
12
13
14
15
16
17
18
19
XTOUT
RESET/RESET
P2.0/INT0
P2.1/INT1
P2.2/TCL0
Figure 1-2. S3C72H8 Pin Assignment Diagram
1-4
S3C72H8/P72H8
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C72H8 Pin Descriptions
Description
Pin Name
Pin
Type
Number
(64-QFP)
Share
Pin
Circuit
Type
P0.0
P0.1
P0.2
I/O
I/O
I/O
I/O
3-bit I/O port.
6
7
8
ExtRef
D-1
D-1
D-1
E-1
1-bit and 4-bit read/write and test is possible.
Port 0 is software configurable as input or output. 3-bit
pull-up resistors are software assignable.
–
–
P2.0
P2.1
P2.2
P2.3
4-bit I/O port.
17
18
19
20
INT0
INT1
TCL0
FCL
1-bit and 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output. 4-bit pull-up resistors are software assignable.
P3.0
P3.1
P3.2
P3.3
Same as port 2.
21
22
23
24
TCLO0
BTCO
CLO
Ports 2 and 3 can be addressed by 1, 4, and 8-bit
read/write and test instruction.
BUZ
P4.0-P4.3
4/2-bit I/O ports. N-channel open-drain or push-pull
output. 1, 4, and 8-bit read/write and test is possible.
Ports 4 and 5 can be paired to support 8-bit data
transfer. Pull-up resistors are assignable to port unit by
software control.
29-32
C0P/
C0N/
C0OUT/
C1OUT
C1P/
P5.0-P5.1
P6.0-P6.3
33-34
25-28
C1N
I/O
4-bit I/O ports. Port 6 pins are individually software
configurable as input or output. 1-bit and 4-bit read/write
and test is possible. 4-bit pull-up resistors are software
assignable.
KS0-KS3
D-1
BTCO
CLO
I/O
I/O
I/O
Basic timer clock output
CPU clock output
22
23
24
P3.1
P3.2
P3.3
D-1
D-1
D-1
BUZ
2, 4, 8 or 16 kHz frequency output for buzzer sound with
4.19MHz main-system clock or 32.768 kHz sub-system
clock.
XOUT, XIN
–
–
Crystal, ceramic, or RC oscillator signal for main-
system clock. (For external clock input, use XIN and
11, 12
14, 15
17, 18
–
–
–
–
input XIN’s reverse phase to XOUT
)
XTOUT
XTIN
,
Crystal oscillator signal for sub-system clock.
(For external clock input, use XTIN and input XTIN’s
reverse phase to XTOUT
)
INT0, INT1
I/O
External interrupts. The triggering edge for INT0 and
Int1 is selectable. Only INT0 is synchronized with the
system clock.
P2.0, P2.1
D-1
1-5
PRODUCT OVERVIEW
S3C72H8/P72H8
Table 1-1. S3C72H8 Pin Descriptions (Continued)
Pin Name
Pin
Type
Description
Number
Share
Pin
Circuit
Type
(64-QFP)
25-28
6
KS0-KS3
ExtRef
I/O
I/O
I/O
I/O
I/O
O
Quasi-interrupt input with falling edge detection
External Reference input
P6.0-P6.3
D-1
D-1
D-1
D-1
D-1
H-16
H-16
–
P0.0
P2.2
P2.3
P3.0
–
TCL0
External clock input for timer/counter 0
External clock input for frequency counter
Timer/counter 0 clock output
19
FCL
20
TCLO0
21
COM0-COM3
SEG0-SEG25
CA, CB
LCD common signal output
61-64
35-60
1, 2
O
LCD segment output
–
–
Voltage booster capacitor pins
–
VLC0-VLC2
Voltage booster output pins (VLC0 is the regulated
output, VLC1 is the 2* VLC0 output, VLC2 is the 3* VLC0
output)
–
3-5
–
–
C0P, C0N,
C0OUT
I/O
Comparator 0 non-inverting input, inverting input and
output. C0Out can be configured as C-MOS push-pull
or N-Ch open drain output
29-31
32-34
P4.0-P4.2
P4.3-P5.1
–
–
C1P, C1N,
C1OUT
I/O
I
Comparator 1 non-inverting input, inverting input and
output. C1Out can be configured as C-MOS push-pull
or N-Ch open drain output
–
–
–
–
Reset signal for chip initialization
Main power supply
Ground
16
9
–
–
B
–
–
–
RESET
VDD
VSS
10
13
–
Test signal input (must be connected to VSS
)
VPP
TEST
SDAT
SCLK
VPP
I/O
I/O
–
Serial data for OTP programming
Serial clock for OTP programming
Power supply pin for EPROM cell writing
7
8
P0.1
P0.2
13
TEST
NOTE: Pull-up resistors for ports 0, 2, 3, and 6 are automatically disabled if they are configured to output mode.
But pull-up resistors for ports 4 and 5 are retained its state even though they are configured to output mode.
1-6
S3C72H8/P72H8
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
VDD
P-Channel
In
N-Channel
In
Figure 1-4. Pin Circuit Type B (Reset)
Figure 1-3. Pin Circuit Type A
VDD
VDD
Pull-up
Resistor
Resistor
P-Cannel
Enable
P-Channel
Data
Out
Data
Output
Disable
Circuit
Type C
I/O
N-Channel
Output
Disable
Input
Disable
Figure 1-6. Pin Circuit Type D-1 (P0, P2, P3, P6)
Figure 1-5. Pin Circuit Type C
1-7
PRODUCT OVERVIEW
S3C72H8/P72H8
VDD
PNE
VDD
Pull-up
Enable
Data
In/Out
Output
Disable
Input
Disable
To Data Bus
To Comparator
Figure 1-7. Pin Circuit Type E-1 (P4, P5)
VLC2
VLC1
SEG/COM
DATA
Out
VLC0
Figure 1-8. Pin Circuit Type H-16 (COM/SEG)
1-8
S3C72H8/P72H8
ELECTRICAL DATA
16 ELECTRICAL DATA
OVERVIEW
In this section, information on S3C72H8 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at XIN
— Clock timing measurement at XTIN
— TCL timing
— Input timing for RESET
— Input timing for external interrupts
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
16-1
ELECTRICAL DATA
S3C72H8/P72H8
Table 16-1. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
Conditions
Rating
– 0.3 to + 6.5
Units
VDD
VIN
VO
Supply Voltage
Input Voltage
–
–
V
– 0.3 to V
– 0.3 to V
– 7
+ 0.3
+ 0.3
DD
DD
Output Voltage
Output Current High
All I/O ports
IOH
One I/O pin active
mA
mA
All I/O ports active
One I/O pin active
– 40
+ 15
IOL
Output Current Low
Total pin circuit
–
+ 60
TA
°
C
Operating Temperature
Storage Temperature
– 40 to + 85
TSTG
–
– 65 to + 150
Table 16-2. D.C. Electrical Characteristics
(T = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
°
°
A
Parameter
Symbol
Conditions
FOSC = 6 MHz
Min
Typ
Max
Units
VDD
Operation
voltage
2.7
–
5.5
5.5
5.5
V
(CPU clock = 1.25 MHz)
FOSC = 4.19 MHz
2.0
1.8
(Instruction clock = 1.04 MHz)
FOSC = 3 MHz
(CPU clock = 0.75 MHz)
P0, P2, P3, P4, P5 and P6
VIH1
VIH2
VIH3
VIL1
VIL2
VIL3
VOH1
0.8 VDD
0.85 VDD
VDD-0.1
VDD
VDD
Input High
voltage
–
–
–
RESET
XIN
VDD
0.2 VDD
0.3 VDD
0.1
Input low
voltage
P0, P2, P3, P4, P5 and P6
RESET
XIN
VDD = 5.0V
VDD – 1.0
Output high
voltage
–
V
IOH = – 1 mA
All output pins
IOH = – 100 mA
VDD – 0.5
–
VOL1
VDD = 5.0 V, IOL = 2 mA
All output pins except VOL2
Output low
voltage
0.4
0.4
0.5
1.0
V
OL2
V
= 5.0 V, I
= 15 mA
OL
DD
Ports 2,3, and 4
16-2
S3C72H8/P72H8
ELECTRICAL DATA
Table 16-2. D.C. Electrical Characteristics (Continued)
°
°
(T = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Units
ILIH1
–
–
3
µA
VIN = VDD
Input high
leakage
current (note)
All input pins
ILIL1
ILOH
ILOL
RL1
–
–
–
–
– 3
3
VIN = VDD; All input pins
Input low
leakage
except RESET
current (note)
VOUT = VDD
Output high
leakage
current (note)
All I/O pins and output pins
–
–
– 3
100
VOUT = 0 V
Output low
leakage
current (note)
All I/O pins and output pins
25
47
VIN = 0 V, VDD = 5 V
KW
Pull-up
resistors
°
TA = 25 C, Ports 0-6
50
90
150
350
VDD = 3 V
RL2
150
250
VIN = 0 V; VDD = 5.0 V
°
TA = 25 C, RESET
ROSC1
400
700
1200
°
Oscillator
feed back
resistors
VDD = 5.0 V, TA = 25 C
XIN = VDD, XOUT = 0V
ROSC2
1000
–
1500
–
3000
120
°
VDD = 5.0 V, TA = 25 C
XTIN = VDD, XTOUT = 0V
-15 uA per common pin
VDC
mV
|VLC1-COMi|
Voltage Drop
(I = 0-3)
VDS
–
–
120
|VLC1-SEGi|
-15 uA per segment pin
Voltage Drop
(I = 0-25)
NOTE: Except X , X
, XT , XT
IN OUT
IN OUT
16-3
ELECTRICAL DATA
S3C72H8/P72H8
Table 16-2. D.C. Electrical Characteristics (Continued)
°
°
(T = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
A
Parameter
Symbol
Conditions
Main operation mode:
VDD = 5 V ± 10%, 6-MHz crystal
VDD = 5 V ± 10%, 4.19 MHz
VDD = 3 V ± 10%, 6-MHz crystal
VDD = 3 V ± 10%, 4.19 MHz
Min
Typ
Max
Units
IDD1
Supply
Current (note)
–
3.5
8
mA
2.5
1.6
1.2
1.8
5.5
4
3
IDD2
Main Idle mode:
–
3.5
VDD = 5 V ± 10%, 6-MHz crystal
VDD = 5 V ± 10%, 4.19 MHz
VDD = 3 V ± 10%, 6-MHz crystal
VDD = 3 V ± 10%, 4.19 MHz
1.4
0.6
0.5
15
3.0
1.2
1.1
30
IDD3
IDD4
IDD5
Sub operation mode:
VDD = 3 V, 32768Hz
Main OSC stop, except IVB, IVLD
–
–
–
uA
,
,
Icomp, ILCD and external load.
Sub Idle mode;
VDD = 3.0, 32768Hz
Main OSC stop, except IVB, IVLD
Icomp, ILCD and external load.
6
15
Stop mode; Main & Sub
OSC stop, VDD=5 V ± 10%
SCMOD =
0100B
0.3
0.1
3
1
uA
XTIN = 0V-
except IVD, VLD,
I
Icomp and
external load.
Stop & Sub OSC stop,
VDD = 3 V, except IVD,
IVLD, Lcomp and external
load.
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
is LCD controller/driver operating current, I is voltage booster current, Icomp is comparator current and I
VLD
I
LCD
VB
is voltage level detector current.
Table 16-3. Data Retention Supply Voltage in Stop Mode
°
°
(T = – 40 C to + 85 C)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VDDDR
Data retention supply
voltage
1.0
-
5.5
V
IDDDR
VDDDR = 1.0 V
Data retention supply
current
-
-
1
uA
Stop mode; Main & Sub
OSC stop.
except IVB, IVLD, ILCD and
external load.
16-4
S3C72H8/P72H8
ELECTRICAL DATA
Table 16-4. Main System Clock Oscillator Characteristics
°
°
(TA = – 40 C + 85 C, VDD = 1.8 V to 5.5 V)
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
(1)
Ceramic
Oscillator
–
0.4
–
6.0
MHz
Oscillation frequency
X
IN
X
OUT
C1
C2
(2)
Stabilization occurs
when VDD is equal to
–
–
–
4
6
ms
Stabilization time
the minimum oscillator
voltage range.
(1)
Crystal
Oscillator
–
0.4
MHz
Oscillation frequency
X
IN
X
OUT
C1
C2
(2)
VDD = 4.5 V to 5.5 V
VDD = 2.0 V to 4.5 V
–
–
–
–
–
–
10
30
ms
Stabilization time
(1)
External
Clock
0.4
6.0
MHz
XIN input frequency
X
IN
X
OUT
XIN input high and low
level width (tXH, tXL)
–
83.3
0.4
–
–
ns
Frequency (1)
VDD = 5 V
RC
Oscillator
–
2.5
MHz
X
IN
X
OUT
2.0
1.0
R = 25 K, VDD = 5 V
R = 50 K, VDD = 3 V
R
NOTES:
1. Oscillation frequency and X input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
16-5
ELECTRICAL DATA
S3C72H8/P72H8
Table 16-5. Subsystem Clock Oscillator Characteristics
°
°
(TA = – 40 C + 85 C, VDD = 1.8 V to 5.5 V)
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
Oscillation frequency (1)
Crystal
–
32
32.768
35
kHz
XT
XT
IN
OUT
Oscillator
C1
C2
(2)
VDD = 4.5 V to 5.5 V
VDD = 1.8 V to 4.5 V
–
–
–
1.0
–
2
s
Stabilization time
10
XTIN input frequency (1)
External
Clock
32
–
100
kHz
XT
XT
OUT
IN
XTIN input high and low
level width (t , t
–
5
–
15
us
)
XTL XTH
NOTES:
1. Oscillation frequency and XT input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
Table 16-6. A.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
A
Parameter
Symbol
Conditions
Min
0.67
1.33
0
Typ
–
Max
Units
tCY
VDD = 2.7 V to 5.5 V
Instruction cycle
64
64
1.5
1
µs
(1)
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 1.8 V to 5.5V
VDD = 2.7 V to 5.5 V
VDD = 1.8 V to 5.5 V
–
time
fTI0, fTI0
TCL0, FCL input
frequency
–
MHz
ns
tTIH0, tTIL0
tFCH, tFCL
tINTH,
TCL0, FCL input
high, low width
Interrupt input
high, low width
150
250
(2)
–
–
INT0
–
–
–
–
µs
µs
tINTL
INT1, INT2 (KS0-KS3)
Input
10
tRSL
RESET Input Low
Width
10
NOTES
1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock (fx) source.
2. Minimum value for INT0 is based on a clock of 2t or 128/fx as assigned by the IMOD0 register setting.
CY
16-6
S3C72H8/P72H8
ELECTRICAL DATA
CPU Clock
Main OSC Frequency
1.5 MHz
1.05 MHz
750 kHz
6 MHz
4.19 MHz
3 MHz
15.625 kHz
1
2
3
4
5
6
7
1.8 V 2.7 V
5.5 V
Supply Voltage (V)
CPU clock = 1/n x oscillator frequency (n = 4, 8, 64)
Figure 16-1. Standard Operating Voltage Range
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Measurement
Points
Figure 16-2. A.C Timing Measure Pints (Except for XIN and XTIN)
16-7
ELECTRICAL DATA
S3C72H8/P72H8
Internal RESET
Operation
Idle Mode
Stop Mode
Operationg Mode
Data Retention Mode
VDD
VDDDR
Execution of
STOP Instrction
RESET
tWAIT
tSREL
Figure 16-3. Stop Mode Release Timing When Initiated By RESET
Idle Mode
Normal
Operating
Mode
Stop Mode
Data Retention Mode
VDD
VDDDR
tSREL
Execution of
STOP Instrction
tWAIT
Power-down Mode Terminating Signal
(Interrupt Request)
Figure 16-4.Stop Release Timing When Initiated By Interrupt Request
1/fx
tXL
tXH
XIN
VDD - 0.5 V
0.4 V
Figure 16-5. Clock Timing Measurement at X
IN
16-8
S3C72H8/P72H8
ELECTRICAL DATA
1/fxt
tXTL
tXTH
XTIN
VDD - 0.5 V
0.4 V
Figure 16-6. Clock Timing Measurement at XTIN
tRSL
RESET
0.2 VDD
Figure 16-7. Input Timing for RESET Signal
tINTL
tINTH
INT0, 1
KS0 to KS3
0.8 VDD
0.2 VDD
Figure 16-8. Input Timing External Interrupt
16-9
S3C72H8/P72H8
MECHANICAL DATA
17 MECHANICAL DATA
OVERVIEW
The S3C72H8/P72H8 microcontroller is available in a 64-pin QFP package (Samsung: 64-QFP-1420F)
Package dimensions are shown in Figure 17-1
23.90 ± 0.3
0-8
+0.10
-0.05
20.00 ± 0.2
0.15
64-QFP-1420F
0.10 MAX
#64
#1
0.40+0.10
-0.05
1.00
(1.00)
0.05-0.25
0.15 MAX
2.65 ± 0.10
3.00 MAX
0.80 ± 0.20
NOTE: Dimensions are in millimeters.
Figure 17-1. 64-QFP-1420F Package Dimensions
17-1
S3C72H8/P72H8
S3P72H8 OTP
18 S3P72H8 OTP
OVERVIEW
The S3P72H8 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C72H8
microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by a serial data
format.
The S3P72H8 is fully compatible with the S3C72H8, both in function and in pin configuration. Because of its
simple programming requirements, the S3P72H8 is ideal for use as an evaluation chip for the S3C72H8.
18-1
S3P72H8 OTP
S3C72H8/P72H8
SEG9
CA
CB
VLC0
VLC1
VLC2
1
2
3
4
5
6
7
8
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
P5.1/C1N
P5.0/C1P
P0.0/ExtRef
SDAT/P0.1
SCLK/P0.2
VDD/VDD
VSS/VSS
XOUT
XIN
VPP/TEST
XTIN
9
S3P72H8
(TOP VIEW)
10
11
12
13
14
15
16
17
18
19
XTOUT
RESET/RESET
P2.0/INT0
P2.1/INT1
P2.2/TCL0
Figure 18-1. S3P72H8 Pin Assignments
18-2
S3C72H8/P72H8
S3P72H8 OTP
Table 18-1. Pin Descriptions Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
P0.1
Pin Name
SDAT
Pin No.
I/O
Function
7
I/O
Serial data pin. Output port when reading and
input port when writing can be assigned as
Input/push-pull output port respectively.
P0.2
SCLK
8
I/O
I
Serial clock pin. Input only pin.
VPP (TEST)
TEST
13
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing
mode). When 12.5 V is applied, OTP is in
writing mode and when 5 V is applied, OTP is in
reading mode. (Option)
RESET
RESET
16
I
I
Chip initialization
VDD / VSS
VDD / VSS
Logic power supply pin. VDD should be tied to
+ 5 V during programming.
9/10
Table 18-2. Comparison of S3P72H8 and S3C72H8 Features
Characteristic
S3P72H8
8 K-byte EPROM
S3C72H8
8 K-byte mask ROM
1.8 V to 5.5 V
Program Memory
Operating Voltage (VDD
)
1.8 V to 5.5 V
VDD = 5 V, VPP (TEST) = 12.5 V
OTP Programming Mode
–
Pin Configuration
64 QFP
64 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (TEST) pin of the S3P72H8, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 18-3 below.
Table 18-3. Operating Mode Selection Criteria
VDD
VPP
(TEST)
REG/
Address
(A15-A0)
Mode
R/W
MEM
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5V
12.5V
12.5V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means low level; "1" means high level.
18-3
S3P72H8 OTP
S3C72H8/P72H8
Table 18-4. D.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
A
Parameter
Symbol
Conditions
Main operation mode:
VDD = 5 V ± 10%, 6-MHz crystal
Min
Typ
Max
Units
IDD1
Supply
Current (note)
–
3.5
8
mA
VDD = 5 V ± 10%, 4.19 MHz
2.5
1.6
1.2
1.8
5.5
4
VDD = 3 V ± 10%, 6-MHz crystal
VDD = 3 V ± 10%, 4.19 MHz
3
IDD2
Main Idle mode:
–
3.5
VDD = 5 V ± 10%, 6-MHz crystal
VDD = 5 V ± 10%, 4.19 MHz
VDD = 3 V ± 10%, 6-MHz crystal
VDD = 3 V ± 10%, 4.19 MHz
1.4
0.6
0.5
15
3.0
1.2
1.1
30
IDD3
IDD4
IDD5
Sub operation mode:
VDD = 3 V, 32768Hz
Main OSC stop, except IVB, IVLD
–
–
–
uA
,
,
Icomp, ILCD and external load.
Sub Idle mode;
VDD = 3.0, 32768Hz
Main OSC stop, except IVB, IVLD
Icomp, ILCD and external load.
6
15
Stop mode; Main & Sub
OSC stop, VDD=5 V ± 10%
SCMOD =
0100B
0.3
0.1
3
1
uA
XTIN = 0V-
except IVD, VLD,
I
Icomp and
external load.
Stop & Sub OSC stop,
VDD = 3 V, except IVD,
IVLD, Lcomp and external
load.
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
I
is LCD controller/driver operating current, I is voltage booster current, Icomp is comparator current, and
LCD
VLD
VB
I
is voltage level detector current.
18-4
S3C72H8/P72H8
S3P72H8 OTP
CPU Clock
Main OSC Frequency
1.5 MHz
1.05 MHz
750 kHz
6 MHz
4.19 MHz
3 MHz
15.625 kHz
1
2
3
4
5
6
7
1.8 V 2.7 V
5.5 V
Supply Voltage (V)
CPU clock = 1/n x oscillator frequency (n = 4, 8, 64)
Figure 18-2. Standard Operating Voltage Range
18-5
S3P72H8 OTP
S3C72H8/P72H8
START
Address= First Location
V
=5V, V =12.5V
PP
DD
x = 0
Program One 1ms Pulse
Increment X
YES
x = 10
NO
FAIL
FAIL
NO
Verify Byte
Verify 1 Byte
Last Address
Increment Address
V
= V = 5 V
PP
DD
FAIL
Compare All Byte
PASS
Device Failed
Device Passed
Figure 18-3. OTP Programming Algorithm
18-6
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