S3C72F5XX-QX [SAMSUNG]
Microcontroller, 4-Bit, MROM, 6MHz, CMOS, PQFP100, 14 X 20 MM, QFP-100;
| 型号： | S3C72F5XX-QX |
| 厂家： | 
SAMSUNG |
| 描述： | Microcontroller, 4-Bit, MROM, 6MHz, CMOS, PQFP100, 14 X 20 MM, QFP-100 时钟 微控制器 外围集成电路 |
| 文件： | 总41页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3C72F5/P72F5
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
OVERVIEW
The S3C72F5 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With an up-to-896-dot LCD direct drive capability, 8-bit and 16-bit timer/counter, and serial I/O, the S3C72F5
offers an excellent design solution for a wide variety of applications which require LCD functions.
Up to 39 pins of the 100-pin QFP package can be dedicated to I/O. Eight vectored interrupts provide fast
response to internal and external events. In addition, the S3C72F5's advanced CMOS technology provides for
low power consumption and a wide operating voltage range.
OTP
The S3C72F5 microcontroller is also available in OTP (One Time Programmable) version, S3P72F5. S3P72F5
microcontroller has an on-chip 16K-byte one-time-programable EPROM instead of masked ROM. The S3P72F5
is comparable to S3C72F5, both in function and in pin configuration.
PRODUCT OVERVIEW
S3C72F5/P72F5
FEATURES SUMMARY
Memory
Watch Timer
•
Time interval generation: 0.5 s, 3.9 ms
at 32768 Hz
•
•
544 ´ 4-bit RAM (excluding LCD display RAM)
16,384 ´ 8-bit ROM
•
•
4 frequency outputs to BUZ pin
Clock source generation for LCD
39 I/O Pins
•
•
I/O: 35 pins
Interrupts
Input only: 4 pins
•
•
•
Four internal vectored interrupts
LCD Controller/Driver
Four external vectored interrupts
Two quasi-interrupts
•
•
•
•
56 segments and 16 common terminals
8 and 16 common selectable
Bit Sequential Carrier
Supports 16-bit serial data transfer in arbitrary
format
Internal resistor circuit for LCD bias
All dot can be switched on/off
•
8-bit Basic Timer
Power-Down Modes
•
•
4 interval timer functions
Watch-dog timer
•
•
•
Idle mode (only CPU clock stops)
Stop mode (main system oscillation stops)
Subsystem clock stop mode
8-bit Timer/Counter
•
•
•
•
•
Programmable 8-bit timer
Oscillation Sources
External event counter
•
•
•
•
•
Crystal, ceramic, or RC for main system clock
Crystal oscillator for subsystem clock
Arbitrary clock frequency output
External clock signal divider
Serial I/O interface clock generator
Main system clock frequency: 0.4 – 6 MHz
Subsystem clock frequency: 32.768 kHz
CPU clock divider circuit (by 4, 8, or 64)
16-Bit Timer/Counter
•
•
•
•
Programmable 16-bit timer
External event counter
Instruction Execution Times
•
•
•
0.67, 1.33, 10.7 µs at 6 MHz
0.95, 1.91, 15.3 µs at 4.19 MHz
122 µs at 32.768 kHz
Arbitrary clock frequency output
External clock signal divider
8-bit Serial I/O Interface
Operating Temperature
•
•
•
•
8-bit transmit/receive mode
° °
– 40 C to 85 C
•
8-bit receive mode
Operating Voltage Range
1.8 V to 5.5 V
LSB-first or MSB-first transmission selectable
Internal or external clock source
•
Package Type
100-pin QFP
Memory-Mapped I/O Structure
•
•
Data memory bank 15
1–2
S3C72F5/P72F5
PRODUCT OVERVIEW
BLOCK DIAGRAM
BASIC
TIMER
WATCH
TIMER
Xin
Xout
RESET
XTin XTout
P1.0-P1.3/
INT0-INT4
INPUT PORT 1
VLC1-VLC5
COM0-COM7
P4.0-P5.3/
P2.0/CLO
P2.1/LCDCK
P2.2/LCDSY
INTERRUPT
CONTROL
BLOCK
INSTRUCTION
REGISTER
LCD
DRIVER/
CONTROLLER
I/O PORT 2
I/O PORT 3
CLOCK
COM8-COM15
P3.0/TCLO0
P3.1/TCLO1
P3.2/TCL0
P3.3/TCL1
SEG0-SEG39
PROGRAM
COUNTER
P9.3-P6.0/
SEG40-SEG55
INTERNAL
INTERRUPTS
SERIAL I/O
P4.0–P4.3/
COM8-COM11
PROGRAM
STATUS
WORD
I/O PORT 4
I/O PORT 5
INSTRUCTION
P5.0–P5.3/
COM12-COM15
P0.0/SCK/K0
P0.1/SO/K1
P0.2/SI/K2
I/O
PORT 0
ARITHMETIC
AND
LOGIC UNIT
P6.0–P6.3/
SEG55-SEG52/
KS4–KS7
STACK
POINTER
P0.3/BUZ/K3
I/O PORT 6
I/O PORT 7
8-BIT
TIMER/
COUNTER
P7.0–P7.3/
SEG51-SEG48
16-BIT
TIMER/
COUNTER
P8.0–P8.3/
SEG47-SEG44
I/O PORT 8
I/O PORT 9
544 x 4-BIT
DATA
MEMORY
16 KBYTE
PROGRAM
MEMORY
P9.0–P9.3/
SEG43-SEG40
Figure 1-1. S3C72F5 Simplified Block Diagram
PRODUCT OVERVIEW
S3C72F5/P72F5
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
SEG4
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
P9.3/SEG40
P9.2/SEG41
P9.1/SEG42
P9.0/SEG43
P8.3/SEG44
P8.2/SEG45
P8.1/SEG46
P8.0/SEG47
P7.3/SEG48
P7.2/SEG49
P7.1/SEG50
P7.0/SEG51
P6.3/SEG52/K7
P6.2/SEG53/K6
P6.1/SEG54/K5
SEG3
SEG2
SEG1
SEG0
VLC5
VLC4
VLC3
VLC2
VLC1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P0.0/
/K0
SCK
P0.1/SO/K1
P0.2/SI/K2
P0.3/BUZ/K3
VDD
S3C72F5
(100-QFP-1420C)
VSS
Xout
Xin
TEST
XTin
XTout
RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P2.0/CLO
P2.1/LCDCK
P2.2/LCDSY
P3.0/TCLO0
Figure 1-2. S3C72F5 100-QFP Pin Assignment Diagram
1–4
S3C72F5/P72F5
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1–1. S3C72F5 Pin Descriptions
Description
Pin Name
P0.0
P0.1
P0.2
P0.3
Pin Type
I/O
Number
Share Pin
4-bit I/O port.
11
12
13
14
SCK/K0
SO/K1
SI/K2
1-bit and 4-bit read/write and test are possible.
Individual pins are software configurable as input or
output.
Individual pins are software configurable as open-
drain or push-pull output.
BUZ/K3
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
P1.0
P1.1
P1.2
P1.3
I
4-bit input port.
1-bit and 4-bit read and test are possible.
4-bit pull-up resistors are assignable by software.
23
24
25
26
INT0
INT1
INT2
INT4
P2.0
P2.1
P2.2
I/O
I/O
Same as port 0 except that port 2 is 3-bit I/O port.
Same as port 0.
27
28
29
CLO
LCDCK
LCDSY
P3.0
P3.1
P3.2
P3.3
30
31
32
33
TCLO0
TCLO1
TCL0
TCL1
P4.0–P4.3
I/O
I/O
4-bit I/O ports.
42–45
COM8–
COM11
COM12–
COM15
1-, 4-bit or 8-bit read/write and test are possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
P5.0–P5.3
46–49
P6.0–P6.3
P7.0–P7.3
Same as P4, P5.
50–53
54–57
SEG55/K4–
SEG52/K7
SEG51–
SEG48
P8.0–P8.3
P9.0–P9.3
I/O
I/O
Same as P4, P5.
58–61
62–65
SEG47–
SEG44
SEG43–
SEG40
Serial I/O interface clock signal.
11
P0.0/K0
SCK
SO
I/O
I/O
I/O
Serial data output.
Serial data input.
12
13
14
P0.1/K1
P0.2/K2
P0.3/K3
SI
BUZ
2 kHz, 4 kHz, 8 kHz or 16 kHz frequency output for
buzzer signal.
INT0, INT1
I
External interrupts. The triggering edge for INT0 and
INT1 is selectable.
23, 24
P1.0, P1.1
PRODUCT OVERVIEW
S3C72F5/P72F5
Table 1–1. S3C72F5 Pin Descriptions (Continued)
Pin Name
Pin Type
Description
Number
Share Pin
INT2
I
Quasi-interrupt with detection of rising or
falling edges.
25
P1.2
INT4
I
External interrupt with detection of rising or
falling edges.
26
P1.3
CLO
I/O
I/O
I/O
Clock output .
27
28
29
P2.0
P2.1
P2.2
LCDCK
LCDSY
LCD clock output for display expansion.
LCD synchronization clock output for display
expansion.
TCLO0
I/O
I/O
I/O
I/O
O
Timer/counter 0 clock output.
30
31
P3.0
P3.1
TCLO1
Timer/counter 1 clock output.
TCL0
External clock input for timer/counter 0.
External clock input for timer/counter 1.
LCD common signal output.
32
P3.2
TCL1
33
P3.3
COM0–COM7
COM8–COM11
COM12–COM15
SEG0–SEG39
34–41
42–45
46–49
–
I/O
P4.0–P4.3
P5.0–P5.3
–
O
LCD segment signal output.
5–1,
100–66
SEG40–SEG43
SEG44–SEG47
SEG48–SEG51
SEG52–SEG55
K0–K3
I/O
65–62
61–58
57–54
53–50
11–14
P9.3–P9.0
P8.3–P8.0
P7.3–P7.0
P6.3/K7–P6.0/K4
P0.0–P0.3
I/O
External interrupt. The triggering edge is
selectable.
K4–K7
50–53
15
P6.0–P6.3
V
–
–
I
Main power supply.
Ground.
–
–
–
DD
SS
V
16
Reset signal.
22
RESET
V
–V
LC1 LC5
–
–
LCD power supply.
10–6
–
–
X
X
Crystal, Ceramic or RC oscillator pins for
system clock.
18, 17
in, out
XT XT
in,
–
I
Crystal oscillator pins for subsystem clock.
20, 21
19
–
–
out
TEST
Test signal input. (must be connected to V )
SS
NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
1–6
S3C72F5/P72F5
PRODUCT OVERVIEW
Table 1–2. Overview of S3C72F5 Pin Data
Pin Names
Share Pins
I/O Type
I/O
Reset Value
Input
Circuit Type
P0.1, P0.3
P0.0, P0.2
SO/K1, BUZ/K3
E-1
E-2
I/O
Input
SCK/K0, SI/K2
P1.0–P1.3
P2.0–P2.2
P3.0–P3.1
P3.2–P3.3
INT0–INT2, INT4
CLO, LCDCK, LCDSY
TCLO0, TCLO1
TCL0, TCL1
I
Input
Input
Input
Input
Input
A-3
E
I/O
I/O
I/O
I/O
E
E-1
H-13
P4.0–P4.3
P5.0–P5.3
COM8–COM11
COM12–COM15
I/O
H-16
P6.0–P6.3
P7.0–P7.3
SEG55/K4–SEG52/K7
SEG51–SEG48
Input
Input
Input
I/O
I/O
H-13
H-13
P8.0–P8.3
P9.0–P9.3
SEG47–SEG44
SEG43–SEG40
COM0–COM7
SEG0–SEG39
–
–
–
–
–
O
O
–
–
I
High
High
–
H-3
H-15
–
V
DD
SS
V
–
–
–
B
RESET
V
–V
LC1 LC5
–
–
–
–
–
–
–
I
–
–
–
–
–
–
–
–
X
X
in, out
XT XT
in,
out
TEST
PRODUCT OVERVIEW
S3C72F5/P72F5
PIN CIRCUIT DIAGRAMS
V
DD
V
DD
PULL-UP
RESISTOR
-
P CHANNEL
IN
IN
N-CHANNEL
SCHMITT TRIGGER
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type B
V
DD
V
DD
PULL-UP
RESISTOR
P-CHANNEL
OUT
PULL-UP
RESISTOR
ENABLE
DATA
P-CHANNEL
N-CHANNEL
IN
OUTPUT
DISABLE
SCHMITT TRIGGER
Figure 1-4. Pin Circuit Type A-3
Figure 1-6. Pin Circuit Type C
1–8
S3C72F5/P72F5
PRODUCT OVERVIEW
VDD
VDD
PULL-UP
RESISTOR
PNE
RESISTOR
ENABLE
P-CH
I/O
DATA
N-CH
OUTPUT
DISABLE
CIRCUIT TYPE A
Figure 1-7. Pin Circuit Type E
VDD
VDD
PULL-UP
RESISTOR
PNE
RESISTOR
ENABLE
P-CH
N-CH
I/O
DATA
OUTPUT
DISABLE
SCHMITT TRIGGER
Figure 1-8. Pin Circuit Type E-1
PRODUCT OVERVIEW
S3C72F5/P72F5
VDD
VDD
PULL-UP
RESISTOR
PNE
RESISTOR
ENABLE
P-CH
I/O
DATA
N-CH
OUTPUT
DISABLE
SCHMITT TRIGGER
Figure 1-9. Pin Circuit Type E-2
1–10
S3C72F5/P72F5
PRODUCT OVERVIEW
V
V
DD
LC1
OUT
COM DATA
V
V
LC4
LC5
Figure 1-10. Pin Circuit Type H-3
V
V
DD
LC2
OUT
SEG DATA
V
V
LC3
LC5
Figure 1-11. Pin Circuit Type H-15
PRODUCT OVERVIEW
S3C72F5/P72F5
V
DD
PULL-UP
RESISTOR
P-CH
RESISTOR
ENABLE
COM/SEG
TYPE H-3
OUTPUT
DISABLE
DATA
I/O
TYPE C
CIRCUIT TYPE A
Figure 1-12. Pin Circuit Type H-13
V
DD
PULL-UP
RESISTOR
P-CH
RESISTOR
ENABLE
SEG
TYPE H-15
OUTPUT
DISABLE
DATA
TYPE C
I/O
SCHMITT TRIGGER
Figure 1-13. Pin Circuit Type H-16
1–12
S3C72F5/P72F5
ELECTRICAL DATA
14 ELECTRICAL DATA
OVERVIEW
In this section, information on S3C72F5 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at X
in
— Clock timing measurement at XT
— TCL timing
in
— Input timing for RESET
— Input timing for external interrupts
— Serial data transfer timing
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
14–1
ELECTRICAL DATA
S3C72F5/P72F5
Table 14–1. Absolute Maximum Ratings
°
(T = 25 C)
A
Parameter
Symbol
Conditions
Rating
Units
V
V
DD
Supply Voltage
Input Voltage
–
– 0.3 to + 6.5
V
I
– 0.3 to V
+ 0.3
Ports 0–9
V
DD
DD
V
O
– 0.3 to V
+ 0.3
Output Voltage
Output Current High
–
V
I
One I/O pin active
All I/O pins active
One I/O pin active
– 15
– 35
mA
OH
I
Output Current Low
+ 30 (Peak value)
mA
OL
+ 15 (note)
+ 100 (Peak value)
+ 60 (note)
Total for ports 0, 2–9
T
A
°
Operating Temperature
Storage Temperature
–
–
– 40 to + 85
– 65 to + 150
C
T
°
C
stg
NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value ´
Duty .
Table 14–2. D.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
DD
A
Parameter
Symbol
Conditions
Min
Typ
Max
Units
V
IH1
0.7V
V
DD
Input High
Voltage
All input pins except those
specified below for V –V
–
V
DD
IH2 IH3
V
IH2
0.8V
V
DD
Ports 0, 1, 6, P3.2, P3.3, and
DD
RESET
V
IH3
X , X , and XT
in out in
V
DD
– 0.1
V
DD
V
0.3V
Input Low
Voltage
All input pins except those
specified below for V –V
–
–
V
IL1
IL2
IL3
DD
IL2 IL3
V
0.2V
Ports 0, 1, 6, P3.2, P3.3, and
DD
RESET
V
V
X , X , and XT
0.1
–
in
out
in
V
I
= 4.5 V to 5.5 V
= – 1 mA
V
– 1.0
DD
Output High
Voltage
–
–
V
V
OH
DD
OH
Ports 0, 2–9
V = 4.5 V to 5.5 V
V
Output Low
Voltage
–
2.0
OL
DD
= 15 mA
I
OL
Ports 0, 2–9
14–2
S3C72F5/P72F5
ELECTRICAL DATA
Table 14–2. D.C. Electrical Characteristics (Continued)
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
DD
A
Parameter
Symbol
Conditions
Min
Typ
Max
Units
I
V = V
I
Input High
Leakage
Current
–
–
3
µA
LIH1
DD
All input pins except those
specified below for I
LIH2
I
V = V
I
20
LIH2
DD
X
X
XT and RESET
in,
in, out,
I
V = 0 V
Input Low
Leakage
–
–
– 3
– 20
3
µA
LIL1
I
X
X
and XT
in
in, out,
Current
I
V = 0 V
LIL2
I
X , X
in out,
and XT
in
I
V = V
DD
Output High
Leakage
Current
–
–
–
–
µA
µA
kW
LOH
O
All output pins
I
V = 0 V
O
All output pins
Output Low
Leakage
Current
– 3
LOL
R
LI
V = 0 V; V
I
Port 0–9
= 5 V
Pull-Up
Resistor
25
47
100
DD
DD
V
DD
= 3 V
50
95
200
400
R
100
220
L2
V = 0 V; V
I
= 5 V, RESET
V
= 3 V
200
25
450
55
800
80
DD
R
LCD
LCD Voltage
Dividing
Ta = 25 °C
kW
Resistor
V
V
– 15 µA per common pin
– 15 µA per segment pin
–
–
–
–
120
120
mV
| DD-COMi|
DC
Voltage Drop
(i = 0–15)
V
V
| DD-SEGx|
DS
Voltage Drop
(x = 0–55)
V
V
LCD clock = 0 Hz, V
LC5
= 0 V
0.8V -0.2 0.8V
DD
0.8V +0.2
DD
V
LC1 Output
LC1
DD
DD
DD
DD
Voltage
V
V
LC2
V
LC3
V
LC4
0.6V -0.2 0.6V
DD
0.6V +0.2
DD
LC2 Output
Voltage
V
0.4V -0.2 0.4V
DD
0.4V +0.2
DD
LC3 Output
Voltage
V
0.2V -0.2 0.2V
DD
0.2V +0.2
DD
LC4 Output
Voltage
14–3
ELECTRICAL DATA
S3C72F5/P72F5
Table 14–2. D.C. Electrical Characteristics (Concluded)
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
DD
A
Parameter
Symbol
Conditions
Min
Typ
Max
Units
V
= 5 V ± 10%
(2)
Supply
Current
6.0 MHz
4.19 MHz
–
3.9
2.9
8.0
5.5
mA
DD
I
DD1
Crystal oscillator
C1 = C2 = 22 pF
V
DD
= 3 V ± 10%
6.0 MHz
4.19 MHz
1.8
1.3
4.0
3.0
(2)
Idle mode;
= 5 V ± 10%
6.0 MHz
4.19 MHz
1.3
1.2
2.5
1.8
I
DD2
V
DD
Crystal oscillator
C1 = C2 = 22 pF
V
DD
= 3 V ± 10%
6.0 MHz
4.19 MHz
0.5
0.44
1.5
1.0
V
= 3 V ± 10%
(3)
(3)
–
15.3
6.4
2.5
0.5
0.2
0.1
30
15
5
µA
DD
I
I
DD3
32 kHz crystal oscillator
Idle mode; V = 3 V ± 10%
DD
DD4
I
32 kHz crystal oscillator
Stop mode;
SCMOD =
0000B
DD5
V
= 5 V ± 10%
DD
Stop mode;
= 3 V ± 10%
XT = 0V
3
V
DD
Stop mode;
= 5 V ± 10%
SCMOD =
0100B
3
V
DD
Stop mode;
= 3 V ± 10%
2
V
DD
NOTES:
1. Data includes power consumption for subsystem clock oscillation.
2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
3. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
output port drive currents.
14–4
S3C72F5/P72F5
ELECTRICAL DATA
Table 14–3. Main System Clock Oscillator Characteristics
°
°
(T = – 40 C + 85 C, V
= 1.8 V to 5.5 V)
DD
A
Oscillator
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max Units
(1)
Ceramic
Oscillator
–
0.4
–
6.0
MHz
Oscillation frequency
Xin Xout
C1
C2
(2)
Stabilization occurs
–
–
–
4
ms
Stabilization time
when V
is equal
DD
to the minimum
oscillator voltage
range; V
= 3.0 V.
DD
(1)
Crystal
Oscillator
–
0.4
6.0
MHz
Oscillation frequency
Xin
Xout
C1
C2
(2)
V
V
= 3.0 V
–
–
–
–
–
10
30
ms
DD
Stabilization time
= 2.0 V to 5.5 V
–
DD
(1)
External
Clock
0.4
6.0
MHz
Xin
Xout
X input frequency
in
X input high and low
in
–
83.3
–
–
2
1250
–
ns
level width (t , t
)
XH XL
RC
Frequency
MHz
Xin
Xout
R = 20 kW,
= 5 V
V
Oscillator
DD
R
–
1
–
R = 39 kW,
= 3 V
V
DD
NOTES:
1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
14–5
ELECTRICAL DATA
S3C72F5/P72F5
Table 14–4. Recommended Oscillator Constants
°
°
(T = – 40 C + 85 C, V
= 1.8 V to 5.5 V)
DD
A
Manufacturer
Series
Number (1)
Frequency Range
Load Cap (pF)
Oscillator Voltage
Range (V)
Remarks
C1
33
(2)
C2
33
(2)
MIN
2.0
MAX
5.5
TDK
3.58 MHz–6.0 MHz
3.58 MHz–6.0 MHz
Leaded Type
FCR” ðÿM5
2.0
5.5
On-chip C
FCR” ðÿMC5
Leaded Type
(3)
(3)
3.58 MHz–6.0 MHz
2.0
5.5
On-chip C
SMD Type
CCR” ðÿMC3
NOTES:
1. Please specify normal oscillator frequency.
2. On-chip C: 30pF built in.
3. On-chip C: 38pF built in.
14–6
S3C72F5/P72F5
ELECTRICAL DATA
Table 14–5. Subsystem Clock Oscillator Characteristics
°
°
(T = – 40 C + 85 C, V
= 1.8 V to 5.5 V)
DD
A
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max
Units
Configuration
Crystal
Oscillator
Oscillation
frequency (1)
–
32
32.768
35
kHz
XTin XTout
C1
C2
Stabilization time (2)
VDD = 2.7 V to 5.5 V
VDD = 2.0 V to 5.5 V
–
–
–
1.0
–
2
s
10
XT input
in
frequency (1)
External
Clock
32
–
100
kHz
XTin XTout
XT input high and
in
–
5
–
15
µs
low level width (t
,
XTL
t
)
XTH
NOTES:
1. Oscillation frequency and XT input frequency data are for oscillator characteristics only.
in
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
Table 14–6. Input/Output Capacitance
°
(T = 25 C, V = 0 V )
A
DD
Parameter
Symbol
Condition
Min
Typ
Max
Units
C
Input
Capacitance
f = 1 MHz; Unmeasured pins
–
–
15
15
15
pF
pF
pF
IN
are returned to V
SS
C
OUT
Output
Capacitance
–
–
–
–
C
IO
I/O Capacitance
14–7
ELECTRICAL DATA
S3C72F5/P72F5
Table 14–7. A.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
A
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Units
t
V
= 2.7 V to 5.5 V
Instruction Cycle
Time
0.67
–
64
µs
CY
, f
DD
(note)
V
V
= 2.0 V to 5.5 V
= 2.7 V to 5.5 V
0.95
0
64
DD
f
TCL0, TCL1 Input
Frequency
–
–
1.5
MHz
µs
TI0 TI1
DD
V
V
= 2.0 V to 5.5 V
= 2.7 V to 5.5 V
1
–
DD
t
t
, t
TIH0 TIL0
TCL0, TCL1 Input
High, Low Width
0.48
DD
, t
TIH1 TIL1
V
V
= 2.0 V to 5.5 V
1.8
800
DD
t
= 2.7 V to 5.5 V; Input
–
–
–
–
ns
ns
KCY
DD
SCK Cycle Time
650
Internal SCK source; Output
= 2.0 V to 5.5 V; Input
V
3200
3800
325
DD
Internal SCK source; Output
= 2.7 V to 5.5 V; Input
t
, t
V
DD
KH KL
SCK High, Low
Width
t
/2 –
KCY
Internal SCK source; Output
50
V
DD
= 2.0 V to 5.5 V; Input
1600
t
KCY/2 –
150
Internal SCK source; Output
t
V
= 2.7 V to 5.5 V; Input
SI Setup Time to
100
–
–
–
–
ns
ns
SIK
DD
SCK High
V
DD
V
DD
V
DD
V
DD
= 2.7 V to 5.5 V; Output
= 2.0 V to 5.5 V; Input
= 2.0 V to 5.5 V; Output
= 2.7 V to 5.5 V; Input
150
150
500
400
t
SI Hold Time to
KSI
SCK High
V
DD
V
DD
V
DD
= 2.7 V to 5.5 V; Output
= 2.0 V to 5.5 V; Input
= 2.0 V to 5.5 V; Output
400
600
500
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.
14–8
S3C72F5/P72F5
ELECTRICAL DATA
Table 14–7. A.C. Electrical Characteristics (Continued)
_
_
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
A
DD
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
V
DD
= 2.7 V to 5.5 V; Input
Output Delay for
–
–
300
ns
KSO
SCK to SO
V
V
V
= 2.7 V to 5.5 V; Output
= 2.0 V to 5.5 V; Input
= 2.0 V to 5.5 V; Output
250
1000
1000
–
DD
DD
DD
t
t
,
Interrupt Input
High, Low Width
INT0, INT1, INT2, INT4,
K0–K7
10
10
–
–
µs
µs
INTH
INTL
t
Input
–
RSL
RESET Input Low
Width
NOTE: Minimum value for INT0 is based on a clock of 2tCY or 128 / fx as assigned by the IMOD0 register setting.
Main Oscillator Frequency
CPU CLOCK
1.5 MHz
(Divided by 4)
6 MHz
4.2 MHz
3 MHz
1.05 MHz
750 kHz
15.6 kHz
1
2
3
4
5
6
7
1.8 V
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 14–1. Standard Operating Voltage Range
14–9
ELECTRICAL DATA
S3C72F5/P72F5
Table 14–8. RAM Data Retention Supply Voltage in Stop Mode
°
°
(T = – 40 C to + 85 C)
A
Parameter
Symbol
Conditions
–
Min
1.8
–
Typ
–
Max
Unit
V
V
DDDR
Data retention supply voltage
Data retention supply current
5.5
10
I
V
= 1.8 V
0.1
µA
DDDR
DDDR
t
Release signal set time
–
0
–
–
–
–
µs
SREL
217 / fx
t
Oscillator stabilization wait
ms
WAIT
Released by RESET
(1)
time
(2)
Released by interrupt
–
–
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
14–10
S3C72F5/P72F5
ELECTRICAL DATA
TIMING WAVEFORMS
INTERNAL
RESET
OPERATION
IDLE MODE
NORMAL MODE
STOP MODE
DATA RETENTION MODE
V
DD
V
DDDR
EXECUTION OF
STOP INSTRUCTION
RESET
t
WAIT
t
SREL
Figure 14–2. Stop Mode Release Timing When Initiated by RESET
IDLE MODE
NORMAL MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
tSREL
EXECUTION OF
STOP INSTRUCTION
tWAIT
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
Figure 14–3. Stop Mode Release Timing When Initiated by Interrupt Request
14–11
ELECTRICAL DATA
S3C72F5/P72F5
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
MEASUREMENT
POINTS
Figure 14–4. A.C. Timing Measurement Points (Except for X and XT )
in
in
1 / fx
t
t
XH
XL
X
in
V
-0.1 V
DD
0.1 V
Figure 14–5. Clock Timing Measurement at X
in
1 / fxt
t
t
XTH
XTL
XT
in
V
- 0.1 V
DD
0.1 V
Figure 14–6. Clock Timing Measurement at XT
in
14–12
S3C72F5/P72F5
ELECTRICAL DATA
1 / f
TI
t
t
TIH
TIL
0.8 V
DD
TCL0
0.2 V
DD
Figure 14–7. TCL Timing
t
RSL
RESET
0.2 V
DD
Figure 14–8. Input Timing for RESET Signal
t
t
INTL
INTH
0.8V
0.2V
DD
INT0, 1, 2, 4 K0 to K7
DD
Figure 14–9. Input Timing for External Interrupts and Quasi-Interrupts
14–13
ELECTRICAL DATA
S3C72F5/P72F5
t
KCY
t
t
KH
KL
0.8 V
DD
0.2 V
DD
SCK
t
t
KSI
SIK
0.8 V
DD
INPUT DATA
SI
0.2 V
DD
t
KSO
SO
OUTPUT DATA
Figure 14–10. Serial Data Transfer Timing
14–14
S3C72F5/P72F5
ELECTRICAL DATA
NOTES
14–15
ELECTRICAL DATA
S3C72F5/P72F5
CHARACTERISTIC CURVES
NOTE
The characteristic values shown in the following graphs are based on actual test measurements.
They do not, however, represent guaranteed operating values.
(T = 25 °C, fx = 4.2 MHz)
A
5.0
4.5
I
, CPU Clock = fx/4
DD1
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
I
, CPU Clock = fx/64
DD1
I
DD2
0
2.7
4.0
4.5
6.0
V
(V)
DD
, I
Figure 14–11. I
VS. V
DD
DD1 DD2
14–16
S3C72F5/P72F5
ELECTRICAL DATA
(T = 25 °C, fx = 32.768 kHz)
A
50
45
40
35
30
25
20
15
10
5
I
DD3
I
DD4
DD5
I
0
2.0
2.5
3.0
3.5
4.0
V
4.5
5.0
5.5
6.0
6.5
(V)
DD
Figure 14–12. I
, I
, I
VS. V
DD3 DD4 DD5
DD
14–17
ELECTRICAL DATA
S3C72F5/P72F5
(T = 25 °C, CPU CLOCK = fx/4)
A
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
V
= 6.0 V
DD
= 4.5 V
DD
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Main System Clock Frequency (MHz)
Figure 14–13. I
VS. Main System Clock Frequency
DD1
(T = 25 °C)
A
1.6
V
= 6.0 V
= 4.5 V
DD
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
DD
0.5
1.0
Main System Clock Frequency (MHz)
Figure 14–14. I VS. Main System Clock Frequency
1.5
2.0
2.5
3.0
3.5
4.0
4.5
DD2
14–18
S3C72F5/P72F5
ELECTRICAL DATA
(T = 25 °C, Ports 0, 2, 3, 4, 5, 6, 7)
A
–25.0
–22.5
–20.0
–17.5
–15.0
–12.5
–10.0
–7.5
–5.0
–2.5
V
= 4.5 V
4.0
V
= 6.0 V
DD
DD
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.5
5.0
5.5
6.0
V
(V)
OH
Figure 14–15. I
OH
VS. V
(P0, 2, 3, 4, 5, 6, 7)
OH
14–19
ELECTRICAL DATA
S3C72F5/P72F5
(T = 25 °C, Ports 8, 9)
A
–25.0
–22.5
–20.0
–17.5
–15.0
–12.5
–10.0
–7.5
–5.0
–2.5
V
= 4.5 V
4.0
V
= 6.0 V
DD
DD
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.5
5.0
5.5
6.0
V
(V)
OH
Figure 14–16. I
OH
VS. V (P8, 9)
OH
14–20
S3C72F5/P72F5
ELECTRICAL DATA
(T = 25 °C, Ports 0, 2, 3, 4, 5, 6, 7)
A
55.0
50.0
45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
5.0
V
= 6.0 V
DD
V
= 4.5 V
DD
0
0.5
1.0
1.5
2.0
2.5
3.0
OL
3.5
4.0
4.5
5.0
5.5
6.0
V
(V)
Figure 14–17. I
OL
VS. V
(P0, 2, 3, 4, 5, 6, 7)
OL
14–21
ELECTRICAL DATA
S3C72F5/P72F5
(T = 25 °C, Ports 8, 9)
A
55.0
50.0
45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
5.0
V
= 6.0 V
DD
V
= 4.5 V
DD
0
0.5
1.0
1.5
2.0
2.5
3.0
OL
3.5
4.0
4.5
5.0
5.5
6.0
V
(V)
Figure 14–18. I
OL
VS. V
OL
(P8, 9)
14–22
S3C72F5/P72F5
MECHANICAL DATA
15 MECHANICAL DATA
OVERVIEW
This section contains the following information about the device package:
—
—
—
Package dimensions in millimetersD
Pad diagram
Pad/pin coordinate data table
15–1
MECHANICAL DATA
S3C72F5/P72F5
20.00 TYP
C
D
100 QFP
(Top View)
B
+ 0.1
– 0.05
0.65 TYP
0.30 ± 0.1
0.15
A
E
Item
A
B
C
D
E
Package
+ 0.1
– 0.05
100-QFP-1420A 25.00 ± 0.3 19.00 ± 0.3 2.45 MAX
100-QFP-1420C 23.20 ± 0.3 17.20 ± 0.3 3.00 MAX
0.15
1.20 ± 0.2
0.80 ± 0.2
0.15 ± 0.1
NOTE
: Typical dimensions are in millimeters.
Figure 15–1. 100-QFP Package Dimensions
15-2
S3C72F5/P72F5
S3P72F5 OTP
16 S3P72F5 OTP
OVERVIEW
The S3P72F5 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C72F5
microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data
format.
The S3P72F5 is fully compatible with the S3C72F5, both in function and in pin configuration. Because of its
simple programming requirements, the S3P72F5 is ideal for use as an evaluation chip for the S3C72F5.
16–1
S3P72F5 OTP
S3C72F5/P72F5
1
2
3
4
5
6
7
8
SEG4
SEG3
SEG2
SEG1
SEG0
VLC5
VLC4
VLC3
VLC2
VLC1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
P9.3/SEG40
P9.2/SEG41
P9.1/SEG42
P9.0/SEG43
P8.3/SEG44
P8.2/SEG45
P8.1/SEG46
P8.0/SEG47
P7.3/SEG48
P7.2/SEG49
P7.1/SEG50
P7.0/SEG51
P6.3/SEG52/K7
P6.2/SEG53/K6
P6.1/SEG54/K5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P0.0/
/K0
SCK
P0.1/SO/K1
/P0.2/SI/K2
/P0.3/BUZ/K3
SDAT
SCLK
S3P72F5
(100-QFP-1420C)
/VDD
VDD
/VSS
Xout
Xin
VSS
/TEST
XTin
XTout
VPP
RESET /RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P2.0/CLO
P2.1/LCDCK
P2.2/LCDSY
P3.0/TCLO0
The bolds indicate an OTP pin name.
NOTE:
Figure 16–1. S3P72F5 Pin Assignments (100-QFP Package)
16–2
S3C72F5/P72F5
S3P72F5 OTP
Table 16–1. Descriptions of Pins Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
P0.2
Pin Name
Pin No.
I/O
Function
SDAT
13
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input / push-pull output port.
P0.3
SCLK
14
19
I/O
I
Serial clock pin. Input only pin.
V
(TEST)
TEST
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing
mode). When 12.5 V is applied, OTP is in
writing mode and when 5 V is applied, OTP is in
reading mode. (Option)
PP
22
I
I
Chip initialization
RESET
RESET
V
/ V
V
/ V
SS
15/16
Logic power supply pin. VDD should be tied to
+5 V during programming.
DD
SS
DD
Table 16–2. Comparison of S3P72F5 and S3C72F5 Features
S3P72F5
Characteristic
S3C72F5
Program Memory
16 Kbyte EPROM
1.8 V to 5.5 V
16 Kbyte mask ROM
1.8 V to 5.5 V
Operating Voltage (V
)
DD
V
= 5 V, V (TEST)=12.5V
PP
OTP Programming Mode
DD
100 QFP
User Program 1 time
Pin Configuration
100 QFP
EPROM Programmability
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the V (TEST) pin of the S3P72F5, the EPROM programming mode is entered. The
PP
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 16–3 below.
Table 16–3. Operating Mode Selection Criteria
V
DD
Vpp
(TEST)
REG/MEM
Address
(A15-A0)
R/W
Mode
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
16–3
S3P72F5 OTP
S3C72F5/P72F5
Table 16–4. D.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
A
DD
Parameter
Symbol
Conditions
= 5 V ± 10%
Min
Typ
Max
Units
(2)
V
DD
Supply
Current
6.0 MHz
–
3.9
2.9
8.0
5.5
mA
I
DD1
4.19 MHz
Crystal oscillator
C1 = C2 = 22 pF
V
DD
= 3 V ± 10%
6.0 MHz
4.19 MHz
1.8
1.3
4.0
3.0
(2)
Idle mode;
= 5 V ± 10%
6.0 MHz
4.19 MHz
1.3
1.2
2.5
1.8
I
DD2
V
DD
Crystal oscillator
C1 = C2 = 22 pF
V
DD
= 3 V ± 10%
6.0 MHz
4.19 MHz
0.5
0.44
1.5
1.0
(3)
(3)
V
= 3 V ± 10%
–
15.3
6.4
2.5
0.5
0.2
0.1
30
15
5
µA
DD
I
I
DD3
32 kHz crystal oscillator
Idle mode; V = 3 V ± 10%
DD
DD4
I
32 kHz crystal oscillator
Stop mode;
= 5 V ± 10%
SCMOD =
0000B
DD5
V
DD
Stop mode;
= 3 V ± 10%
XT = 0V
3
V
DD
Stop mode;
= 5 V ± 10%
SCMOD =
0100B
3
V
DD
Stop mode;
= 3 V ± 10%
2
V
DD
NOTES:
1. Data includes power consumption for subsystem clock oscillation.
2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
3. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
output port drive currents.
16–4
S3C72F5/P72F5
S3P72F5 OTP
Main Oscillator Frequency
CPU CLOCK
1.5 MHz
(Divided by 4)
6 MHz
1.05 MHz
750 kHz
4.2 MHz
3 MHz
15.6 kHz
1
2
3
4
5
6
7
1.8 V
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 16–2. Standard Operating Voltage Range
16–5
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