S3C72G9_技术文档

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ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀ

ꢀꢁꢂꢃꢁꢄꢂꢅꢆ

ꢀ ꢁꢂꢃꢄꢅꢀꢆꢇꢁꢈꢉꢊꢋꢈꢆꢌꢇꢀꢁꢍꢈꢀ

The SAM47 instruction set is specifically designed to support the large register files typically founded in most

KS57-series microcontrollers. The SAM47 instruction set includes 1-bit, 4-bit, and 8-bit instructions for data

manipulation, logical and arithmetic operations, program control, and CPU control. I/O instructions for peripheral

hardware devices are flexible and easy to use. Symbolic hardware names can be substituted as the instruction

operand in place of the actual address. Other important features of the SAM47 instruction set include:

— 1-byte referencing of long instructions (REF instruction)

— Redundant instruction reduction (string effect)

— Skip feature for ADC and SBC instructions

Instruction operands conform to the operand format defined for each instruction. Several instructions have multiple

operand formats.

Predefined values or labels can be used as instruction operands when addressing immediate data. Many of the

symbols for specific registers and flags may also be substituted as labels for operations such DA, mema, memb,

b, and so on. Using instruction labels can greatly simplify programming and debugging tasks.

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In this section, the following SAM47 instruction set features are described in detail:

— Instruction reference area

— Instruction redundancy reduction

— Flexible bit manipulation

— ADC and SBC instruction skip condition

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ꢜꢝꢅꢞꢓꢕꢎꢔꢍꢒꢅꢘꢌꢖꢊ ꢐꢁꢅ

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ꢔꢕꢖꢉ

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ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

INSTRUCTION REFERENCE AREA

Using the 1-byte REF (Reference) instruction, you can reference instructions stored in addresses 0020H-007FH of

program memory (the REF instruction look-up table). The location referenced by REF may contain either two 1-

byte instructions or a single 2-byte instruction. The starting address of the instruction being referenced must

always be an even number.

3-byte instructions such as JP or CALL may also be referenced using REF. To reference these 3-byte instructions,

the 2-byte pseudo commands TJP and TCALL must be written in the reference instead of JP and CALL.

The PC is not incremented when a REF instruction is executed. After it executes, the program's instruction

execution sequence resumes at the address immediately following the REF instruction. By using REF instructions

to execute instructions larger than one byte, as well as branches and subroutines, you can reduce program size.

To summarize, the REF instruction can be used in three ways:

— Using the 1-byte REF instruction to execute one 2-byte or two 1-byte instructions;

— Branching to any location by referencing a branch address that is stored in the look-up table;

— Calling subroutines at any location by referencing a call address that is stored in the look-up table.

If necessary, a REF instruction can be circumvented by means of a skip operation prior to the REF in the

execution sequence. In addition, the instruction immediately following a REF can also be skipped by using an

appropriate reference instruction or instructions.

Two-byte instruction can be referenced by using a REF instruction (An exception is XCH A, DA). If the MSB value

of the first one-byte instruction in the reference area is “0”, the instruction cannot be referenced by a REF

instruction. Therefore, if you use REF to reference two 1-byte instruction stored in the reference area, specific

combinations must be used for the first and second 1-byte instruction.

These combination examples are described in Table 5-1.

Table 5-1. Valid 1-Byte Instruction Combinations for REF Look-Ups

First 1-Byte Instruction

Instruction Operand

Second 1-Byte Instruction

Instruction

ꢀꢁꢂꢃꢄꢅ

Operand

LD

A, #im

R

INCS

DECS

INCS

DECS

INCS

DECS

RRb

R

ꢀꢁꢂꢃꢄꢅ

A, @RRa

@HL, A

R

RRb

R

ꢀꢁꢂꢃꢄꢅ

R

RRb

R

ꢀꢁꢂꢃꢄꢅ

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ꢔꢕꢄꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

REDUCING INSTRUCTION REDUNDANCY

When redundant instructions such as LD A,#im and LD EA,#imm are used consecutively in a program sequence,

only the first instruction is executed. The redundant instructions which follow are ignored, that is, they are handled

like a NOP instruction. When LD HL,#imm instructions are used consecutively, redundant instructions are also

ignored.

In the following example, only the 'LD A, #im' instruction will be executed. The 8-bit load instruction which follows it

is interpreted as redundant and is ignored:

LD

A,#im

; Load 4-bit immediate data (#im) to accumulator

; Load 8-bit immediate data (#imm) to extended

; accumulator

EA,#imm

In this example, the statements 'LD A,#2H' and 'LD A,#3H' are ignored:

BITR

LD

EMB

A,#1H

A,#2H

A,#3H

23H,A

; Execute instruction

LD

; Ignore, redundant instruction

; Execute instruction, 023H ← #1H

LD

If consecutive LD HL, #imm instructions (load 8-bit immediate data to the 8-bit memory pointer pair, HL) are

detected, only the first LD is executed and the LDs which immediately follow are ignored. For example,

LD

HL,#10H

HL,#20H

A,#3H

; HL ← 10H

; Ignore, redundant instruction

; A ← 3H

EA,#35H

@HL,A

; Ignore, redundant instruction

; (10H) ← 3H

If an instruction reference with a REF instruction has a redundancy effect, the following conditions apply:

— If the instruction preceding the REF has a redundancy effect, this effect is cancelled and the referenced

instruction is not skipped.

— If the instruction following the REF has a redundancy effect, the instruction following the REF is skipped.

ꢀꢀ^{PROGRAMMING TIP — Example of the Instruction Redundancy Effect}

ORG

0020H

ABC

LD

EA,#30H

0080H

; Stored in REF instruction reference area

ORG

ꢆ

LD

EA,#40H

ABC

; Redundancy effect is encountered

REF

; No skip (EA ← #30H)

ꢆ

REF

LD

ABC

; EA ← #30H

EA,#50H

; Skip

ꢉ

ꢔꢕꢁꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

FLEXIBLE BIT MANIPULATION

In addition to normal bit manipulation instructions like set and clear, the SAM47 instruction set can also perform bit

tests, bit transfers, and bit Boolean operations. Bits can also be addressed and manipulated by special bit

addressing modes. Three types of bit addressing are supported:

— mema.b

— memb.@L

— @H+DA.b

The parameters of these bit addressing modes are described in more detail in Table 5-2.

Table 5-2. Bit Addressing Modes and Parameters

Addressing Mode

mema.b

Addressable Peripherals

ERB, EMB, IS1, IS0, IEx, IRQx

Ports

BSCx, Ports

All bit-manipulatable peripheral hardware

Address Range

FB0H-FBFH

FF0H-FFFH

FC0H-FFFH

memb.@L

@H+DA.b

All bits of the memory bank specified by

EMB and SMB that are bit-manipulatable

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ꢄꢇꢈꢉꢃꢊꢋꢉꢄꢀꢇꢈꢆꢅꢎꢄꢋꢎꢆꢎꢍꢁꢂꢆꢈꢏꢄꢐꢆꢋꢀꢇꢑꢄꢉꢄꢀꢇꢈꢆ

The following instructions have a skip function when an overflow or borrow occurs:

XCHI

XCHD

LDI

INCS

DECS

ADS

LDD

SBS

If there is an overflow or borrow from the result of an increment or decrement, a skip signal is generated and a

skip is executed. However, the carry flag value is unaffected.

The instructions BTST, BTSF, and CPSE also generate a skip signal and execute a skip when they meet a skip

condition, and the carry flag value is also unaffected.

ꢔꢕꢌꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

INSTRUCTIONS WHICH AFFECT THE CARRY FLAG

The only instructions which do not generate a skip signal, but which do affect the carry flag are as follows:

ADC

SBC

SCF

RCF

CCF

RRC

LDB

BAND

BOR

BXOR

IRET

C,(operand)

ADC AND SBC INSTRUCTION SKIP CONDITIONS

The instructions 'ADC A,@HL' and 'SBC A,@HL' can generate a skip signal, and set or clear the carry flag, when

they are executed in combination with the instruction 'ADS A,#im'.

If an 'ADS A,#im' instruction immediately follows an 'ADC A,@HL' or 'SBC A,@HL' instruction in a program

sequence, the ADS instruction does not skip the instruction following ADS, even if it has a skip function. If,

however, an 'ADC A,@HL' or 'SBC A,@HL' instruction is immediately followed by an 'ADS A,#im' instruction, the

ADC (or SBC) skips on overflow (or if there is no borrow) to the instruction immediately following the ADS, and

program execution continues. Table 5-3 contains additional information and examples of the 'ADC A,@HL' and

'SBC A,@HL' skip feature.

Table 5-3. Skip Conditions for ADC and SBC Instructions

Sample

If the result of

Then, the execution

sequence is:

Reason

Instruction Sequences

instruction 1 is:

ADC A,@HL

ADS A,#im

xxx

1

2

3

4

Overflow

1, 3, 4

ADS cannot skip

instruction 3, even if it

has a skip function.

No overflow

1, 2, 3, 4

xxx

SBC A,@HL

ADS A,#im

xxx

1

2

3

4

Borrow

1, 2, 3, 4

1, 3, 4

ADS cannot skip

instruction 3, even if it

has a skip function.

No borrow

xxx

ꢉ

ꢔꢕꢔꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢈꢒꢓꢔꢀꢕꢈꢆꢖꢗꢘꢆꢋꢀꢇꢁꢂꢇꢉꢄꢀꢇꢈ

Table 5-4. Data Type Symbols

Table 5-6. Instruction Operand Notation

Symbol Definition

Direct address

Symbol

Data Type

Immediate data

d

a

b

r

f

i

DA

@

src

dst

(R)

.b

Indirect address prefix

Source operand

Destination operand

Contents of register R

Bit location

Address data

Bit data

Register data

Flag data

Indirect addressing data

memc × 0.5 immediate data

im

4-bit immediate data (number)

8-bit immediate data (number)

Immediate data prefix

000H-3FFFH immediate address

'n' bit address

A, E, L, H, X, W, Z, Y

E, L, H, X, W, Z, Y

EA, HL, WX, YZ

t

imm

#

ADR

ADRn

R

Table 5-5. Register Identifiers

Full Register Name

ID

4-bit accumulator

A

Ra

4-bit working registers

E, L, H, X, W,

Z, Y

RR

8-bit extended accumulator

8-bit memory pointer

8-bit working registers

Select register bank 'n'

Select memory bank 'n'

Carry flag

EA

HL

RRa

RRb

RRc

mema

memb

memc

HL, WX, WL

HL, WX, YZ

WX, WL

FB0H-FBFH, FF0H-FFFH

FC0H-FFFH

WX, YZ, WL

SRB n

SMB n

C

Code direct addressing:

0020H-007FH

Program status word

Port 'n'

PSW

Pn

SB

Select bank register (8 bits)

Logical exclusive-OR

Logical OR

XOR

OR

'm'-th bit of port 'n'

Pn.m

IPR

EMB

ERB

Interrupt priority register

Enable memory bank flag

Enable register bank flag

AND

[(RR)]

Logical AND

Contents addressed by RR

ꢔꢕꢘꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢐꢋꢀꢑꢂꢆꢑꢂꢌꢄꢇꢄꢉꢄꢀꢇꢈ

Table 5-7. Opcode Definitions (Direct)

Table 5-8. Opcode Definitions (Indirect)

Register

r2

0

1

0

1

r1

0

1

0

1

0

1

0

1

r0

0

1

0

1

0

1

0

1

0

Register

@HL

@WX

@WL

i2

1

i1

0

1

i0

1

0

A

E

L

H

X

W

Z

Y

EA

HL

WX

YZ

1

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ꢙꢅꢅ1ꢅꢅ2ꢖꢖꢄꢎꢊꢌꢒꢄꢅꢎꢌꢒꢌꢅꢘꢕꢓꢅꢓꢄꢗꢊꢉꢒꢄꢓꢅ

ꢋꢍꢕꢋꢊꢕꢍꢉꢄꢇꢙꢆꢍꢑꢑꢄꢉꢄꢀꢇꢍꢕꢆꢓꢍꢋꢎꢄꢇꢂꢆꢋꢒꢋꢕꢂꢈꢆꢌꢀꢃꢆꢈꢏꢄꢐꢈꢆ

A machine cycle is defined as one cycle of the selected CPU clock. Three different clock rates can be selected

using the PCON register.

In this document, the letter 'S' is used in tables when describing the number of additional machine cycles required

for an instruction to execute, given that the instruction has a skip function ('S' = skip). The addition number of

machine cycles that will be required to perform the skip usually depends on the size of the instruction being

skipped — whether it is a 1-byte, 2-byte, or 3-byte instruction. A skip is also executed for SMB and SRB

instructions.

The values in additional machine cycles for 'S' for the three cases in which skip conditions occur are as follows:

Case 1: No skip

Case 2: Skip is 1-byte or 2-byte instruction

Case 3: Skip is 3-byte instruction

S = 0 cycles

S = 1 cycle

S = 2 cycles

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ꢉ

ꢔꢕꢃꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢎꢄꢙꢎꢚꢕꢂꢁꢂꢕꢆꢈꢊꢓꢓꢍꢃꢒꢆ

This section contains a high-level summary of the SAM47 instruction set in table format. The tables are designed

to familiarize you with the range of instructions that are available in each instruction category.

These tables are a useful quick-reference resource when writing application programs.

If you are reading this user's manual for the first time, however, you may want to scan this detailed information

briefly, and then return to it later on. The following information is provided for each instruction:

— Instruction name

— Operand(s)

— Brief operation description

— Number of bytes of the instruction and operand(s)

— Number of machine cycles required to execute the instruction

The tables in this section are arranged according to the following instruction categories:

— CPU control instructions

— Program control instructions

— Data transfer instructions

— Logic instructions

— Arithmetic instructions

— Bit manipulation instructions

ꢔꢕꢛꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

Table 5-9. CPU Control Instructions — High-Level Summary

Operand Operation Description

Set carry flag to logic one

Name

SCF

RCF

CCF

EI

Bytes

Cycles

–

1

2

1

2

1

2

1

2

1

2

3

2

Reset carry flag to logic zero

Complement carry flag

Enable all interrupts

Disable all interrupts

Engage CPU idle mode

Engage CPU stop mode

No operation

DI

IDLE

STOP

NOP

SMB

SRB

REF

n

Select memory bank

Select register bank

Reference code

memc

VENTn

EMB (0,1)

ERB (0,1)

ADR

Load enable memory bank flag (EMB) and the enable

register bank flag (ERB) and program counter to vector

address, then branch to the corresponding location

Table 5-10. Program Control Instructions — High-Level Summary

Name

CPSE

Operand

Operation Description

Compare and skip if register equals #im

Compare and skip if indirect data memory equals #im

Compare and skip if A equals R

Compare and skip if A equals indirect data memory

Compare and skip if EA equals indirect data memory

Compare and skip if EA equals RR

Long jump to direct address (15 bits)

Jump to direct address (14 bits)

Jump direct in page (12 bits)

Jump to immediate address

Branch relative to WX register

Branch relative to EA

Long call direct in page (15 bits)

Call direct in page (14 bits)

Bytes

Cycles

2 + S

1 + S

2 + S

3

R,#im

@HL,#im

A,R

A,@HL

EA,@HL

EA,RR

ADR

#im

@WX

@EA

ADR

–

2

1

2

3

2

1

2

3

2

1

LJP

JP

3

2

3

4

3

JPS

JR

LCALL

CALL

CALLS

RET

IRET

SRET

Call direct in page (11 bits)

Return from subroutine

Return from interrupt

Return from subroutine and skip

–

3

3 + S

ꢉ

ꢔꢕꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

Table 5-11. Data Transfer Instructions — High-Level Summary

Name

XCH

Operand

A,DA

A,Ra

A,@Rra

EA,DA

EA,RRb

EA,@HL

A,@HL

Operation Description

Exchange A and direct data memory contents

Exchange A and register (Ra) contents

Bytes

Cycles

2

1

2

1

2

1

2

Exchange A and indirect data memory

Exchange EA and direct data memory contents

Exchange EA and register pair (RRb) contents

Exchange EA and indirect data memory contents

Exchange A and indirect data memory contents;

increment contents of register L and skip on carry

Exchange A and indirect data memory contents;

decrement contents of register L and skip on carry

Load 4-bit immediate data to A

Load indirect data memory contents to A

Load direct data memory contents to A

Load register contents to A

Load 4-bit immediate data to register

Load 8-bit immediate data to register

Load contents of A to direct data memory

Load contents of A to register

Load indirect data memory contents to EA

Load direct data memory contents to EA

Load register contents to EA

Load contents of A to indirect data memory

Load contents of EA to data memory

Load contents of EA to register

2

XCHI

XCHD

LD

2 + S

A,@HL

1

2 + S

A,#im

A,@Rra

A,DA

1

2

1

2

1

2

1

2

A,Ra

Ra,#im

RR,#imm

DA,A

Ra,A

EA,@HL

EA,DA

EA,RRb

@HL,A

DA,EA

RRb,EA

@HL,EA

A,@HL

Load contents of EA to indirect data memory

Load indirect data memory to A; increment register L

contents and skip on carry

LDI

2 + S

LDD

LDC

A,@HL

Load indirect data memory contents to A; decrement

register L contents and skip on carry

Load code byte from WX to EA

Load code byte from EA to EA

Rotate right through carry bit

1

2 + S

EA,@WX

EA,@EA

A

RR

SB

1

2

1

2

3

1

2

1

2

RRC

PUSH

Push register pair onto stack

Push SMB and SRB values onto stack

Pop to register pair from stack

Pop SMB and SRB values from stack

POP

RR

SB

ꢔꢕꢖꢜꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

Table 5-12. Logic Instructions — High-Level Summary

Name

AND

Operand

A,#im

Operation Description

Logical-AND A immediate data to A

Logical-AND A indirect data memory to A

Logical-AND register pair (RR) to EA

Logical-AND EA to register pair (RRb)

Logical-OR immediate data to A

Logical-OR indirect data memory contents to A

Logical-OR double register to EA

Logical-OR EA to double register

Exclusive-OR immediate data to A

Exclusive-OR indirect data memory to A

Exclusive-OR register pair (RR) to EA

Exclusive-OR register pair (RRb) to EA

Complement accumulator (A)

Bytes

Cycles

2

1

2

1

2

1

2

1

2

1

2

1

2

A,@HL

EA,RR

RRb,EA

A, #im

A, @HL

EA,RR

RRb,EA

A,#im

A,@HL

EA,RR

RRb,EA

A

OR

XOR

COM

Table 5-13. Arithmetic Instructions — High-Level Summary

Name

ADC

Operand

Operation Description

Add indirect data memory to A with carry

Add register pair (RR) to EA with carry

Add EA to register pair (RRb) with carry

Bytes

Cycles

1

A,@HL

EA,RR

RRb,EA

A, #im

EA,#imm

A,@HL

EA,RR

RRb,EA

A,@HL

EA,RR

RRb,EA

A,@HL

EA,RR

RRb,EA

R

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

ADS

Add 4-bit immediate data to A and skip on carry

Add 8-bit immediate data to EA and skip on carry

Add indirect data memory to A and skip on carry

Add register pair (RR) contents to EA and skip on carry

Add EA to register pair (RRb) and skip on carry

Subtract indirect data memory from A with carry

Subtract register pair (RR) from EA with carry

Subtract EA from register pair (RRb) with carry

Subtract indirect data memory from A; skip on borrow

Subtract register pair (RR) from EA; skip on borrow

Subtract EA from register pair (RRb); skip on borrow

Decrement register ®; skip on borrow

Decrement register pair (RR); skip on borrow

Increment register ®; skip on carry

Increment direct data memory; skip on carry

Increment indirect data memory; skip on carry

Increment register pair (RRb); skip on carry

1 + S

2 + S

1 + S

2 + S

1

SBC

SBS

2

1 + S

2 + S

1 + S

2 + S

1 + S

2 + S

1 + S

DECS

INCS

RR

R

DA

@HL

RRb

ꢉ

ꢔꢕꢖꢖꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

Table 5-14. Bit Manipulation Instructions — High-Level Summary

Name

BTST

Operand

Operation Description

Test specified bit and skip if carry flag is set

Test specified bit and skip if memory bit is set

Bytes

Cycles

1 + S

2 + S

C

1

2

DA.b

mema.b

memb.@L

@H+DA.b

DA.b

BTSF

Test specified memory bit and skip if bit equals “0”

mema.b

memb.@L

@H+DA.b

mema.b

memb.@L

@H+DA.b

DA.b

BTSTZ

BITS

Test specified bit; skip and clear if memory bit is set

Set specified memory bit

2

mema.b

memb.@L

@H+DA.b

DA.b

BITR

Clear specified memory bit to logic zero

mema.b

memb.@L

@H+DA.b

C,mema.b

C,memb.@L

C,@H+DA.b

C,mema.b

C,memb.@L

C,@H+DA.b

C,mema.b

C,memb.@L

C,@H+DA.b

mema.b,C

memb.@L,C

@H+DA.b,C

C,mema.b

C,memb.@L

C,@H+DA.b

BAND

BOR

Logical-AND carry flag with specified memory bit

Logical-OR carry with specified memory bit

Exclusive-OR carry with specified memory bit

BXOR

LDB

Load carry bit to a specified memory bit

Load carry bit to a specified indirect memory bit

Load specified memory bit to carry bit

Load specified indirect memory bit to carry bit

ꢔꢕꢖꢄꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢔꢄꢇꢍꢃꢒꢆꢋꢀꢑꢂꢆꢈꢊꢓꢓꢍꢃꢒꢆ

This section contains binary code values and operation notation for each instruction in the SAM47 instruction set in

an easy-to-read, tabular format. It is intended to be used as a quick-reference source for programmers who are

experienced with the SAM47 instruction set. The same binary values and notation are also included in the detailed

descriptions of individual instructions later in Section 5.

If you are reading this user’s manual for the first time, please just scan this very detailed information briefly. Most

of the general information you will need to write application programs can be found in the high-level summary

tables in the previous section. The following information is provided for each instruction:

— Instruction name

— Operand(s)

— Binary values

— Operation notation

The tables in this section are arranged according to the following instruction categories:

— CPU control instructions

— Program control instructions

— Data transfer instructions

— Logic instructions

— Arithmetic instructions

— Bit manipulation instructions

ꢉ

ꢔꢕꢖꢁꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

Table 5-15. CPU Control Instructions — Binary Code Summary

Operand Binary Code Operation Notation

Name

SCF

RCF

CCF

EI

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢒꢝꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

ꢒ5ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢒ6ꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

ꢒꢜꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

C ← 1

C ← 0

C ← ꢀꢁ

IME ← 1

DI

IME ← 0

IDLE

STOP

PCON.2 ← 1

PCON.3 ←1

NOP

SMB

No operation

SMB ← n (n = 0, … ,15)

n

ꢎ+ꢅ ꢎ(ꢅ ꢎꢀꢅ ꢎ.ꢅ

SRB

SRB ← n (n = 0, 1, 2, 3)

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

ꢎꢀꢅ ꢎ.ꢅ

REF

memc

PC13-0 ← memc.7-4, memc.3-0 < 1

ꢒ+ꢅ

ꢒ(ꢅ

ꢒꢀꢅ

ꢒ.ꢅ

VENTn

EMB (0,1)

ERB (0,1)

ADR

ROM (2 x n) 7-6 → EMB, ERB

ROM (2 x n) 5-4 → PC13-12

ROM (2 x n) 3-0 → PC11-8

ROM (2 x n + 1) 7-0 → PC7-0

(n = 0, 1, 2, 3, 4, 5, 6, 7)

3ꢅ

ꢈꢅ

*ꢅ

3ꢅ ꢌꢀ+ꢅ ꢌꢀ(ꢅ ꢌꢀꢀꢅ ꢌꢀ.ꢅ ꢌ7ꢅ ꢌ8ꢅ

ꢆꢅ

*ꢅ

ꢌꢝꢅ ꢌ5ꢅ ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

ꢔꢕꢖꢌꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

Table 5-16. Program Control Instructions — Binary Code Summary

Name

CPSE

Operand

R,#im

Binary Code

Operation Notation

Skip if R = im

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢓ(ꢅ ꢓꢀꢅ ꢓ.ꢅ

ꢀꢅ .ꢅ ꢀꢅ

.ꢅ

ꢀꢅ

ꢎ+ꢅ ꢎ(ꢅ ꢎꢀꢅ ꢎ.ꢅ

@HL,#im

A,R

Skip if (HL) = im

Skip if A = R

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

ꢎ+ꢅ ꢎ(ꢅ ꢎꢀꢅ ꢎ.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

ꢓ(ꢅ ꢓꢀꢅ ꢓ.ꢅ

A,@HL

EA,@HL

Skip if A = (HL)

Skip if A = (HL), E = (HL+1)

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

EA,RR

ADR

Skip if EA = RR

ꢓ(ꢅ ꢓꢀꢅ

.ꢅ .ꢅ

LJP

JP

PC14-0 ← ADR14-0

.ꢅ ꢌꢀꢜꢅ ꢌꢀ+ꢅ ꢌꢀ(ꢅ ꢌꢀꢀꢅ ꢌꢀ.ꢅ ꢌ7ꢅ ꢌ8ꢅ

ꢌꢝꢅ ꢌ5ꢅ ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

ADR

PC13-0 ← ADR13-0

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ ꢌꢀ+ꢅ ꢌꢀ(ꢅ ꢌꢀꢀꢅ ꢌꢀ.ꢅ ꢌ7ꢅ ꢌ8ꢅ

ꢌꢝꢅ ꢌ5ꢅ ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

JPS

JR

PC14-0 ← PC14-12 + ADR11-0

ꢀꢅ

.ꢅ

ꢀꢅ ꢌꢀꢀꢅ ꢌꢀ.ꢅ ꢌ7ꢅ ꢌ8ꢅ

ꢌꢝꢅ ꢌ5ꢅ ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

ꢅ

PC13-0 ← ADR (PC-15 to PC+16)

PC13-0 ← PC13-8 + (WX)

#im ꢀ

@WX

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

@EA

ADR

PC13-0 ← PC13-8 + (EA)

LCALL

CALL

[(SP-1) (SP-2)] ← EMB, ERB

.ꢅ ꢌꢀꢜꢅ ꢌꢀ+ꢅ ꢌꢀ(ꢅ ꢌꢀꢀꢅ ꢌꢀ.ꢅ ꢌ7ꢅ ꢌ8ꢅ [(SP-3) (SP-4)] ← PC7-0

ꢌꢝꢅ ꢌ5ꢅ ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ [(SP-5) (SP-6)] ← PC14-8

[(SP-1) (SP-2)] ← EMB, ERB

ADR

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

ꢀꢅ ꢌꢀ+ꢅ ꢌꢀ(ꢅ ꢌꢀꢀꢅ ꢌꢀ.ꢅ ꢌ7ꢅ ꢌ8ꢅ [(SP-3) (SP-4)] ← PC7-0

ꢌꢝꢅ ꢌ5ꢅ ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ [(SP-5) (SP-6)] ← PC13-8

[(SP-1) (SP-2)] ← EMB, ERB

CALLS

ꢀꢅ

.ꢅ

ꢀꢅ ꢌꢀ.ꢅ ꢌ7ꢅ ꢌ8ꢅ

ꢌꢝꢅ ꢌ5ꢅ ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ [(SP-3) (SP-4)] ← PC7-0

[(SP-5) (SP-6)] ← PC14-8

ꢉ

ꢔꢕꢖꢔꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

First Byte

Condition

.ꢅ

ꢀꢅ

ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ PC ← PC+2 to PC+16

ꢀꢅꢅJR #im

.ꢅ

ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ PC ← PC-1 to PC-15

Table 5-16. Program Control Instructions — Binary Code Summary (Continued)

Name

Operand

Binary Code

Operation Notation

RET

–

PC14-8 ← (SP + 1) (SP)

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

PC7-0 ← (SP + 3) (SP + 2)

EMB,ERB ← (SP + 5) (SP + 4)

SP ← SP + 6

IRET

–

PC14-8 ← (SP + 1) (SP)

PC7-0 ← (SP + 3) (SP + 2)

PSW ← (SP + 5) (SP + 4)

SP ← SP + 6

PC14-8 ← (SP + 1) (SP)

PC7-0 ← (SP + 3) (SP + 2)

EMB,ERB ← (SP + 5) (SP + 4)

SP ← SP + 6

SRET

ꢔꢕꢖꢘꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

Table 5-17. Data Transfer Instructions — Binary Code Summary

Operand Binary Code Operation Notation

A,DA

Name

XCH

.ꢅ

ꢀꢅ

ꢀꢅ ꢀꢅ

.ꢅ

ꢀꢅ

A ↔ DA

ꢌꢝꢅ ꢌ5ꢅ ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

A,Ra

A,@RRa

EA,DA

A ↔ Ra

A ↔ (RRa)

A ↔ DA,E ↔ DA + 1

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

ꢓ(ꢅ ꢓꢀꢅ ꢓ.ꢅ

ꢊ(ꢅ

ꢀꢅ

ꢊꢀꢅ

ꢀꢅ

ꢊ.ꢅ

ꢀꢅ

ꢌꢝꢅ ꢌ5ꢅ ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

EA,RRb

EA,@HL

EA ↔ RRb

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢓ(ꢅ ꢓꢀꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

A ↔ (HL), E ↔ (HL + 1)

XCHI

XCHD

LD

A,@HL

A ↔ (HL), then L ← L+1;

skip if L = 0H

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

A ↔ (HL), then L ← L-1;

skip if L = 0FH

A,#im

A,@RRa

A,DA

A ← im

A ← (RRa)

A ← DA

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢎ+ꢅ ꢎ(ꢅ ꢎꢀꢅ ꢎ.ꢅ

ꢀꢅ

ꢊ(ꢅ

ꢀꢅ

ꢊꢀꢅ

.ꢅ

ꢊ.ꢅ

.ꢅ

ꢌꢝꢅ ꢌ5ꢅ ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

A,Ra

A ← Ra

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

ꢓ(ꢅ ꢓꢀꢅ ꢓ.ꢅ

ꢉ

ꢔꢕꢖꢃꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

Table 5-17. Data Transfer Instructions — Binary Code Summary (Continued)

Operand Binary Code Operation Notation

Ra,#im

Name

LD

ꢀꢅ

ꢎ+ꢅ ꢎ(ꢅ ꢎꢀꢅ ꢎ.ꢅ

ꢀꢅ .ꢅ .ꢅ .ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢓ(ꢅ ꢓꢀꢅ ꢓ.ꢅ

ꢓ(ꢅ ꢓꢀꢅ ꢀꢅ

.ꢅ

ꢀꢅ

Ra ← im

RR,#imm

DA,A

RR ← imm

ꢎꢝꢅ ꢎ5ꢅ ꢎ6ꢅ ꢎꢜꢅ ꢎ+ꢅ ꢎ(ꢅ ꢎꢀꢅ ꢎ.ꢅ

ꢀꢅ .ꢅ .ꢅ .ꢅ ꢀꢅ .ꢅ .ꢅ ꢀꢅ

ꢌꢝꢅ ꢌ5ꢅ ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

DA ← A

Ra,A

Ra ← A

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

ꢓ(ꢅ ꢓꢀꢅ ꢓ.ꢅ

EA,@HL

EA,DA

EA,RRb

A ← (HL), E ← (HL + 1)

A ← DA, E ← DA + 1

EA ← RRb

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢌꢝꢅ ꢌ5ꢅ ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

ꢓ(ꢅ ꢓꢀꢅ

@HL,A

DA,EA

(HL) ← A

DA ← A, DA + 1 ← E

ꢀꢅ

.ꢅ

ꢌꢝꢅ ꢌ5ꢅ ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

RRb,EA

@HL,EA

RRb ← EA

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢓ(ꢅ ꢓꢀꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

(HL) ← A, (HL + 1) ← E

LDI

A,@HL

A ← (HL), then L ← L+1;

skip if L = 0H

LDD

LDC

A ← (HL), then L ← L-1;

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

skip if L = 0FH

EA,@WX

EA,@EA

A

EA ← [PC14-8 + (WX)]

EA ← [PC14-8 + (EA)]

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

RRC

C ← A.0, A3 ← C

A.n-1 ← A.n (n = 1, 2, 3)

PUSH

RR

SB

((SP-1)) ((SP-2)) ← (RR),

(SP) ← (SP)-2

((SP-1)) ← (SMB), ((SP-2)) ← (SRB),

(SP) ← (SP)-2

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢓ(ꢅ ꢓꢀꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

ꢔꢕꢖꢛꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

Table 5-17. Data Transfer Instructions — Binary Code Summary (Concluded)

Operand Binary Code Operation Notation

RR

Name

POP

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

ꢓ(ꢅ ꢓꢀꢅ

.ꢅ

RR ← (SP), RR ← (SP + 1)

ꢅ

ꢈ

ꢇ

SP ← SP + 2

SB

(SRB) ← (SP), SMB ← (SP + 1),

SP ← SP + 2

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

Table 5-18. Logic Instructions — Binary Code Summary

Binary Code Operation Notation

ꢀꢅ

ꢎ+ꢅ ꢎ(ꢅ ꢎꢀꢅ ꢎ.ꢅ

Name

AND

Operand

A,#im

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

A ← A AND im

A,@HL

EA,RR

A ← A AND (HL)

EA ← EA AND RR

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

ꢓ(ꢅ ꢓꢀꢅ

ꢀꢅ .ꢅ

ꢓ(ꢅ ꢓꢀꢅ

ꢀꢅ .ꢅ

RRb,EA

A, #im

RRb ← RRb AND EA

A ← A OR im

OR

ꢎ+ꢅ ꢎ(ꢅ ꢎꢀꢅ ꢎ.ꢅ

A, @HL

EA,RR

A ← A OR (HL)

EA ← EA OR RR

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

ꢓ(ꢅ ꢓꢀꢅ

ꢀꢅ .ꢅ

ꢓ(ꢅ ꢓꢀꢅ

ꢀꢅ .ꢅ

RRb,EA

A,#im

RRb ← RRb OR EA

A ← A XOR im

XOR

COM

ꢎ+ꢅ ꢎ(ꢅ ꢎꢀꢅ ꢎ.ꢅ

A,@HL

EA,RR

A ← A XOR (HL)

EA ← EA XOR (RR)

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

ꢓ(ꢅ ꢓꢀꢅ

ꢀꢅ .ꢅ

ꢓ(ꢅ ꢓꢀꢅ

RRb,EA

A

RRb ← RRb XOR EA

A ← ꢂ

ꢀꢅ

.ꢅ

ꢀꢅ

ꢉ

ꢔꢕꢖꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

Table 5-19. Arithmetic Instructions — Binary Code Summary

Operand Binary Code Operation Notation

A,@HL

C, A ← A + (HL) + C

Name

ADC

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

EA,RR

C, EA ← EA + RR + C

C, RRb ← RRb + EA + C

A ← A + im; skip on carry

ꢓ(ꢅ ꢓꢀꢅ

ꢀꢅ .ꢅ

ꢓ(ꢅ ꢓꢀꢅ

RRb,EA

ADS

A, #im

ꢎ+ꢅ ꢎ(ꢅ ꢎꢀꢅ ꢎ.ꢅ

EA,#imm

EA ← EA + imm; skip on carry

ꢀꢅ

.ꢅ

ꢀꢅ

ꢎꢝꢅ ꢎ5ꢅ ꢎ6ꢅ ꢎꢜꢅ ꢎ+ꢅ ꢎ(ꢅ ꢎꢀꢅ ꢎ.ꢅ

A,@HL

EA,RR

A ← A+ (HL); skip on carry

EA ← EA + RR; skip on carry

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢓ(ꢅ ꢓꢀꢅ

ꢀꢅ .ꢅ

ꢓ(ꢅ ꢓꢀꢅ

RRb,EA

RRb ← RRb + EA; skip on carry

SBC

SBS

A,@HL

EA,RR

C,A ← A-(HL)-C

C, EA ← EA-RR-C

ꢀꢅ

.ꢅ

ꢓ(ꢅ ꢓꢀꢅ

ꢀꢅ .ꢅ

ꢓ(ꢅ ꢓꢀꢅ

RRb,EA

C,RRb ← RRb-EA-C

A,@HL

EA,RR

A ← A-(HL); skip on borrow

EA ← EA-RR; skip on borrow

ꢀꢅ

.ꢅ

ꢓ(ꢅ ꢓꢀꢅ

ꢀꢅ .ꢅ

ꢓ(ꢅ ꢓꢀꢅ

ꢓ(ꢅ ꢓꢀꢅ ꢓ.ꢅ

RRb,EA

RRb ← RRb-EA; skip on borrow

DECS

INCS

R

RR

R ← R-1; skip on borrow

RR ← RR-1; skip on borrow

ꢀꢅ

.ꢅ

ꢓ(ꢅ ꢓꢀꢅ

R

DA

R ← R+1; skip on carry

DA ← DA+1; skip on carry

ꢓ(ꢅ ꢓꢀꢅ ꢓ.ꢅ

.ꢅ ꢀꢅ .ꢅ

ꢌꢝꢅ ꢌ5ꢅ ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

@HL

RRb

(HL) ← (HL)+1; skip on carry

RRb ← RRb+1; skip on carry

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢓ(ꢅ ꢓꢀꢅ

ꢔꢕꢄꢜꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

Table 5-20. Bit Manipulation Instructions — Binary Code Summary

Operand Binary Code Operation Notation

Skip if C = 1

Name

BTST

C

ꢀꢅ

.ꢅ

ꢀꢅ .ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

DA.b

Skip if DA.b = 1

ꢏꢀꢅ ꢏ.ꢅꢅ .ꢅ

ꢌꢝꢅ ꢌ5ꢅ ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

Skip if mema.b = 1

ꢀꢅ

.ꢅ

ꢀꢅ

mema.b ꢀ

memb.@L

@H+DA.b

DA.b

ꢅ

Skip if [memb.7-2 + L.3-2].[L.1-0] = 1

Skip if [H + DA.3-0].b = 1

Skip if DA.b = 0

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ

ꢀꢅ .ꢅ .ꢅ ꢀꢅ

ꢏꢀꢅ ꢏ.ꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

ꢏꢀꢅ ꢏ.ꢅ .ꢅ .ꢅ ꢀꢅ .ꢅ

BTSF

ꢌꢝꢅ ꢌ5ꢅ ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

Skip if mema.b = 0

ꢀꢅ

.ꢅ

^mema.bꢀ

memb.@L

@H+DA.b

mema.b ꢀ

memb.@L

ꢅ

Skip if [memb.7-2 + L.3-2].[L.1-0] = 0

Skip if [H + DA.3-0].b = 0

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ

ꢀꢅ .ꢅ .ꢅ .ꢅ

ꢏꢀꢅ ꢏ.ꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

BTSTZ

Skip if mema.b = 1 and clear

ꢀꢅ

.ꢅ

ꢀꢅ

ꢅ

Skip if [memb.7-2 + L.3-2].

[L.1-0] = 1 and clear

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ

@H+DA.b

DA.b

Skip if [H + DA.3-0].b =1 and clear

ꢀꢅ

.ꢅ

ꢀꢅ

ꢏꢀꢅ ꢏ.ꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

BITS

DA.b ← 1

ꢏꢀꢅ ꢏ.ꢅ

.ꢅ

ꢀꢅ

ꢌꢝꢅ ꢌ5ꢅ ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

ꢀꢅ

ꢀꢅ mema.b ← 1

mema.b ꢀ

memb.@L

@H+DA.b

ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

[memb.7-2 + L.3-2].[L.1-0] ← 1

ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ

ꢀꢅ

[H + DA.3-0].b ← 1

ꢏꢀꢅ ꢏ.ꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

ꢉ

ꢔꢕꢄꢖꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

Table 5-20. Bit Manipulation Instructions — Binary Code Summary (Continued)

Operand Binary Code Operation Notation

DA.b

Name

BITR

ꢀꢅ

ꢏꢀꢅ ꢏ.ꢅ .ꢅ

.ꢅ

DA.b ← 0

ꢌꢝꢅ ꢌ5ꢅ ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

ꢀꢅ

.ꢅ mema.b ← 0

mema.b ꢀ

ꢅ

memb.@L

@H+DA.b

^C,mema.bꢀ

C,memb.@L

[memb.7-2 + L3-2].[L.1-0] ← 0

[H + DA.3-0].b ← 0

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ

ꢀꢅ ꢀꢅ ꢀꢅ .ꢅ

ꢏꢀꢅ ꢏ.ꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

BAND

BOR

C ← C AND mema.b

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

C ← C AND [memb.7-2 + L.3-2].

[L.1-0]

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ

C,@H+DA.b

C,mema.b ꢀ

C,memb.@L

C ← C AND [H + DA.3-0].b

C ← C OR mema.b

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

ꢏꢀꢅ ꢏ.ꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

C ← C OR [memb.7-2 + L.3-2].

[L.1-0]

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ

C,@H+DA.b

^C,mema.bꢀ

C,memb.@L

C ← C OR [H + DA.3-0].b

C ← C XOR mema.b

.ꢅ

ꢀꢅ

.ꢅ

ꢏꢀꢅ ꢏ.ꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

BXOR

ꢀꢅ

.ꢅ

ꢀꢅ

ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

C ← C XOR [memb.7-2 + L.3-2].

[L.1-0]

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ

C,@H+DA.b

C ← C XOR [H + DA.3-0].b

.ꢅ

ꢀꢅ

ꢏꢀꢅ ꢏ.ꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

Second Byte

ꢏꢀꢅ ꢏ.ꢅꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

Bit Addresses

FB0H-FBFH

ꢀꢅ

.ꢅ

ꢀꢅ

ꢀ ^mema.b

FF0H-FFFH

ꢏꢀꢅ ꢏ.ꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

ꢔꢕꢄꢄꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

Table 5-20. Bit Manipulation Instructions — Binary Code Summary (Concluded)

Name

LDB

Operand

Binary Code

Operation Notation

mema.b ← C

ꢀꢅ

.ꢅ

mema.b,C ꢀ

ꢅ

memb.@L,C

@H+DA.b,C

C,mema.b ꢀ

C,memb.@L

C,@H+DA.b

memb.7-2 + [L.3-2]. [L.1-0] ← C

H+[DA.3-0].b ← (C)

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ

ꢀꢅ ꢀꢅ .ꢅ .ꢅ

ꢏꢀꢅ ꢏ.ꢅꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

.ꢅ C ← mema.b

ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

ꢀꢅ

.ꢅ

C ← memb.7-2+[L.3-2]. [L.1-0]

ꢌ6ꢅ ꢌꢜꢅ ꢌ+ꢅ ꢌ(ꢅ

.ꢅ

ꢀꢅ

.ꢅ

C ← [H + DA.3-0].b

ꢏꢀꢅ ꢏ.ꢅꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

Second Byte

ꢏꢀꢅ ꢏ.ꢅꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

Bit Addresses

FB0H-FBFH

ꢀꢅ

.ꢅ

ꢀꢅ

ꢀ ^mema.b

FF0H-FFFH

ꢏꢀꢅ ꢏ.ꢅ ꢌ+ꢅ ꢌ(ꢅ ꢌꢀꢅ ꢌ.ꢅ

ꢆ

ꢉ

ꢔꢕꢄꢁꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢄꢇꢈꢉꢃꢊꢋꢉꢄꢀꢇꢆꢑꢂꢈꢋꢃꢄꢐꢉꢄꢀꢇꢈꢆ

This section contains detailed information and programming examples for each instruction of the SAM47

instruction set. Information is arranged in a consistent format to improve readability and for use as a quick-

reference resource for application programmers.

If you are reading this user's manual for the first time, please just scan this very detailed information briefly in order

to acquaint yourself with the basic features of the instruction set. The information elements of the instruction

description format are as follows:

— Instruction name (mnemonic)

— Full instruction name

— Source/destination format of the instruction operand

— Operation overview (from the "High-Level Summary" table)

— Textual description of the instruction's effect

— Binary code overview (from the "Binary Code Summary" table)

— Programming example(s) to show how the instruction is used

ꢔꢕꢄꢌꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢂꢎꢋꢆꢛꢆꢍꢘꢘꢆꢜꢝꢞ ꢆꢋꢖ!!"ꢁ

ADC

dst,src

Operand

Operation:

Operation Summary

Add indirect data memory to A with carry

Add register pair (RR) to EA with carry

Add EA to register pair (RRb) with carry

Bytes

Cycles

A,@HL

EA,RR

RRb,EA

1

2

1

2

Description: The source operand, along with the setting of the carry flag, is added to the destination operand

and the sum is stored in the destination. The contents of the source are unaffected. If there is an

overflow from the most significant bit of the result, the carry flag is set; otherwise, the carry flag is

cleared.

If 'ADC A,@HL' is followed by an 'ADS A,#im' instruction in a program, ADC skips the ADS

instruction if an overflow occurs. If there is no overflow, the ADS instruction is executed normally.

(This condition is valid only for 'ADC A,@HL' instructions. If an overflow occurs following an 'ADS

A,#im' instruction, the next instruction will not be skipped.)

Operand

A,@HL

EA,RR

Binary Code

Operation Notation

C, A ← A + (HL) + C

C, EA ← EA + RR + C

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

r2

1

0

r1

0

RRb,EA

C, RRb ← RRb + EA + C

r2

r1

Examples:

1. The extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and

the carry flag is set to "1":

SCF

ADC

JPS

; C ← "1"

EA,HL

XXX

; EA ← 0C3H + 0AAH + 1H = 6EH, C ← "1"

; Jump to XXX;no skip after ADC

2. If the extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and

the carry flag is cleared to "0":

RCF

ADC

JPS

; C ← "0"

EA,HL

XXX

; EA ← 0C3H + 0AAH + 0H = 6DH, C ← "1"

; Jump to XXX; no skip after ADC

ꢉ

ꢔꢕꢄꢔꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢂꢎꢋꢆꢛꢆꢍꢘꢘꢆꢜꢝꢞ ꢆꢋꢖ!!"ꢀ

ADC

(Continued)

Examples:

3. If ADC A,@HL is followed by an ADS A,#im, the ADC skips on carry to the instruction

immediately after the ADS. An ADS instruction immediately after the ADC does not skip even

if an overflow occurs. This function is useful for decimal adjustment operations.

a. 8 + 9 decimal addition (the contents of the address specified by the HL register is 9H):

RCF

LD

; C ← "0"

A,#8H

A,#6H

A,@HL

A,#0AH

XXX

; A ← 8H

ADS

ADC

ADS

JPS

; A ← 8H + 6H = 0EH

; A ← 0EH + 9H + C(0), C ← "1"

; Skip this instruction because C = "1" after ADC result

b. 3 + 4 decimal addition (the contents of the address specified by the HL register is 4H):

RCF

LD

; C ← "0"

A,#3H

; A ← 3H

ADS

ADC

ADS

A,#6H

; A ← 3H + 6H = 9H

A,@HL

A,#0AH

; A ← 9H + 4H + C(0) = 0DH

; No skip. A ← 0DH + 0AH = 7H

; (The skip function for 'ADS A,#im' is inhibited after an

; 'ADC A,@HL' instruction even if an overflow occurs.)

JPS

XXX

ꢔꢕꢄꢘꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢂꢎꢁ^ꢀ^{ꢛꢆꢍꢘꢘꢆꢖꢗꢘꢆꢈ#ꢝ$ꢆ%ꢗꢆꢀ&'!()%ꢜ}ꢀ

ADS

Operation:

dst,src

Operand

Operation Summary

Bytes

Cycles

1 + S

2 + S

1 + S

2 + S

A, #im

Add 4-bit immediate data to A and skip on overflow

Add 8-bit immediate data to EA and skip on overflow

Add indirect data memory to A and skip on overflow

Add register pair (RR) contents to EA and skip on

overflow

1

2

1

2

EA, #imm

A,@HL

EA,RR

RRb, EA

Add EA to register pair (RRb) and skip on overflow

2

2 + S

Description: The source operand is added to the destination operand and the sum is stored in the destination.

The contents of the source are unaffected. If there is an overflow from the most significant bit of

the result, the skip signal is generated and a skip is executed, but the carry flag value is

unaffected.

If 'ADS A,#im' follows an 'ADC A,@HL' instruction in a program, ADC skips the ADS instruction if

an overflow occurs. If there is no overflow, the ADS instruction is executed normally. This skip

condition is valid only for 'ADC A,@HL' instructions, however. If an overflow occurs following an

ADS instruction, the next instruction is not skipped.

Operand

A, #im

EA,#imm

Binary Code

Operation Notation

1

0

1

0

d3 d2 d1 d0 A ← A + im; skip on overflow

1

0

1

EA ← EA + imm; skip on overflow

d7 d6 d5 d4 d3 d2 d1 d0

A,@HL

EA,RR

0

1

0

1

0

1

0

1

0

1

0

1

r2

1

0

r1

0

1

0

A ← A + (HL); skip on overflow

EA ← EA + RR; skip on overflow

RRb,EA

RRb ← RRb + EA; skip on overflow

r2

r1

Examples:

1. The extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and

the carry flag = "0":

ADS

EA,HL

; EA ← 0C3H + 0AAH = 6DH

; ADS skips on overflow, but carry flag value is not

; affected.

JPS

XXX

YYY

; This instruction is skipped since ADS had an overflow.

; Jump to YYY.

ꢉ

ꢔꢕꢄꢃꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢂꢎꢁꢆꢛꢆꢍꢘꢘꢆꢖꢗꢘꢆꢈ#ꢝ$ꢆ%ꢗꢆꢀ&'!()%ꢜꢀ

ADS

(Continued)

Examples:

2. If the extended accumulator contains the value 0C3H, register pair HL the value 12H, and

the carry flag = "0":

ADS

JPS

EA,HL

XXX

; EA ← 0C3H + 12H = 0D5H

; Jump to XXX; no skip after ADS.

3. If 'ADC A,@HL' is followed by an 'ADS A,#im', the ADC skips on overflow to the instruction

mmediately after the ADS. An 'ADS A,#im' instruction immediately after the 'ADC A,@HL'

does not skip even if overflow occurs. This function is useful for decimal adjustment

operations.

a. 8 + 9 decimal addition (the contents of the address specified by the HL register is 9H):

RCF

LD

; C ← "0"

A,#8H

A,#6H

A,@HL

A,#0AH

XXX

; A ← 8H

ADS

ADC

ADS

JPS

; A ← 8H + 6H = 0EH

; A ← 0EH + 9H + C(0) = 7H, C ← "1"

; Skip this instruction because C = "1" after ADC result.

b. 3 + 4 decimal addition (the contents of the address specified by the HL register is 4H):

RCF

LD

; C ← "0"

A,#3H

; A ← 3H

ADS

ADC

ADS

A,#6H

; A ← 3H + 6H = 9H

A,@HL

A,#0AH

; A ← 9H + 4H + C(0) = 0DH, C ← "0"

; No skip. A ← 0DH + 0AH = 7H

; (The skip function for 'ADS A,#im' is inhibited after an

; 'ADC A,@HL' instruction even if an overflow occurs.)

JPS

XXX

ꢔꢕꢄꢛꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢂꢇꢎ^ꢀ^{ꢛꢆꢕ%*ꢝ+ꢖ)ꢆꢍꢇꢑ}ꢀ

AND

dst,src

Operand

Operation:

Operation Summary

Logical-AND A immediate data to A

Logical-AND A indirect data memory to A

Logical-AND register pair (RR) to EA

Logical-AND EA to register pair (RRb)

Bytes

Cycles

A,#im

2

1

2

1

2

A,@HL

EA,RR

RRb,EA

Description: The source operand is logically ANDed with the destination operand. The result is stored in the

destination. The logical AND operation results in a "1" whenever the corresponding bits in the two

operands are both "1"; otherwise a "0" is stored in the corresponding destination bit. The contents

of the source are unaffected.

Operand

A,#im

Binary Code

Operation Notation

A ← A AND im

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

d3 d2 d1 d0

A,@HL

EA,RR

1

0

1

r2

1

0

r1

0

1

0

A ← A AND (HL)

EA ← EA AND RR

RRb,EA

RRb ← RRb AND EA

r2

r1

Example:

If the extended accumulator contains the value 0C3H (11000011B) and register pair HL the value

55H (01010101B), the instruction

AND

EA,HL

leaves the value 41H (01000001B) in the extended accumulator EA .

ꢉ

ꢔꢕꢄꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢏꢂꢇꢎ^ꢀꢛꢆꢔꢝꢞꢆꢕ%*ꢝ+ꢖ)ꢆꢍꢇꢑꢁ

BAND

C,src.b

Operand

Operation:

Operation Summary

Bytes

Cycles

C,mema.b

C,memb.@L

C,@H+DA.b

Logical-AND carry flag with memory bit

2

Description: The specified bit of the source is logically ANDed with the carry flag bit value. If the Boolean value

of the source bit is a logic zero, the carry flag is cleared to "0"; otherwise, the current carry flag

setting is left unaltered. The bit value of the source operand is not affected.

Operand

^C,mema.bꢀ

Binary Code

Operation Notation

C ← C AND mema.b

1

0

1

0

1

C,memb.@L

C,@H+DA.b

1

0

C ← C AND [memb.7-2 + L.3-2].

[L.1-0]

0

1

0

1

0

1

0

1

a5 a4 a3 a2

0

1

0

1

C ← C AND [H + DA.3-0].b

b1 b0 a3 a2 a1 a0

Second Byte

Bit Addresses

1

0

1

b1 b0 a3 a2 a1 a0 FB0H-FBFH

ꢀꢅ mema.b

b1 b0 a3 a2 a1 a0 FF0H-FFFH

Examples:

1. The following instructions set the carry flag if P1.0 (port 1.0) is equal to "1" (and assuming the

carry flag is already set to "1"):

SMB

15

; C ← "1"

BAND

C,P1.0

; If P1.0 = "1", C ← "1"

; If P1.0 = "0", C ← "0"

2. Assume the P1 address is FF1H and the value for register L is 5H (0101B). The address

(memb.7-2) is 111100B; (L.3-2) is 01B. The resulting address is 11110001B or FF1H,

specifying P1. The bit value for the BAND instruction, (L.1-0) is 01B which specifies bit 1.

Therefore, P1.@L = P1.1:

LD

L,#5H

BAND

C,P1.@L

; P1.@L is specified as P1.1

; C AND P1.1

ꢔꢕꢁꢜꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢏꢂꢇꢎꢆꢛꢆꢔꢝꢞꢆꢕ%*ꢝ+ꢖ)ꢆꢍꢇꢑꢁ

BAND

(Continued)

Examples:

3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and

FLAG(3-0) is 0000B. The resulting address is 00100000B or 20H. The bit value for the BAND

instruction is 3. Therefore, @H+FLAG = 20H.3:

FLAG

LD

EQU

20H.3

H,#2H

BAND

C,@H+FLAG

; C AND FLAG (20H.3)

ꢉ

ꢔꢕꢁꢖꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢏꢆꢈꢉ^ꢀꢛꢆꢔꢝꢞꢆꢃ','ꢞꢀ

BITR

dst.b

Operand

Operation:

Operation Summary

Bytes

Cycles

DA.b

Clear specified memory bit to logic zero

2

mema.b

memb.@L

@H+DA.b

Description: A BITR instruction clears to logic zero (resets) the specified bit within the destination operand. No

other bits in the destination are affected.

Operand

DA.b

Binary Code

b1 b0

a7 a6 a5 a4 a3 a2 a1 a0

Operation Notation

DA.b ← 0

1

0

1

0

mema.b ← 0

mema.b ꢀ

memb.@L

@H+DA.b

1

0

1

0

1

0

1

0

1

0

1

[memb.7-2 + L3-2].[L.1-0] ← 0

[H + DA.3-0].b ← 0

a5 a4 a3 a2

1

0

b1 b0 a3 a2 a1 a0

Second Byte

Bit Addresses

1

0

1

b1 b0 a3 a2 a1 a0 FB0H-FBFH

ꢀꢅ mema.b

b1 b0 a3 a2 a1 a0 FF0H-FFFH

Examples:

1. If the Bit location 30H.2 in the RAM has a current value of "1". The following instruction

clears the third bit of location 30H to "0":

BITR

30H.2

; 30H.2 ← "0"

2. You can use BITR in the same way to manipulate a port address bit:

BITR

P0.0

; P0.0 ← "0"

ꢔꢕꢁꢄꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢏꢆꢈꢉꢆꢛꢆꢔꢝꢞꢆꢃ','ꢞꢀ

BITR

(Continued)

Examples:

3. For clearing P0.2, P0.3, and P1.0-P1.3 to "0":

LD

L,#2H

BP2

BITR

P0.@L

; First, P0.@2H = P0.2

; (111100B) + 00B.10B = 0F0H.2

INCS

CPSE

JR

L

L,#8H

BP2

4. If bank 0, location 0A0H.0 is cleared (and regardless of whether the EMB value is logic

zero), BITR has the following effect:

FLAG

EQU

0A0H.0

ꢆ

BITR

EMB

ꢆ

LD

BITR

H,#0AH

@H+FLAG

;

Bank 0 (AH + 0H).0 = 0A0H.0 ← "0”

ꢎꢒꢏꢓꢗꢉ ꢚꢊꢑꢍꢄꢅꢒꢃꢄꢅ*2ꢂꢆꢅꢊꢑꢉꢒꢓꢔꢍꢒꢊꢕꢑꢅꢊꢉꢅꢔꢉꢄꢎꢅꢘꢕꢓꢅꢕꢔꢒꢞꢔꢒꢅꢘꢔꢑꢍꢒꢊꢕꢑꢉ$ꢅꢒꢃꢄꢅꢞꢊꢑꢅꢑꢌꢖꢄꢉꢅꢔꢉꢄꢎꢅꢊꢑꢅꢒꢃꢄꢅꢄ9ꢌꢖꢞ ꢄꢉꢅꢌꢏꢕꢙꢄꢅꢖꢌꢐꢅꢍꢃꢌꢑꢗꢄꢅꢘꢕꢓꢅꢅ

ꢅ

ꢎꢊꢘꢘꢄꢓꢄꢑꢒꢅꢎꢄꢙꢊꢍꢄꢉꢅꢊꢑꢅꢒꢃꢄꢅꢚꢛꢈꢜꢝꢅꢞꢓꢕꢎꢔꢍꢒꢅꢘꢌꢖꢊ ꢐꢁꢅ

ꢉ

ꢔꢕꢁꢁꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢏꢆꢈꢁꢆꢛꢆꢔꢝꢞꢆꢈ'ꢞꢀ

BITS

Operation:

dst.b

Operand

Operation Summary

Set specified memory bit

Bytes

Cycles

DA.b

2

mema.b

memb.@L

@H+DA.b

Description: This instruction sets the specified bit within the destination without affecting any other bits in the

destination. BITS can manipulate any bit that is addressable using direct or indirect addressing

modes.

Operand

DA.b

Binary Code

b1 b0

a7 a6 a5 a4 a3 a2 a1 a0

Operation Notation

DA.b ← 1

1

0

1

mema.b ← 1

mema.b ꢀ

memb.@L

@H+DA.b

1

0

1

0

1

0

1

0

1

0

1

[memb.7-2 + L.3-2].b [L.1-0] ← 1

[H + DA.3-0].b ← 1

a5 a4 a3 a2

1

b1 b0 a3 a2 a1 a0

Second Byte

Bit Addresses

1

0

1

b1 b0 a3 a2 a1 a0 FB0H-FBFH

ꢀꢅ mema.b

b1 b0 a3 a2 a1 a0 FF0H-FFFH

Examples:

1. If the bit location 30H.2 in the RAM has a current value of "0", the following instruction sets

the second bit of location 30H to "1".

BITS

30H.2

; 30H.2 ← "1"

2. You can use BITS in the same way to manipulate a port address bit:

BITS

P0.0

; P0.0 ← "1"

ꢔꢕꢁꢌꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢏꢆꢈꢁꢆꢛꢆꢔꢝꢞꢆꢈ'ꢞꢁ

BITS

(Continued)

3. For setting P0.2, P0.3, and P1.0-P1.3 to "1":

Examples:

LD

L,#2H

BP2

BITS

P0.@L

; First, P0.@02H = P0.2

; (111100B) + 00B.10B = 0F0H.2

INCS

CPSE

JR

L

L,#8H

BP2

4. If bank 0, location 0A0H.0, is set to "1" and the EMB = "0", BITS has the following effect:

FLAG

EQU

0A0H.0

EMB

ꢆ

BITR

ꢆ

LD

BITS

H,#0AH

@H+FLAG ; Bank 0 (AH + 0H).0 = 0A0H.0 ← "1"

ꢎꢒꢏꢓꢗꢉ ꢚꢊꢑꢍꢄꢅꢒꢃꢄꢅ*2ꢂꢚꢅꢊꢑꢉꢒꢓꢔꢍꢒꢊꢕꢑꢅꢊꢉꢅꢔꢉꢄꢎꢅꢘꢕꢓꢅꢕꢔꢒꢞꢔꢒꢅꢘꢔꢑꢍꢒꢊꢕꢑꢉ$ꢅꢞꢊꢑꢅꢑꢌꢖꢄꢉꢅꢔꢉꢄꢎꢅꢊꢑꢅꢒꢃꢄꢅꢄ9ꢌꢖꢞ ꢄꢉꢅꢌꢏꢕꢙꢄꢅꢖꢌꢐꢅꢍꢃꢌꢑꢗꢄꢅꢘꢕꢓꢅ

ꢅ

ꢎꢊꢘꢘꢄꢓꢄꢑꢒꢅꢎꢄꢙꢊꢍꢄꢉꢅꢊꢑꢅꢒꢃꢄꢅꢚꢛꢈꢜꢝꢅꢞꢓꢕꢎꢔꢍꢒꢅꢘꢌꢖꢊ ꢐꢁꢅ

ꢉ

ꢔꢕꢁꢔꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢏꢌꢉꢆꢛꢆꢔꢝꢞꢆꢕ%*ꢝ+ꢖ)ꢆꢀꢃꢀ

BOR

C,src.b

Operand

Operation:

Operation Summary

Bytes

Cycles

C,mema.b

C,memb.@L

C,@H+DA.b

Logical-OR carry with specified memory bit

2

Description: The specified bit of the source is logically ORed with the carry flag bit value. The value of the

source is unaffected.

Operand

^C,mema.bꢀ

Binary Code

Operation Notation

C ← C OR mema.b

1

0

1

0

C,memb.@L

C,@H+DA.b

1

0

C ← C OR [memb.7-2 + L.3-2].

[L.1-0]

0

1

0

1

0

1

0

1

a5 a4 a3 a2

0

1

0

C ← C OR [H + DA.3-0].b

b1 b0 a3 a2 a1 a0

Second Byte

Bit Addresses

1

0

1

b1 b0 a3 a2 a1 a0 FB0H-FBFH

ꢀ ^mema.b

b1 b0 a3 a2 a1 a0 FF0H-FFFH

Examples:

1. The carry flag is logically ORed with the P1.0 value:

RCF

BOR

; C ← "0"

C,P1.0

; If P1.0 = "1", then C ← "1"; if P1.0 = "0", then C ← "0"

2. The P1 address is FF1H and register L contains the value 1H (0001B). The address (memb.7-

2) is 111100B and (L.3-2) = 00B. The resulting address is 11110000B or FF0H, specifying P0.

The bit value for the BOR instruction, (L.1-0) is 01B which specifies bit 1. Therefore, P1.@L =

P0.1:

LD

L,#1H

BOR

C,P1.@L

; P1.@L is specified as P0.1; C OR P0.1

ꢆ

ꢔꢕꢁꢘꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢏꢌꢉꢆꢛꢆꢔꢝꢞꢆꢕ%*ꢝ+ꢖ)ꢆꢀꢃꢁ

BOR

(Continued)

Examples:

3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and

FLAG(3-0) is 0000B. The resulting address is 00100000B or 20H. The bit value for the BOR

instruction is 3. Therefore, @H+FLAG = 20H.3:

FLAG

LD

EQU

20H.3

H,#2H

BOR

C,@H+FLAG

; C OR FLAG (20H.3)

ꢉ

ꢔꢕꢁꢃꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢏꢈꢁꢐ^ꢀꢛꢆꢔꢝꢞꢆꢉ',ꢞꢆꢖꢗꢘꢆꢈ#ꢝ$ꢆ%ꢗꢆꢌꢖ),'ꢀ

BTSF

dst.b

Operand

Operation:

Operation Summary

Test specified memory bit and skip if bit equals "0"

Bytes

Cycles

2 + S

DA.b

2

mema.b

memb.@L

@H+DA.b

Description: The specified bit within the destination operand is tested. If it is a "0", the BTSF instruction skips

the instruction which immediately follows it; otherwise the instruction following the BTSF is

executed. The destination bit value is not affected.

Operand

DA.b

Binary Code

b1 b0

a7 a6 a5 a4 a3 a2 a1 a0

Operation Notation

Skip if DA.b = 0

1

0

1

0

1

0

Skip if mema.b = 0

mema.b ꢀ

memb.@L

Skip if [memb.7-2 + L.3-2].

[L.1-0] = 0

0

1

0

1

0

1

0

1

a5 a4 a3 a2

@H + DA.b

1

0

Skip if [H + DA.3-0].b = 0

b1 b0 a3 a2 a1 a0

Second Byte

Bit Addresses

1

0

1

b1 b0 a3 a2 a1 a0 FF0H-FBFH

ꢀ ^mema.b

b1 b0 a3 a2 a1 a0 FF0H-FFFH

Examples:

1. If RAM bit location 30H.2 is set to “0”, the following instruction sequence will cause

program to continue execution from the instruction identifed as LABEL2:

the

BTSF

RET

JP

30H.2

; If 30H.2 = "0", then skip

; If 30H.2 = "1", return

LABEL2

2. You can use BTSF in the same way to test a port pin address bit:

BTSF

RET

JP

P1.0

; If P1.0 = "0", then skip

; If P1.0 = "1", then return

LABEL3

ꢔꢕꢁꢛꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢏꢈꢁꢐꢆꢛꢆꢔꢝꢞꢆꢉ',ꢞꢆꢖꢗꢘꢆꢈ#ꢝ$ꢆ%ꢗꢆꢌꢖ),'ꢀ

BTSF

(Continued)

Examples:

3. P0.2, P0.3 and P1.0-P1.3 are tested:

LD

L,#2H

BP2

BTSF

P0.@L

; First, P1.@02H = P0.2

; (111100B) + 00B.10B = 0F0H.2

RET

INCS

CPSE

JR

L

L,#8H

BP2

4. Bank 0, location 0A0H.0, is tested and (regardless of the current EMB value) BTSF has the

following effect:

FLAG

EQU

0A0H.0

ꢆ

BITR

EMB

ꢆ

LD

H,#0AH

BTSF

@H+FLAG

;

If bank 0 (AH + 0H).0 = 0A0H.0 = "0", then skip

RET

ꢆ

ꢉ

ꢔꢕꢁꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢏꢈꢁꢈꢆꢛꢆꢔꢝꢞꢆꢉ',ꢞꢆꢖꢗꢘꢆꢈ#ꢝ$ꢆ%ꢗꢆꢉ!-'ꢀ

BTST

dst.b

Operation:

Operand

Operation Summary

Test carry bit and skip if set (= "1")

Test specified bit and skip if memory bit is set

Bytes

Cycles

1 + S

2 + S

C

DA.b

1

2

mema.b

memb.@L

@H+DA.b

Description: The specified bit within the destination operand is tested. If it is "1", the instruction that

immediately follows the BTST instruction is skipped; otherwise the instruction following the BTST

instruction is executed. The destination bit value is not affected.

Operand

Binary Code

Operation Notation

Skip if C = 1

Skip if DA.b = 1

C

1

0

1

0

1

0

1

DA.b

b1 b0

a7 a6 a5 a4 a3 a2 a1 a0

1

0

1

Skip if mema.b = 1

mema.b ꢀ

memb.@L

Skip if [memb.7-2 + L.3-2].

[L.1-0] = 1

0

1

0

1

0

1

0

1

a5 a4 a3 a2

@H+DA.b

1

0

1

Skip if [H + DA.3-0].b = 1

b1 b0 a3 a2 a1 a0

Second Byte

Bit Addresses

1

0

1

b1 b0 a3 a2 a1 a0 FB0H-FBFH

ꢀ ^mema.b

b1 b0 a3 a2 a1 a0 FF0H-FFFH

Examples:

1. If RAM bit location 30H.2 is set to “0”, the following instruction sequence will execute the RET

instruction:

BTST

RET

JP

30H.2

; If 30H.2 = "1", then skip

; If 30H.2 = "0", return

LABEL2

ꢔꢕꢌꢜꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢏꢈꢁꢈꢆꢛꢆꢔꢝꢞꢆꢉ',ꢞꢆꢖꢗꢘꢆꢈ#ꢝ$ꢆ%ꢗꢆꢉ!-'ꢀ

BTST

(Continued)

Examples:

2. You can use BTST in the same way to test a port pin address bit:

BTST

RET

JP

P1.0

; If P1.0 = "1", then skip

; If P1.0 = "0", then return

LABEL3

3. P0.2, P0.3 and P1.0-P1.3 are tested:

LD

L,#2H

BP2

BTST

P0.@L

; First, P0.@02H = P0.2

; (111100B) + 00B.10B = 0F0H.2

RET

INCS

CPSE

JR

L

L,#8H

BP2

4. Bank 0, location 0A0H.0, is tested and (regardless of the current EMB value) BTST has the

following effect:

FLAG

EQU

0A0H.0

ꢆ

BITR

EMB

ꢆ

LD

H,#0AH

BTST

@H+FLAG ; If bank 0 (AH + 0H).0 = 0A0H.0 = "1", then skip

RET

ꢆ

ꢉ

ꢔꢕꢌꢖꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢏꢈꢁꢈꢑꢆꢛꢆꢔꢝꢞꢆꢉ',ꢞꢆꢖꢗꢘꢆꢈ#ꢝ$ꢆ%ꢗꢆꢉ!-'.ꢆꢋ)'ꢖ!ꢆꢔꢝꢞꢆ

BTSTZ

dst.b

Operand

Operation:

Operation Summary

Test specified bit; skip and clear if memory bit is set

Bytes

Cycles

2 + S

mema.b

memb.@L

@H+DA.b

2

Description: The specified bit within the destination operand is tested. If it is a "1", the instruction immediately

following the BTSTZ instruction is skipped; otherwise the instruction following the BTSTZ is

executed. The destination bit value is cleared.

Operand

^mema.bꢀ

Binary Code

Operation Notation

Skip if mema.b = 1 and clear

1

0

1

memb.@L

@H+DA.b

1

Skip if [memb.7-2 + L.3-2].

[L.1-0] = 1 and clear

0

1

0

1

0

1

0

1

a5 a4 a3 a2

1

0

1

Skip if [H + DA.3-0].b =1 and clear

b1 b0 a3 a2 a1 a0

Second Byte

Bit Addresses

1

0

1

b1 b0 a3 a2 a1 a0 FB0H-FBFH

ꢀ ^mema.b

b1 b0 a3 a2 a1 a0 FF0H-FFFH

Examples:

1. Port pin P0.0 is toggled by checking the P0.0 value (level):

BTSTZ

BITS

JP

P0.0

; If P0.0 = "1", then P0.0 ← "0" and skip

; If P0.0 = "0", then P0.0 ← "1"

P0.0

LABEL3

2. For toggling P2.2, P2.3, and P3.0-P3.3:

LD

L,#0AH

P2.@L

BP2

BTSTZ

; First, P2.@0AH = P2.2

; (111100B) + 10B.10B = 0F2H.2

BITS

INCS

JR

P2.@L

L

BP2

ꢔꢕꢌꢄꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢏꢈꢁꢈꢑꢆꢛꢆꢔꢝꢞꢆꢉ',ꢞꢆꢖꢗꢘꢆꢈ#ꢝ$ꢆ%ꢗꢆꢉ!-'.ꢆꢋ)'ꢖ!ꢆꢔꢝꢞꢀ

BTSTZ

(Continued)

Examples:

3. Bank 0, location 0A0H.0, is tested and EMB = "0":

FLAG

EQU

0A0H.0

ꢆ

BITR

EMB

ꢆ

LD

H,#0AH

BTSTZ

BITS

@H+FLAG ; If bank 0 (AH + 0H).0 = 0A0H.0 = "1", clear and skip

@H+FLAG ; If 0A0H.0 = "0", then 0A0H.0 ← "1"

ꢉ

ꢔꢕꢌꢁꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢏꢒꢌꢉ^ꢀ^{ꢛꢆꢔꢝꢞꢆꢂ/+)-,ꢝ&'ꢆꢀꢃ}ꢀ

BXOR

C,src.b

Operand

Operation:

Operation Summary

Bytes

Cycles

C,mema.b

C,memb.@L

C,@H+DA.b

Exclusive-OR carry with memory bit

2

Description: The specified bit of the source is logically XORed with the carry bit value. The resultant bit is

written to the carry flag. The source value is unaffected.

Operand

^C,mema.bꢀ

Binary Code

Operation Notation

C ← C XOR mema.b

1

0

1

C,memb.@L

C,@H+DA.b

1

0

C ← C XOR [memb.7-2 + L.3-2].

[L.1-0]

0

1

0

1

0

1

0

1

a5 a4 a3 a2

0

1

C ← C XOR [H + DA.3-0].b

b1 b0 a3 a2 a1 a0

Second Byte

Bit Addresses

1

0

1

b1 b0 a3 a2 a1 a0 FB0H-FBFH

ꢀ ^mema.b

b1 b0 a3 a2 a1 a0 FF0H-FFFH

Examples:

1. The carry flag is logically XORed with the P1.0 value:

RCF

; C ← "0"

BXOR

C,P1.0

; If P1.0 = "1", then C ← "1"; if P1.0 = "0", then C ← "0"

2. The P1 address is FF1H and register L contains the value 1H (0001B). The address (memb.7-

2) is 111100B and (L.3-2) = 00B. The resulting address is 11110000B or FF0H, specifying P0.

The bit value for the BXOR instruction, (L.1-0) is 01B which specifies bit 1. Therefore, P1.@L

= P0.1:

LD

L,#0001B

C,P0.@L

BXOR

; P1.@L is specified as P0.1; C XOR P0.1

ꢔꢕꢌꢌꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢏꢒꢌꢉꢆꢛꢆꢔꢝꢞꢆꢂ/+)-,ꢝ&'ꢆꢀꢃꢁ

BXOR

(Continued)

Examples:

3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and

FLAG(3-0) is 0000B. The resulting address is 00100000B or 20H. The bit value for the BOR

instruction is 3. Therefore, @H+FLAG = 20H.3:

FLAG

LD

EQU

20H.3

H,#2H

BXOR

C,@H+FLAG

; C XOR FLAG (20H.3)

ꢉ

ꢔꢕꢌꢔꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢋꢂꢓꢓꢆꢛꢆꢋꢖ))ꢆꢐ!%+'ꢘ-!'ꢀ

CALL

dst

Operand

ADR

Operation:

Operation Summary

Call direct in page (14 bits)

Bytes

Cycles

3

4

Description: CALL calls a subroutine located at the destination address. The instruction adds three to the

program counter to generate the return address and then pushes the result onto the stack,

decreasing the stack pointer by six. The EMB and ERB are also pushed to the stack. Program

execution continues with the instruction at this address. The subroutine may therefore begin

anywhere in the full 16 K byte program memory address space.

Operand

ADR

Binary Code

Operation Notation

[(SP-1) (SP-2)] ← EMB, ERB

a8 [(SP-3) (SP-4)] ← PC7-0

a0 [(SP-5) (SP-6)] ← PC13-8

1

0

a7

1

0

1

0

1

a13 a12 a11 a10 a9

a4 a3 a2 a1

a6 a5

Example:

The stack pointer value is 00H and the label 'PLAY' is assigned to program memory location

0E3FH. Executing the instruction

CALL PLAY

at location 0123H will generate the following values:

SP

=

0FAH

0H

0FFH

0FEH

0FDH

0FCH

0FBH

0FAH

PC

EMB, ERB

2H

3H

0H

1H

0E3FH

Data is written to stack locations 0FFH-0FAH as follows:

SP - 6

SP - 5

SP - 4

SP - 3

SP - 2

SP - 1

SP →

(0FAH)

(0FBH)

(0FCH)

(0FDH)

(0FEH)

(0FFH)

(00H)

PC11 - PC8

0

PC13 PC12

PC3 - PC0

PC7 - PC4

0

EMB

0

ERB

0

ꢔꢕꢌꢘꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢋꢂꢓꢓꢁꢆꢛꢆꢋꢖ))ꢆꢐ!%+'ꢘ-!'ꢆ0ꢈ %!ꢞ1ꢆ

CALLS

dst

Operand

ADR

Operation:

Operation Summary

Call direct in page (11 bits)

Bytes

Cycles

2

3

Description: The CALLS instruction unconditionally calls a subroutine located at the indicated address. The

instruction increments the PC twice to obtain the address of the following instruction. Then, it

pushes the result onto the stack, decreasing the stack pointer six times. The higher bits of the PC,

with the exception of the lower 11 bits, are cleared. The CALLS instruction can be used in the all

range (0000H-7FFFH), but the subroutine call must therefore be located within the 2 K byte block

(0000H-07FFH) of program memory.

Operand

ADR

Binary Code

Operation Notation

a8 [(SP-1) (SP-2)] ← EMB, ERB

a0 [(SP-3) (SP-4)] ← PC7-0

[(SP-5) (SP-6)] ← PC14-8

1

a7

1

0

1

a10 a9

a6 a5

a4

a3 a2 a1

Example:

The stack pointer value is 00H and the label 'PLAY' is assigned to program memory location

0345H. Executing the instruction

CALLS

PLAY

at location 0123H will generate the following values:

SP

=

0FAH

0H

0FFH

0FEH

0FDH

0FCH

0FBH

0FAH

PC

EMB, ERB

2H

3H

0H

1H

0345H

Data is written to stack locations 0FFH-0FAH as follows:

SP - 6

SP - 5

SP - 4

SP - 3

SP - 2

SP - 1

SP →

(0FAH)

(0FBH)

(0FCH)

(0FDH)

(0FEH)

(0FFH)

(00H)

PC11 - PC8

PC14 PC13 PC12

PC3 - PC0

0

PC7 - PC4

0

EMB

0

ERB

0

ꢉ

ꢔꢕꢌꢃꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢋꢋꢐꢆꢛꢆꢋ%2$)'2'ꢗꢞꢆꢋꢖ!!"ꢆꢌ)ꢖ*ꢀ

CCF

Operation:

Operand

Operation Summary

Complement carry flag

Bytes

Cycles

-

1

Description: The carry flag is complemented; if C = "1" it is changed to C = "0" and vice-versa.

Operand

Binary Code

Operation Notation

-

1

0

1

0

1

0

C ← ꢀ

Example:

If the carry flag is logic zero, the instruction

CCF

changes the value to logic one.

ꢔꢕꢌꢛꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢋꢌꢃꢆꢛꢆꢋ%2$)'2'ꢗꢞꢆꢍ++-2-)ꢖꢞ%!ꢀ

COM

A

Operation:

Operand

Operation Summary

Complement accumulator (A)

Bytes

Cycles

A

2

Description: The accumulator value is complemented; if the bit value of A is "1", it is changed to "0" and vice

versa.

Operand

Binary Code

Operation Notation

A

1

0

1

0

1

0

1

A ← ꢂ

Example:

If the accumulator contains the value 4H (0100B), the instruction

COM

A

leaves the value 0BH (1011B) in the accumulator.

ꢉ

ꢔꢕꢌꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢋꢔꢁꢍ^{ꢆꢛꢆꢋ%2$ꢖ!'ꢆꢖꢗꢘꢆꢈ#ꢝ$ꢆꢝ(ꢆꢂ3-ꢖ)}ꢀ

CPSE

dst,src

Operand

Operation:

Operation Summary

Bytes

Cycles

2 + S

1 + S

2 + S

R,#im

@HL,#im

A,R

A,@HL

EA,@HL

EA,RR

Compare and skip if register equals #im

Compare and skip if indirect data memory equals #im

Compare and skip if A equals R

Compare and skip if A equals indirect data memory

Compare and skip if EA equals indirect data memory

Compare and skip if EA equals RR

2

1

2

Description: CPSE compares the source operand (subtracts it from) the destination operand, and skips the

next instruction if the values are equal. Neither operand is affected by the comparison.

Operand

R,#im

Binary Code

Operation Notation

Skip if R = im

1

0

1

0

1

0

r2

1

0

r1

0

1

r0

1

d3 d2 d1 d0

@HL,#im

A,R

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Skip if (HL) = im

Skip if A = R

d3 d2 d1 d0

1

r2

0

1

0

r1

0

1

r0

0

1

A,@HL

EA,@HL

Skip if A = (HL)

Skip if A = (HL), E = (HL+1)

EA,RR

1

r2

0

r1

0

Skip if EA = RR

Example:

The extended accumulator contains the value 34H and register pair HL contains 56H. The second

instruction (RET) in the instruction sequence

CPSE

RET

EA,HL

is not skipped. That is, the subroutine returns since the result of the comparison is 'not equal.'

ꢔꢕꢔꢜꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢎꢍꢋꢁꢆꢛꢆꢑ'+!'2'ꢗꢞꢆꢖꢗꢘꢆꢈ#ꢝ$ꢆ%ꢗꢆꢔ%!!%ꢜꢁ

DECS

dst

Operand

Operation:

Operation Summary

Decrement register (R); skip on borrow

Decrement register pair (RR); skip on borrow

Bytes

Cycles

1 + S

2 + S

R

RR

1

2

Description: The destination is decremented by one. An original value of 00H will underflow to 0FFH. If a

borrow occurs, a skip is executed. The carry flag value is unaffected.

Operand

Binary Code

Operation Notation

R

RR

0

1

0

1

r2

1

r2

r1

0

r1

r0 R ← R-1; skip on borrow

0

RR ← RR-1; skip on borrow

Examples:

1. Register pair HL contains the value 7FH (01111111B). The following instruction leaves the

value 7EH in register pair HL:

DECS

HL

2. Register A contains the value 0H. The following instruction sequence leaves the value 0FFH

in register A. Since a "borrow" occurs, the 'CALL PLAY1' instruction is skipped and the 'CALL

PLAY2' instruction is executed:

DECS

CALL

A

; "Borrow" occurs

; Skipped

PLAY1

PLAY2

; Executed

ꢉ

ꢔꢕꢔꢖꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢎꢆꢆꢛꢆꢑꢝ,ꢖ4)'ꢆꢄꢗꢞ'!!-$ꢞ,ꢁ

DI

Operation:

Operand

Operation Summary

Disable all interrupts

Bytes

Cycles

-

2

Description: Bit 3 of the interrupt priority register IPR, IME, is cleared to logic zero, disabling all interrupts.

Interrupts can still set their respective interrupt status latches, but the CPU will not directly service

them.

Operand

Binary Code

Operation Notation

IME ← 0

-

1

0

1

0

1

0

1

0

Example:

If the IME bit (bit 3 of the IPR) is logic one (e.g., all instructions are enabled), the instruction

DI

sets the IME bit to logic zero, disabling all interrupts.

ꢔꢕꢔꢄꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢍꢆꢆꢛꢆꢂꢗꢖ4)'ꢆꢄꢗꢞ'!!-$ꢞ,ꢀ

EI

Operation:

Operand

Operation Summary

Enable all interrupts

Bytes

Cycles

-

2

Description: Bit 3 of the interrupt priority register IPR (IME) is set to logic one. This allows all interrupts to be

serviced when they occur, assuming they are enabled. If an interrupt's status latch was previously

enabled by an interrupt, this interrupt can also be serviced.

Operand

Binary Code

Operation Notation

-

1

0

1

0

1

0

1

0

IM ← 1

Example:

If the IME bit (bit 3 of the IPR) is logic zero (e.g., all instructions are disabled), the instruction

EI

sets the IME bit to logic one, enabling all interrupts.

ꢉ

ꢔꢕꢔꢁꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢆꢎꢓꢍꢆꢛꢁꢄꢘ)'ꢆꢀ$'!ꢖꢞꢝ%ꢗꢀ

IDLE

Operation:

Operand

Operation Summary

Engage CPU idle mode

Bytes

Cycles

-

2

Description: IDLE causes the CPU clock to stop while the system clock continues oscillating by setting bit 2 of

the power control register (PCON). After an IDLE instruction has been executed, peripheral hard-

ware remains operative.

In application programs, an IDLE instruction must be immediately followed by at least three NOP

instructions. This ensures an adequate time interval for the clock to stabilize before the next

instruction is executed. If three or more NOP instructions are not used after IDLE instruction,

leakage current could be flown because of the floating state in the internal bus.

Operand

Binary Code

Operation Notation

PCON.2 ← 1

-

1

0

1

0

1

0

1

0

1

Example:

The instruction sequence

IDLE

NOP

sets bit 2 of the PCON register to logic one, stopping the CPU clock. The three NOP instructions

provide the necessary timing delay for clock stabilization before the next instruction in the program

sequence is executed.

ꢔꢕꢔꢌꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢆꢇꢋꢁꢆꢛꢆꢄꢗ+!'2'ꢗꢞꢆꢖꢗꢘꢆꢈ#ꢝ$ꢆ%ꢗꢆꢋꢖ!!"ꢁ

INCS

dst

Operand

Operation:

Operation Summary

Increment register (R); skip on carry

Increment direct data memory; skip on carry

Increment indirect data memory; skip on carry

Increment register pair (RRb); skip on carry

Bytes

Cycles

1 + S

2 + S

1 + S

R

DA

@HL

RRb

1

2

1

Description: The instruction INCS increments the value of the destination operand by one. An original value of

0FH will, for example, overflow to 00H. If a carry occurs, the next instruction is skipped. The carry

flag value is unaffected.

Operand

Binary Code

Operation Notation

R

DA

0

1

0

1

0

1

r2

0

r1

1

r0 R ← R + 1; skip on carry

0

DA ← DA + 1; skip on carry

(HL) ← (HL) + 1; skip on carry

RRb ← RRb + 1; skip on carry

a7 a6 a5 a4 a3 a2 a1 a0

@HL

RRb

1

0

1

0

1

0

1

0

1

0

1

0

r2

0

1

r1

1

0

Example:

Register pair HL contains the value 7EH (01111110B). RAM location 7EH contains 0FH. The

instruction sequence

INCS

@HL

HL

; 7EH ← "0"

; Skip

@HL

; 7EH ← "1"

leaves the register pair HL with the value 7EH and RAM location 7EH with the value 1H. Since a

carry occurred, the second instruction is skipped. The carry flag value remains unchanged.

ꢉ

ꢔꢕꢔꢔꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢆꢉꢍꢈꢆꢛꢆꢃ'ꢞ-!ꢗꢆ(!%2ꢆꢄꢗꢞ'!!-$ꢞꢀ

IRET

Operation:

Operand

Operation Summary

Return from interrupt

Bytes

Cycles

-

1

3

Description: IRET is used at the end of an interrupt service routine. It pops the PC values successively from

the stack and restores them to the program counter. The stack pointer is incremented by six and

the PSW, enable memory bank (EMB) bit, and enable register bank (ERB) bit are also

automatically restored to their pre-interrupt values. Program execution continues from the resulting

address, which is generally the instruction immediately after the point at which the interrupt

request was detected. If a lower-level or same-level interrupt was pending when the IRET was

executed, IRET will be executed before the pending interrupt is processed.

Since the 15th bit of an interrupt start address is not loaded in the PC when the interrupt is

occured, this bit of PC values is always interpreted as a logic zero at that time. The start address

of an interrupt in the ROM must for this reason be located in 0000H-3FFFH.

Operand

Binary Code

Operation Notation

-

1

0

1

0

1

0

1

PC14-8 ← (SP + 1) (SP)

PC7-0 ← (SP + 3) (SP + 2)

PSW ← (SP + 5) (SP + 4)

SP ← SP + 6

Example:

The stack pointer contains the value 0FAH. An interrupt is detected in the instruction at location

0123H. RAM locations 0FDH, 0FCH, and 0FAH contain the values 2H, 3H, and 1H, respectively.

The instruction

IRET

leaves the stack pointer with the value 00H and the program returns to continue execution at

location 0123H.

During a return from interrupt, data is popped from the stack to the program counter. The data in

stack locations 0FFH-0FAH is organized as follows:

SP →

SP + 1

SP + 2

SP + 3

SP + 4

SP + 5

SP + 6

(0FAH)

(0FBH)

(0FCH)

(0FDH)

(0FEH)

(0FFH)

(00H)

PC11 - PC8

PC14 PC13 PC12

PC3 - PC0

0

PC7 - PC4

IS1

C

IS0

SC2

EMB

SC1

ERB

SC0

ꢔꢕꢔꢘꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢕꢔ^ꢀꢛꢆ5-2$ꢀ

JP

dst

Operand

ADR

Operation:

Operation Summary

Jump to direct address (14 bits)

Bytes

Cycles

3

Description: JP causes an unconditional branch to the indicated address by replacing the contents of the

program counter with the address specified in the destination operand. The destination can be

anywhere in the 16 K byte program memory address space.

Operand

ADR

Binary Code

Operation Notation

PC13-0 ← ADR13-0

1

0

a7

1

0

1

0

1

a8

a0

a13 a12 a11 a10 a9

a4 a3 a2 a1

a6 a5

Example:

The label 'SYSCON' is assigned to the instruction at program location 07FFH. The instruction

JP SYSCON

at location 0123H will load the program counter with the value 07FFH.

ꢉ

ꢔꢕꢔꢃꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢕꢔꢁ^ꢀ^{ꢛꢆ5-2$ꢆ0ꢈ %!ꢞ1}ꢀ

JPS

dst

Operand

ADR

Operation:

Operation Summary

Jump direct in page (12 bits)

Bytes

Cycles

2

Description: JPS causes an unconditional branch to the indicated address with the 4 K byte program memory

address space. Bits 0-11 of the program counter are replaced with the directly specified address.

The destination address for this jump is specified to the assembler by a label or by an actual

address in program memory.

Operand

ADR

Binary Code

Operation Notation

a8 PC14-0 ← PC14-12+ADR11-0

a0

1

a7

0

1

a11 a10 a9

a3 a2 a1

a6 a5

a4

Example:

The label 'SUB' is assigned to the instruction at program memory location 00FFH. The instruction

JPS SUB

at location 0EABH will load the program counter with the value 00FFH. Normally, the JPS

instruction jumps to the address in the block in which the instruction is located. If the first byte of

the instruction code is located at address xFFEH or xFFFH, the instruction will jump to the next

block. If the instruction 'JPS SUB' were located instead at program memory address 0FFEH or

0FFFH, the instruction 'JPS SUB' would load the PC with the value 10FFH, causing a program

malfunction.

ꢔꢕꢔꢛꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢕꢉꢆꢛꢆ5-2$ꢆꢃ')ꢖꢞꢝ&'ꢆ0ꢁ'!"ꢆꢈ %!ꢞ1ꢀ

JR

dst

Operand

Operation:

Operation Summary

Branch to relative immediate address

Branch relative to contents of WX register

Branch relative to contents of EA

Bytes

Cycles

#im

@WX

@EA

1

2

3

Description: JR causes the relative address to be added to the program counter and passes control to the

instruction whose address is now in the PC. The range of the relative address is current PC - 15 to

current PC + 16. The destination address for this jump is specified to the assembler by a label, an

actual address, or by immediate data using a plus sign (+) or a minus sign (-).

For immediate addressing, the (+) range is from 2 to 16 and the (-) range is from -1 to -15. If a 0,

1, or any other number that is outside these ranges are used, the assembler interprets it as an

error.

For JR @WX and JR @EA branch relative instructions, the valid range for the relative address is

0H-0FFH. The destination address for these jumps can be specified to the assembler by a label

that lies anywhere within the current 256-byte block.

Normally, the 'JR @WX' and 'JR @EA' instructions jump to the address in the page in which the

instruction is located. However, if the first byte of the instruction code is located at address xxFEH

or xxFFH, the instruction will jump to the next page.

Operand

#im ꢀ

Binary Code

Operation Notation

PC14-0 ← ADR (PC-15 to PC+16)

@WX

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

PC14-0 ← PC14-8 + (WX)

@EA

PC14-0 ← PC14-8 + (EA)

First Byte

Condition

0

1

a3 a2 a1 a0 PC ← PC+2 to PC+16

ꢀꢅꢅJR #im

0

a3 a2 a1 a0 PC ← PC-1 to PC-15

ꢉ

ꢔꢕꢔꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢕꢉꢆꢛꢆ5-2$ꢆꢃ')ꢖꢞꢝ&'ꢆ0ꢁ'!"ꢆꢈ %!ꢞ1ꢀ

JR

(Continued)

Examples:

1. A short form for a relative jump to label 'KK' is the instruction

JR

KK

where 'KK' must be within the allowed range of current PC-15 to current PC+16. The JR

instruction has in this case the effect of an unconditional JP instruction.

2. In the following instruction sequence, if the instruction 'LD WX, #02H' were to be executed in

place of 'LD WX,#00H', the program would jump to 1004H and 'JPS CCC' would be

executed. If 'LD WX,#03H' were to be executed, the jump would be to1006H and 'JPS DDD'

would be executed.

ORG

1000H

JPS

LD

AAA

BBB

CCC

DDD

XXX

WX,#00H ; WX ← 00H

LD

EA,WX

ADS

JR

WX,EA

@WX

; WX ← (WX) + (EA)

; Current PC12-8 (10H) + WX (00H) = 1000H

; Jump to address 1000H and execute JPS AAA

3. Here is another example:

ORG

1100H

LD

A,#0H

A,#1H

A,#2H

A,#3H

30H,A

YYY

LD

; Address 30H ← A

JPS

XXX

LD EA,#00H

JR

; EA ← 00H

@EA

; Jump to address 1100H

; Address 30H ← 00H

If 'LD EA,#01H' were to be executed in place of 'LD EA,#00H', the program would jump to

1101H and address 30H would contain the value 1H. If 'LD EA,#02H' were to be executed, the

jump would be to 1102H and address 30H would contain the value 2H.

ꢔꢕꢘꢜꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢓꢋꢂꢓꢓꢀꢖꢀꢁꢂꢃꢄꢀꢋꢖ))ꢆꢐ!%+'ꢘ-!'ꢀ

CALL

dst

Operand

ADR15

Operation:

Operation Summary

Call direct in page (15 bits)

Bytes

Cycles

3

4

Description: CALL calls a subroutine located at the destination address. The instruction adds three to the

program counter to generate the return address and then pushes the result onto the stack,

decrementing the stack pointer by six. The EMB and ERB are also pushed to the stack. Program

execution continues with the instruction at this address. The subroutine may therefore begin

anywhere in the full 32-Kbyte program memory address space.

The LCALL instruction can be used in the all range (0000H-7FFFH) while the CALL instruction can

be used in the only range (0000H-3FFFH).

Operand

ADR15

Binary Code

Operation Notation

[(SP-1) (SP-2)] ← EMB, ERB

a8 [(SP-3) (SP-4)] ← PC7-0

a0 [(SP-5) (SP-6)] ← PC14-8

1

0

a7

1

0

1

0

1

0

a14 a13 a12 a11 a10 a9

a6 a5 a4 a3 a2 a1

Example:

The stack pointer value is 00H and the label 'PLAY' is assigned to program memory location

5E3FH. Executing the instruction

LCALL

PLAY

at location 0123H will generate the following values:

SP

=

0FAH

0H

0FFH

0FEH

0FDH

0FCH

0FBH

0FAH

PC

EMB, ERB

2H

3H

0H

1H

5E3FH

Data is written to stack locations 0FFH–0FAH as follows:

0FAH

0FBH

0FCH

0FDH

0FEH

0FFH

PC11 – PC8

PC14 PC13 PC12

PC3 – PC0

0

PC7 – PC4

0

EMB

0

ERB

0

ꢉ

ꢔꢕꢘꢖꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢓꢎꢆꢛꢆꢕ%ꢖꢘꢀ

LD

dst,src

Operand

Operation:

Operation Summary

Load 4-bit immediate data to A

Load indirect data memory contents to A

Load direct data memory contents to A

Load register contents to A

Load 4-bit immediate data to register

Load 8-bit immediate data to register

Load contents of A to direct data memory

Load contents of A to register

Load indirect data memory contents to EA

Load direct data memory contents to EA

Load register contents to EA

Bytes

Cycles

A,#im

A,@RRa

A,DA

1

2

1

2

1

2

1

2

A,Ra

Ra,#im

RR,#imm

DA,A

Ra,A

EA,@HL

EA,DA

EA,RRb

@HL,A

DA,EA

RRb,EA

@HL,EA

Load contents of A to indirect data memory

Load contents of EA to data memory

Load contents of EA to register

Load contents of EA to indirect data memory

Description: The contents of the source are loaded into the destination. The source's contents are unaffected.

If an instruction such as 'LD A,#im' (LD EA,#imm) or 'LD HL,#imm' is written more than two

times in succession, only the first LD will be executed; the other similar instructions that

immediately follow the first LD will be treated like a NOP. This is called the 'redundancy effect'

(see examples below).

Operand

A,#im

A,@RRa

A,DA

Binary Code

Operation Notation

1

0

1

0

1

0

d3 d2 d1 d0 A ← im

1

i2

1

i1

0

i0 A ← (RRa)

0

A ← DA

a7 a6 a5 a4 a3 a2 a1 a0

A,Ra

1

0

1

0

1

0

1

0

1

r2

0

r1

0

1

r0

1

A ← Ra

Ra,#im

Ra ← im

d3 d2 d1 d0

r2

r1

r0

ꢔꢕꢘꢄꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢓꢎꢆꢛꢆꢕ%ꢖꢘꢀ

LD

(Continued)

Operand

RR,#imm

Description:

Binary Code

Operation Notation

1

0

r2

r1

1

RR ← imm

d7 d6 d5 d4 d3 d2 d1 d0

DA,A

1

0

1

0

1

DA ← A

a7 a6 a5 a4 a3 a2 a1 a0

Ra,A

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

r2

1

0

1

0

r1

0

1

r0

0

Ra ← A

EA,@HL

EA,DA

EA,RRb

A ← (HL), E ← (HL + 1)

A ← DA, E ← DA + 1

EA ← RRb

a7 a6 a5 a4 a3 a2 a1 a0

1

0

1

0

1

0

1

0

1

r2

1

0

r1

0

1

@HL,A

DA,EA

(HL) ← A

DA ← A, DA + 1 ← E

1

0

a7 a6 a5 a4 a3 a2 a1 a0

RRb,EA

@HL,EA

1

0

1

0

1

0

1

0

1

0

1

0

1

r2

1

0

r1

0

RRb ← EA

(HL) ← A, (HL + 1) ← E

0

Examples:

1. RAM location 30H contains the value 4H. The RAM location values are 40H, 41H and 0AH,

3H respectively. The following instruction sequence leaves the value 40H in point pair HL,

0AH in the accumulator and in RAM location 40H, and 3H in register E.

LD

HL,#30H

A,@HL

; HL ← 30H

; A ← 4H

HL,#40H

EA,@HL

@HL,A

; HL ← 40H

; A ← 0AH, E ← 3H

; RAM (40H) ← 0AH

ꢉ

ꢔꢕꢘꢁꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢓꢎ^{ꢆꢛꢆꢕ%ꢖꢘ}ꢀ

LD

(Continued)

Examples:

2. If an instruction such as LD A,#im (LD EA,#imm) or LD HL,#imm is written more than two

times in succession, only the first LD is executed; the next instructions are treated as NOPs.

Here are two examples of this 'redundancy effect':

LD

A,#1H

EA,#2H

A,#3H

23H,A

; A ← 1H

; NOP

; (23H) ← 1H

LD

HL,#10H

HL,#20H

A,#3H

; HL ← 10H

; NOP

; A ← 3H

; NOP

EA,#35

@HL,A

; (10H) ← 3H

The following table contains descriptions of special characteristics of the LD instruction when used

in different addressing modes:

Instruction

Operation Description and Guidelines

LD A,#im

Since the 'redundancy effect' occurs with instructions like LD EA,#imm, if this

instruction is used consecutively, the second and additional instructions of the

same type will be treated like NOPs.

LD A,@RRa Load the data memory contents pointed to by 8-bit RRa register pairs (HL, WX,

WL) to the A register.

LD A,DA

LD A,Ra

LD Ra,#im

Load direct data memory contents to the A register.

Load 4-bit register Ra (E, L, H, X, W, Z, Y) to the A register.

Load 4-bit immediate data into the Ra register (E, L, H, X, W, Y, Z).

LD RR,#imm Load 8-bit immediate data into the Ra register (EA, HL, WX, YZ). There is a

redundancy effect if the operation addresses the HL or EA registers.

LD DA,A

LD Ra,A

Load contents of register A to direct data memory address.

Load contents of register A to 4-bit Ra register (E, L, H, X, W, Z, Y).

ꢔꢕꢘꢌꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢓꢎꢆꢛꢆꢕ%ꢖꢘꢁ

LD

(Concluded)

Instruction

Examples:

Operation Description and Guidelines

LD EA,@HL Load data memory contents pointed to by 8-bit register HL to the A register, and

the contents of HL+1 to the E register. The contents of register L must be an

even number. If the number is odd, the LSB of register L is recognized as a

logic zero (an even number), and it is not replaced with the true value. For

example, 'LD HL,#36H' loads immediate 36H to HL and the next instruction 'LD

EA,@HL' loads the contents of 36H to register A and the contents of 37H to

register E.

LD EA,DA

Load direct data memory contents of DA to the A register, and the next direct

data memory contents of DA + 1 to the E register. The DA value must be an

even number. If it is an odd number, the LSB of DA is recognized as a logic

zero (an even number), and it is not replaced with the true value. For example,

'LD EA,37H' loads the contents of 36H to the A register and the contents of

37H to the E register.

LD EA,RRb

Load 8-bit RRb register (HL, WX, YZ) to the EA register. H, W, and Y register

values are loaded into the E register, and the L, X, and Z values into the A

register.

LD @HL,A

LD DA,EA

Load A register contents to data memory location pointed to by the 8-bit HL

register value.

Load the A register contents to direct data memory and the E register contents

to the next direct data memory location. The DA value must be an even

number. If it is an odd number, the LSB of the DA value is recognized as logic

zero (an even number), and is not replaced with the true value.

LD RRb,EA

Load contents of EA to the 8-bit RRb register (HL, WX, YZ). The E register is

loaded into the H, W, and Y register and the A register into the L, X, and Z

register.

LD @HL,EA Load the A register to data memory location pointed to by the 8-bit HL register,

and the E register contents to the next location, HL + 1. The contents of the L

register must be an even number. If the number is odd, the LSB of the L

register is recognized as logic zero (an even number), and is not replaced with

the true value. For example, 'LD HL,#36H' loads immediate 36H to register HL;

the instruction 'LD @HL,EA' loads the contents of A into address 36H and the

contents of E into address 37H.

ꢉ

ꢔꢕꢘꢔꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢓꢎꢏ^{ꢆꢛꢆꢕ%ꢖꢘꢆꢔꢝꢞ}ꢀ

LDB

dst,src.b

dst.b,src

Operation:

Operand

mema.b,C

Operation Summary

Load carry bit to a specified memory bit

Load carry bit to a specified indirect memory bit

Bytes

Cycles

2

memb.@L,C

@H+DA.b,C

C,mema.b

C,memb.@L

C,@H+DA.b

Load memory bit to a specified carry bit

Load indirect memory bit to a specified carry bit

Description: The Boolean variable indicated by the first or second operand is copied into the location specified

by the second or first operand. One of the operands must be the carry flag; the other may be any

directly or indirectly addressable bit. The source is unaffected.

Operand

Binary Code

Operation Notation

mema.b ← C

1

0

mema.b,C ꢀ

memb.@L,C

@H+DA.b,C

C,mema.b*

C,memb.@L

C,@H+DA.b

1

0

1

0

1

0

1

0

1

0

1

memb.7-2 + [L.3-2]. [L.1-0] ← C

H + [DA.3-0].b ← (C)

a5 a4 a3 a2

1

0

b1 b0 a3 a2 a1 a0

1

0

1

0

C ← mema.b

1

0

1

0

1

0

1

0

1

0

1

0

1

0

C ← memb.7-2 + [L.3-2] . [L.1-0]

C ← [H + DA.3-0].b

a5 a4 a3 a2

0

1

0

b1 b0 a3 a2 a1 a0

Second Byte

Bit Addresses

1

0

1

b1 b0 a3 a2 a1 a0 FB0H-FBFH

ꢀꢅ mema.b

b1 b0 a3 a2 a1 a0 FF0H-FFFH

ꢔꢕꢘꢘꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢓꢎꢏ^{ꢆꢛꢆꢕ%ꢖꢘꢆꢔꢝꢞ}ꢀ

LDB

(Continued)

Examples:

1. The carry flag is set and the data value at input pin P1.0 is logic zero. The following instruction

clears the carry flag to logic zero.

LDB

C,P1.0

2. The P1 address is FF1H and the L register contains the value 1H (0001B). The address

(memb.7-2) is 111100B and (L.3-2) is 00B. The resulting address is 11110000B or FF0H and

P0 is addressed. The bit value (L.1-0) is specified as 01B (bit 1).

LD

L,#0001B

C,P1.@L

LDB

; P1.@L specifies P0.1 and C ← P0.1

3. The H register contains the value 2H and FLAG = 20H.3. The address for H is 0010B and for

FLAG(3-0) the address is 0000B. The resulting address is 00100000B or 20H. The bit value is

3. Therefore, @H+FLAG = 20H.3.

FLAG

LD

EQU

20H.3

H,#2H

LDB

C,@H+FLAG

; C ← FLAG (20H.3)

4. The following instruction sequence sets the carry flag and the loads the "1" data value to the

output pin P1.0, setting it to output mode:

SCF

LDB

; C ← "1"

P1.0,C

; P1.0 ← "1"

5. The P1 address is FF1H and L = 01H (0001B). The address (memb.7-2) is 111100B and (L.3-

2) is 00B. The resulting address, 11110000B specifies P0. The bit value (L.1-0) is specified as

01B (bit 1). Therefore, P1.@L = P0.1.

SCF

LD

; C ← "1"

L,# 0001B

P1.@L,C

LDB

; P1.@L specifies P0.1

; P0.1 ← "1"

6. In this example, H = 2H and FLAG = 20H.3 and the address 20H is specified. Since the bit

value is 3, @H+FLAG = 20H.3:

FLAG

RCF

LD

EQU

20H.3

; C ← "0"

H,#2H

LDB

@H+FLAG,C

; FLAG(20H.3) ← "0"

ꢎꢒꢏꢓ,ꢅꢅ #ꢕꢓꢒꢅꢞꢊꢑꢅꢑꢌꢖꢄꢉꢅꢔꢉꢄꢎꢅꢊꢑꢅꢄ9ꢌꢖꢞ ꢄꢉꢅꢜꢅꢌꢑꢎꢅ6ꢅꢖꢌꢐꢅꢙꢌꢓꢐꢅ:ꢊꢒꢃꢅꢎꢊꢘꢘꢄꢓꢄꢑꢒꢅꢚꢛꢈꢜꢝꢅꢎꢄꢙꢊꢍꢄꢉꢁꢅ

ꢉ

ꢔꢕꢘꢃꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢓꢎꢋ^{ꢆꢛꢆꢕ%ꢖꢘꢆꢋ%ꢘ'ꢆꢔ"ꢞ'}ꢀ

LDC

dst,src

Operand

Operation:

Operation Summary

Load code byte from WX to EA

Load code byte from EA to EA

Bytes

Cycles

EA,@WX

EA,@EA

1

3

Description: This instruction is used to load a byte from program memory into an extended accumulator. The

address of the byte fetched is the six highest bit values in the program counter and the contents of

an 8-bit working register (either WX or EA). The contents of the source are unaffected.

Operand

EA,@WX

EA,@EA

Binary Code

Operation Notation

EA ← [PC14-8 + (WX)]

EA ← [PC14-8 + (EA)]

1

0

1

0

Examples:

1. The following instructions will load one of four values defined by the define byte (DB) directive

to the extended accumulator:

LD

EA,#00H

DISPLAY

MAIN

CALL

JPS

ORG

0500H

DB

66H

DB

77H

DB

88H

99H

DISPLAY LDC

RET

EA,@EA ; EA ← address 0500H = 66H

If the instruction 'LD EA,#01H' is executed in place of 'LD EA,#00H', The content of 0501H

(77H) is loaded to the EA register. If 'LD EA,#02H' is executed, the content of address 0502H

(88H) is loaded to EA.

ꢔꢕꢘꢛꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢓꢎꢋꢆꢛꢆꢕ%ꢖꢘꢆꢋ%ꢘ'ꢆꢔ"ꢞ'ꢀ

LDC

(Continued)

Examples:

2. The following instructions will load one of four values defined by the define byte (DB) directive

to the extended accumulator:

ORG

0500H

DB

66H

77H

88H

99H

DISPLAY LD

WX,#00H

LDC

RET

EA,@WX ; EA ← address 0500H = 66H

If the instruction 'LD WX,#01H' is executed in place of 'LD WX,#00H', then

EA ← address 0501H = 77H.

If the instruction 'LD WX,#02H' is executed in place of 'LD WX,#00H', then

EA ← address 0502H = 88H.

3. Normally, the LDC EA, @EA and the LDC EA, @WX instructions reference the table data

on the page on which the instruction is located. If, however, the instruction is located at

address xxFFH, it will reference table data on the next page. In this example, the upper 4 bits

of the address at location 0200H is loaded into register E and the lower 4 bits into register A:

ORG

LD

01FDH

01FFH

WX,#00H

LDC

EA,@WX ; E ← upper 4 bits of 0200H address

; A ← lower 4 bits of 0200H address

4. Here is another example of page referencing with the LDC instruction:

ORG

DB

0100H

67H

SMB

LD

0

HL,#30H ; Even number

WX,#00H

LD

LDC

EA,@WX ; E ← upper 4 bits of 0100H address

; A ← lower 4 bits of 0100H address

@HL,EA ; RAM (30H) ← 7, RAM (31H) ← 6

LD

ꢉ

ꢔꢕꢘꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢓꢎꢎꢆꢛꢆꢕ%ꢖꢘꢆꢑꢖꢞꢖꢆꢓ'2%!"ꢆꢖꢗꢘꢆꢑ'+!'2'ꢗꢞꢁ

LDD

dst

Operand

A,@HL

Operation:

Operation Summary

Bytes

Cycles

Load indirect data memory contents to A; decrement

register L contents and skip on borrow

1

2 + S

Description: The contents of a data memory location are loaded into the accumulator, and the contents of the

register L are decreased by one. If a "borrow" occurs (e.g., if the resulting value in register L is

0FH), the next instruction is skipped. The contents of data memory and the carry flag value are not

affected.

Operand

A,@HL

Binary Code

Operation Notation

1

0

1

0

1

A ← (HL), then L ← L-1;

skip if L = 0FH

Example:

In this example, assume that register pair HL contains 20H and internal RAM location 20H

contains the value 0FH:

LD

HL,#20H

A,@HL

XXX

LDD

JPS

; A ← (HL) and L ← L-1

; Skip

YYY

; H ← 2H and L ← 0FH

The instruction 'JPS XXX' is skipped since a "borrow" occurred after the 'LDD A,@HL' and

instruction 'JPS YYY' is executed.

ꢔꢕꢃꢜꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢓꢎꢆꢆꢛꢆꢕ%ꢖꢘꢆꢑꢖꢞꢖꢆꢓ'2%!"ꢆꢖꢗꢘꢆꢄꢗ+!'2'ꢗꢞꢀ

LDI

dst,src

Operand

A,@HL

Operation:

Operation Summary

Bytes

Cycles

Load indirect data memory to A; increment register L

contents and skip on overflow

1

2 + S

Description: The contents of a data memory location are loaded into the accumulator, and the contents of the

register L are incremented by one. If an overflow occurs (e.g., if the resulting value in register L is

0H), the next instruction is skipped. The contents of data memory and the carry flag value are

unaffected.

Operand

A,@HL

Binary Code

Operation Notation

1

0

1

0

1

0

A ← (HL), then L ← L+1;

skip if L = 0H

Example:

Assume that register pair HL contains the address 2FH and internal RAM location 2FH contains

the value 0FH:

LD

HL,#2FH

A,@HL

XXX

LDI

JPS

; A ← (HL) and L ← L+1

; Skip

YYY

; H ← 2H and L ← 0H

The instruction 'JPS XXX' is skipped since an overflow occurred after the 'LDI A,@HL' and the

instruction 'JPS YYY' is executed.

ꢉ

ꢔꢕꢃꢖꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢓꢕꢔꢀꢖꢀꢁꢂꢃꢄꢀ5-2$ꢀ

JP

dst

Operand

ADR15

Operation:

Operation Summary

Jump to direct address (15 bits)

Bytes

Cycles

3

Description: JP causes an unconditional branch to the indicated address by replacing the contents of the

program counter with the address specified in the destination operand. The destination can be

anywhere in the 32-Kbyte program memory address space.

The LJP instruction can be used in the all range (0000H-7FFFH) while the JP instruction can be

used in the only range (0000H-3FFFH).

Operand

ADR15

Binary Code

Operation Notation

PC14-0 ← ADR15

1

0

a7

1

0

1

0

a8

a0

a14 a13 a12 a11 a10 a9

a6 a5 a4 a3 a2 a1

Example:

The label 'SYSCON' is assigned to the instruction at program location 5FFFH. The instruction

LJP SYSCON

at location 0123H will load the program counter with the value 5FFFH.

ꢔꢕꢃꢄꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢇꢌꢔ^{ꢆꢛꢆꢇ%ꢆꢀ$'!ꢖꢞꢝ%ꢗ}ꢀ

NOP

Operation:

Operand

Operation Summary

Bytes

Cycles

–

No operation

1

Description: No operation is performed by a NOP instruction. It is typically used for timing delays.

One NOP causes a 1-cycle delay: with a 1 µs cycle time, five NOPs would therefore cause a 5 µs

delay. Program execution continues with the instruction immediately following the NOP. Only the

PC is affected. At least three NOP instructions should follow a STOP or IDLE instruction.

Operand

Binary Code

Operation Notation

No operation

–

1

0

1

0

Example:

Three NOP instructions follow the STOP instruction to provide a short interval for clock

stabilization before power-down mode is initiated:

STOP

NOP

ꢉ

ꢔꢕꢃꢁꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢌꢉꢆꢛꢆꢕ%*ꢝ+ꢖ)ꢆꢀꢃꢁ

OR

dst,src

Operand

Operation:

Operation Summary

Logical-OR immediate data to A

Logical-OR indirect data memory contents to A

Logical-OR double register to EA

Bytes

Cycles

A, #im

2

1

2

1

2

A, @HL

EA,RR

RRb,EA

Logical-OR EA to double register

Description: The source operand is logically ORed with the destination operand. The result is stored in the

destination. The contents of the source are unaffected.

Operand

A, #im

Binary Code

Operation Notation

A ← A OR im

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

d3 d2 d1 d0

A, @HL

EA,RR

1

0

1

r2

1

0

r1

0

A ← A OR (HL)

EA ← EA OR RR

RRb,EA

RRb ← RRb OR EA

r2

r1

Example:

If the accumulator contains the value 0C3H (11000011B) and register pair HL the value 55H

(01010101B), the instruction

OR

EA,@HL

leaves the value 0D7H (11010111B) in the accumulator .

ꢔꢕꢃꢌꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢔꢌꢔꢆꢛꢆꢐ%$ꢆ(!%2ꢆꢈꢞꢖ+#ꢁ

POP

dst

Operand

Operation:

Operation Summary

Pop to register pair from stack

Pop SMB and SRB values from stack

Bytes

Cycles

RR

SB

1

2

1

2

Description: The contents of the RAM location addressed by the stack pointer is read, and the SP is

incremented by two. The value read is then transferred to the variable indicated by the destination

operand.

Operand

RR

Binary Code

Operation Notation

0

1

0

1

r2

r1

0

RR ← (SP), RR ← (SP+1)

&

;

SP ← SP+2

SB

1

0

1

0

1

0

1

0

1

0

1

0

(SRB) ← (SP), SMB ← (SP+1),

SP ← SP+2

Example:

The SP value is equal to 0EDH, and RAM locations 0EFH through 0EDH contain the values 2H,

3H, and 4H, respectively. The instruction

POP

HL

leaves the stack pointer set to 0EFH and the data pointer pair HL set to 34H.

ꢉ

ꢔꢕꢃꢔꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢔꢊꢁꢗꢆꢛꢆꢐ-, ꢆꢀꢗꢞ%ꢆꢈꢞꢖ+#ꢀ

PUSH

src

Operand

Operation:

Operation Summary

Push register pair onto stack

Push SMB and SRB values onto stack

Bytes

Cycles

RR

SB

1

2

1

2

Description: The SP is then decreased by two and the contents of the source operand are copied into the RAM

location addressed by the stack pointer, thereby adding a new element to the top of the stack.

Operand

RR

Binary Code

Operation Notation

0

1

0

1

r2

r1

1

(SP-1) ← RR , (SP-2) ← RR

;

&

SP ← SP-2

SB

1

0

1

0

1

0

1

0

1

0

1

(SP-1) ← SMB, (SP-2) ← SRB;

(SP) ← SP-2

Example:

As an interrupt service routine begins, the stack pointer contains the value 0FAH and the data

pointer register pair HL contains the value 20H. The instruction

PUSH

HL

leaves the stack pointer set to 0F8H and stores the values 2H and 0H in RAM locations 0F9H and

0F8H, respectively.

ꢔꢕꢃꢘꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢉꢋꢐ^{ꢆꢛꢆꢃ','ꢞꢆꢋꢖ!!"ꢆꢌ)ꢖ*}ꢀ

RCF

Operation:

Operand

Operation Summary

Reset carry flag to logic zero

Bytes

Cycles

–

1

Description: The carry flag is cleared to logic zero, regardless of its previous value.

Operand

Binary Code

Operation Notation

–

1

0

1

0

C ← 0

Example:

Assuming the carry flag is set to logic one, the instruction

RCF

resets (clears) the carry flag to logic zero.

ꢉ

ꢔꢕꢃꢃꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢉꢍꢐꢆꢛꢆꢃ'('!'ꢗ+'ꢆꢄꢗ,ꢞ!-+ꢞꢝ%ꢗꢀ

REF

dst

Operand

memc

ꢎꢒꢏꢓ,ꢅ ꢂꢃꢄꢅꢆ34ꢅꢊꢑꢉꢒꢓꢔꢍꢒꢊꢕꢑꢅꢘꢕꢓꢅꢌꢅꢀ5ꢅ<ꢅ%ꢛ&&ꢅꢊꢑꢉꢒꢓꢔꢍꢒꢊꢕꢑꢅꢊꢉꢅꢜꢅꢍꢐꢍ ꢄꢉꢁꢅ

Operation:

Operation Summary

Bytes

Cycles

3

ꢀꢁꢂꢃꢄꢅ

Reference code

1

Description: The REF instruction is used to rewrite into 1-byte form, arbitrary 2-byte or 3-byte instructions (or

two 1-byte instructions) stored in the REF instruction reference area in program memory. REF

reduces the number of program memory accesses for a program.

Operand

memc

Binary Code

t4 t3

Operation Notation

t0 PC13-0 ← memc.7-4,

memc.3-0 < 1

t7

t6

t5

t2

t1

TJP and TCALL are 2-byte pseudo-instructions that are used only to specify the reference area:

1. When the reference area is specified by the TJP instruction,

memc.7-6 = 00

PC13-0 ← memc.5-0 + (memc + 1).7-0

2. When the reference area is specified by the TCALL instruction,

memc.7-6 = 01

[(SP-1) (SP-2)] ← EMB, ERB

[(SP-3) (SP-4)] ← PC7-0

[(SP-5) (SP-6)] ← PC13-8

SP ← SP-6

PC13-0 ← memc.5-0 + (memc + 1).7-0

When the reference area is specified by any other instruction, the 'memc' and 'memc + 1'

instructions are executed.

Instructions referenced by REF occupy 2 bytes of memory space (for two 1-byte instructions or

one 2-byte instruction) and must be written as an even number from 0020H to 007FH in ROM. In

addition, the destination address of the TJP and TCALL instructions must be located with the

3FFFH address. TJP and TCALL are reference instructions for JP/JPS and CALL/CALLS.

If the instruction following a REF is subject to the 'redundancy effect', the redundant instruction is

skipped. If, however, the REF follows a redundant instruction, it is executed.

On the other hand, the binary code of a REF instruction is 1 byte. The upper 4 bits become the

higher address bits of the referenced instruction, and the lower 4 bits of the referenced instruction

becomes the lower address, producing a total of 8 bits or 1 byte (see Example 3 below).

ꢎꢒꢏꢓ,ꢅ 2ꢘꢅꢒꢃꢄꢅꢈꢚ*ꢅꢙꢌ ꢔꢄꢅꢕꢘꢅꢒꢃꢄꢅꢘꢊꢓꢉꢒꢅꢕꢑꢄ=ꢏꢐꢒꢄꢅꢏꢊꢑꢌꢓꢐꢅꢍꢕꢎꢄꢅꢊꢑꢅꢊꢑꢉꢒꢓꢔꢍꢒꢊꢕꢑꢅꢊꢉꢅ-./$ꢅꢒꢃꢄꢅꢊꢑꢉꢒꢓꢔꢍꢒꢊꢕꢑꢅꢍꢌꢑꢑꢕꢒꢅꢏꢄꢅꢓꢄꢘꢄꢓꢄꢑꢍꢄꢎꢅꢏꢐꢅꢌꢅꢆ34ꢅꢅ

ꢅ

ꢊꢑꢉꢒꢓꢔꢍꢒꢊꢕꢑꢁꢅ

ꢔꢕꢃꢛꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢉꢍꢐꢆꢛꢆꢃ'('!'ꢗ+'ꢆꢄꢗ,ꢞ!-+ꢞꢝ%ꢗꢁ

REF

(Continued)

1. Instructions can be executed efficiently using REF, as shown in the following example:

Examples:

ORG

LD

0020H

AAA

BBB

CCC

DDD

HL,#00H

EA,#FFH

SUB1

LD

TCALL

TJP

ꢆꢉ

SUB2

ꢆ

ORG

REF

0080H

AAA

; LD

HL,#00H

EA,#FFH

BBB

CCC

DDD

; CALL SUB1

; JP

SUB2

2. The following example shows how the REF instruction is executed in relation to LD

instructions that have a 'redundancy effect':

ORG

0020H

AAA

LD

EA,#40H

ꢆ

ORG

LD

REF

ꢆ

0100H

EA,#30H

AAA

; Not skipped

ꢆ

REF

LD

SRB

AAA

EA,#50H ; Skipped

2

ꢉ

ꢔꢕꢃꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢉꢍꢐꢆꢛꢆꢃ'('!'ꢗ+'ꢆꢄꢗ,ꢞ!-+ꢞꢝ%ꢗꢀ

REF

(Concluded)

Examples:

3. In this example the binary code of 'REF A1' at locations 20H-21H is 20H, for 'REF A2' at

locations 22H-23H, it is 21H, and for 'REF A3' at 24H-25H, the binary code is 22H :

Opcode Symbol Instruction

ORG

0020H

83 00

83 03

83 05

83 10

83 26

83 08

83 0F

83 F0

83 67

41 0B

01 0D

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

LD

TCALL

TJP

ꢆ

HL,#00H

HL,#03H

HL,#05H

HL,#10H

HL,#26H

HL,#08H

HL,#0FH

HL,#0F0H

HL,#067H

SUB1

SUB2

ꢆ

ORG

0100H

20

21

22

23

24

25

26

27

30

31

32

REF

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

; LD

; CALL

; JP

HL,#00H

HL,#03H

HL,#05H

HL,#10H

HL,#26H

HL,#08H

HL,#0FH

HL,#0F0H

HL,#067H

SUB1

SUB2

ꢔꢕꢛꢜꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢉꢍꢈꢆꢛꢁꢃ'ꢞ-!ꢗꢆ(!%2ꢆꢈ-4!%-ꢞꢝꢗ'ꢀ

RET

Operation:

Operand

Operation Summary

Return from subroutine

Bytes

Cycles

–

1

3

Description: RET pops the PC values successively from the stack, incrementing the stack pointer by six.

Program execution continues from the resulting address, generally the instruction immediately

following a CALL, LCALL or CALLS.

Operand

Binary Code

Operation Notation

–

1

0

1

0

1

PC14-8 ← (SP+1) (SP)

PC7-0 ← (SP+3) (SP+2)

EMB,ERB ← (SP+5) (SP+4)

SP ← SP+6

Example:

The stack pointer contains the value 0FAH. RAM locations 0FAH, 0FBH, 0FCH, and 0FDH

contain 1H, 0H, 5H, and 2H, respectively. The instruction

RET

leaves the stack pointer with the new value of 00H and program execution continues from location

0125H.

During a return from subroutine, PC values are popped from stack locations as follows:

SP →

SP + 1

SP + 2

SP + 3

SP + 4

SP + 5

SP + 6

(0FAH)

(0FBH)

(0FCH)

(0FDH)

(0FEH)

(0FFH)

(000H)

PC11 - PC8

PC14 PC13 PC12

PC3 - PC0

0

PC7 - PC4

0

EMB

0

ERB

0

ꢉ

ꢔꢕꢛꢖꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢉꢉꢋ^{ꢆꢛꢆꢃ%ꢞꢖꢞ'ꢆꢍ++-2-)ꢖꢞ%!ꢆꢃꢝ* ꢞꢆꢞ !%-* ꢆꢋꢖ!!"}ꢀ

RRC

A

Operation:

Operand

Operation Summary

Rotate right through carry bit

Bytes

Cycles

A

1

Description: The four bits in the accumulator and the carry flag are together rotated one bit to the right. Bit 0

moves into the carry flag and the original carry value moves into the bit 3 accumulator position.

+

.

%

Operand

Binary Code

Operation Notation

C ← A.0, A3 ← C

A.n-1 ← A.n (n = 1, 2, 3)

A

1

0

1

0

Example:

The accumulator contains the value 5H (0101B) and the carry flag is cleared to logic zero. The

instruction

RRC

A

leaves the accumulator with the value 2H (0010B) and the carry flag set to logic one.

ꢔꢕꢛꢄꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢁꢏꢋꢆꢛꢆꢈ-4ꢞ!ꢖ+ꢞꢆꢜꢝꢞ ꢆꢋꢖ!!"ꢀ

SBC

dst,src

Operand

Operation:

Operation Summary

Bytes

Cycles

A,@HL

EA,RR

RRb,EA

Subtract indirect data memory from A with carry

Subtract register pair (RR) from EA with carry

Subtract EA from register pair (RRb) with carry

1

2

1

2

Description: SBC subtracts the source and carry flag value from the destination operand, leaving the result in

the destination. SBC sets the carry flag if a borrow is needed for the most significant bit; otherwise

it clears the carry flag. The contents of the source are unaffected.

If the carry flag was set before the SBC instruction was executed, a borrow was needed for the

previous step in multiple precision subtraction. In this case, the carry bit is subtracted from the

destination along with the source operand.

Operand

A,@HL

EA,RR

Binary Code

Operation Notation

C,A ← A - (HL) - C

C, EA ← EA -RR - C

0

1

0

1

0

1

0

1

0

1

0

1

r2

1

0

r1

0

RRb,EA

C,RRb ← RRb - EA - C

r2

r1

Examples:

1. The extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and

the carry flag is set to "1":

SCF

SBC

JPS

; C ← "1"

EA,HL

XXX

; EA ← 0C3H - 0AAH - 1H, C ← "0"

; Jump to XXX; no skip after SBC

2. If the extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and

the carry flag is cleared to "0":

RCF

SBC

JPS

; C ← "0"

EA,HL

XXX

; EA ← 0C3H - 0AAH - 0H = 19H, C ← "0"

; Jump to XXX; no skip after SBC

ꢉ

ꢔꢕꢛꢁꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢁꢏꢋꢆꢛꢆꢈ-4ꢞ!ꢖ+ꢞꢆꢜꢝꢞ ꢆꢋꢖ!!"ꢀ

SBC

(Continued)

Examples:

3. If SBC A,@HL is followed by an ADS A,#im, the SBC skips on 'no borrow' to the instruction

immediately after the ADS. An 'ADS A,#im' instruction immediately after the 'SBC A,@HL'

instruction does not skip even if an overflow occurs. This function is useful for decimal

adjustment operations.

a. 8 - 6 decimal addition (the contents of the address specified by the HL register is 6H):

RCF

LD

; C ← "0"

A,#8H

A,@HL

A,#0AH

XXX

; A ← 8H

SBC

ADS

JPS

; A ← 8H - 6H - C(0) = 2H, C ← "0"

; Skip this instruction because no borrow after SBC result

b. 3 - 4 decimal addition (the contents of the address specified by the HL register is 4H):

RCF

LD

; C ← "0"

A,#3H

; A ← 3H

SBC

ADS

A,@HL

A,#0AH

; A ← 3H - 4H - C(0) = 0FH, C ← "1"

; No skip. A ← 0FH + 0AH = 9H

; (The skip function of 'ADS A,#im' is inhibited after a

; 'SBC A,@HL' instruction even if an overflow occurs.)

JPS

XXX

ꢔꢕꢛꢌꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢁꢏꢁꢆꢛꢆꢈ-4ꢞ!ꢖ+ꢞꢀ

SBS

dst,src

Operand

Operation:

Operation Summary

Bytes

Cycles

1 + S

2 + S

A,@HL

EA,RR

RRb,EA

Subtract indirect data memory from A; skip on borrow

Subtract register pair (RR) from EA; skip on borrow

Subtract EA from register pair (RRb); skip on borrow

1

2

Description: The source operand is subtracted from the destination operand and the result is stored in the

destination. The contents of the source are unaffected. A skip is executed if a borrow occurs. The

value of the carry flag is not affected.

Operand

A,@HL

EA,RR

Binary Code

Operation Notation

A ← A - (HL); skip on borrow

EA ← EA - RR; skip on borrow

0

1

0

1

0

1

0

1

0

1

0

1

0

1

r2

1

0

r1

0

1

0

RRb,EA

RRb ← RRb - EA; skip on borrow

r2

r1

Examples:

1. The accumulator contains the value 0C3H, register pair HL contains the value 0C7H, and the

carry flag is cleared to logic zero:

RCF

SBS

; C ← "0"

EA,HL

; EA ← 0C3H - 0C7H

; SBS instruction skips on borrow,

; but carry flag value is not affected

; Skip because a borrow occurred

; Jump to YYY is executed

JPS

XXX

YYY

2. The accumulator contains the value 0AFH, register pair HL contains the value 0AAH, and the

carry flag is set to logic one:

SCF

SBS

JPS

; C ← "1"

EA,HL

XXX

; EA ← 0AFH - 0AAH

; Jump to XXX

; JPS was not skipped since no "borrow" occurred after

; SBS

ꢉ

ꢔꢕꢛꢔꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢁꢋꢐꢆꢛꢆꢈ'ꢞꢆꢋꢖ!!"ꢆꢌ)ꢖ*ꢀ

SCF

Operation:

Operand

Operation Summary

Set carry flag to logic one

Bytes

Cycles

–

1

Description: The SCF instruction sets the carry flag to logic one, regardless of its previous value.

Operand

Binary Code

Operation Notation

–

1

0

1

C ← 1

Example:

If the carry flag is cleared to logic zero, the instruction

SCF

sets the carry flag to logic one.

ꢔꢕꢛꢘꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢁꢃꢏꢆꢛꢆꢈ')'+ꢞꢆꢓ'2%!"ꢆꢔꢖꢗ#ꢀ

SMB

n

Operation:

Operand

Operation Summary

Select memory bank

Bytes

Cycles

n

2

Description: The SMB instruction sets the upper four bits of a 12-bit data memory address to select a specific

memory bank. The constants 0, n, and 15 are usually used as the SMB operand to select the

corresponding memory bank. All references to data memory addresses fall within the following

address ranges:

Please note that since data memory spaces differ for various devices in the SAM4 product family,

the 'n' value of the SMB instruction will also vary.

Addresses

000H-01FH

Register Areas

Working registers

Bank

0

SMB

0

020H-0FFH

n00H-nFFH

Stack and general-purpose registers

General-purpose registers

n

(n = 1-14) (n = 1-14)

F80H-FFFH

I/O-mapped hardware registers

15

The enable memory bank (EMB) flag must always be set to "1" in order for the SMB instruction to

execute successfully for memory banks 0-15.

Format

Binary Code

Operation Notation

SMB ← n (n = 0-15)

n

1

0

1

0

1

0

1

0

1

d3 d2 d1 d0

Example:

If the EMB flag is set, the instruction

SMB

selects the data memory address range for bank 0 (000H-0FFH) as the working memory bank.

0

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ꢉ

ꢔꢕꢛꢃꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢁꢉꢏ^ꢉꢛꢆꢈ')'+ꢞꢆꢃ'*ꢝ,ꢞ'!ꢆꢔꢖꢗ#ꢅ

SRB

n

Operation:

Operand

Operation Summary

Select register bank

Bytes

Cycles

n

2

Description: The SRB instruction selects one of four register banks in the working register memory area. The

constant value used with SRB is 0, 1, 2, or 3. The following table shows the effect of SRB settings:

ERB Setting

SRB Settings

Selected Register Bank

3

0

2

0

1

x

0

1

0

x

0

1

0

1

0

1

Always set to bank 0

Bank 0

0

Bank 1

Bank 2

Bank 3

ꢎꢒꢏꢓ,ꢅ >9>ꢅ1ꢅꢑꢕꢒꢅꢌꢞꢞ ꢊꢍꢌꢏ ꢄꢁꢅ

The enable register bank flag (ERB) must always be set for the SRB instruction to execute

successfully for register banks 0, 1, 2, and 3. In addition, if the ERB value is logic zero, register

bank 0 is always selected, regardless of the SRB value.

Operand

Binary Code

Operation Notation

n

1

0

1

0

1

0

1

0

1

SRB ← n (n = 0, 1, 2, 3)

d1 d0

Example:

If the ERB flag is set, the instruction

SRB

3

selects register bank 3 (018H-01FH) as the working memory register bank.

ꢔꢕꢛꢛꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢁꢉꢍꢈꢆꢛꢆꢃ'ꢞ-!ꢗꢆ(!%2ꢆꢈ-4!%-ꢞꢝꢗ'ꢆꢖꢗꢘꢆꢈ#ꢝ$ꢀ

SRET

Operation:

Operand

Operation Summary

Return from subroutine and skip

Bytes

Cycles

3 + S

–

1

Description: SRET is normally used to return to the previously executing procedure at the end of a subroutine

that was initiated by a CALL, LCALL or CALLS instruction. SRET skips the resulting address,

which is generally the instruction immediately after the point at which the subroutine was called.

Then, program execution continues from the resulting address and the contents of the location

addressed by the stack pointer are popped into the program counter.

Operand

Binary Code

Operation Notation

–

1

0

1

0

1

PC14-8 ← (SP+1) (SP)

PC7-0 ← (SP+3) (SP+2)

EMB,ERB ← (SP+5) (SP+4)

SP ← SP+6

Example:

If the stack pointer contains the value 0FAH and RAM locations 0FAH, 0FBH, 0FCH, and 0FDH

contain the values 1H, 0H, 5H, and 2H, respectively, the instruction

SRET

leaves the stack pointer with the value 00H and the program returns to continue execution at

location 0125H, then skips unconditionally.

During a return from subroutine, data is popped from the stack to the PC as follows:

SP →

(0FAH)

PC11 - PC8

SP + 1

SP + 2

SP + 3

SP + 4

SP + 5

SP + 6

(0FBH)

(0FCH)

(0FDH)

(0FEH)

(0FFH)

(000H)

0

PC14 PC13 PC12

PC3 - PC0

PC7 - PC4

0

EMB

0

ERB

0

ꢉ

ꢔꢕꢛꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢁꢈꢌꢔꢆꢛꢆꢈꢞ%$ꢆꢀ$'!ꢖꢞꢝ%ꢗꢀ

STOP

Operation:

Operand

Operation Summary

Engage CPU stop mode

Bytes

Cycles

–

2

Description: The STOP instruction stops the system clock by setting bit 3 of the power control register (PCON)

to logic one. When STOP executes, all system operations are halted with the exception of some

peripheral hardware with special power-down mode operating conditions.

In application programs, a STOP instruction must be immediately followed by at least three NOP

instructions. This ensures an adequate time interval for the clock to stabilize before the next

instruction is executed. If three or more NOP instructions are not used after STOP instruction,

leakage current could be flown because of the floating state in the internal bus.

Operand

Binary Code

Operation Notation

PCON.3 ← 1

–

1

0

1

0

1

0

1

Example:

Given that bit 3 of the PCON register is cleared to logic zero, and all systems are operational, the

instruction sequence

STOP

NOP

sets bit 3 of the PCON register to logic one, stopping all controller operations (with the exception

of some peripheral hardware). The three NOP instructions provide the necessary timing delay for

clock stabilization before the next instruction in the program sequence is executed.

ꢔꢕꢆꢜꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢘꢍꢇꢈꢆꢛꢆꢕ%ꢖꢘꢆꢂꢓꢔ6ꢆꢂꢃꢔ6ꢆꢖꢗꢘꢆꢁ'+ꢞ%!ꢆꢍꢘꢘ!',,ꢀ

VENTn

dst

Operand

Operation:

Operation Summary

Bytes

Cycles

EMB (0,1)

ERB (0,1)

ADR

Load enable memory bank flag (EMB) and the enable

register bank flag (ERB) and program counter to

vector address, then branch to the corresponding

location.

2

Description: The VENT instruction loads the contents of the enable memory bank flag (EMB) and enable

register bank flag (ERB) into the respective vector addresses. It then points the interrupt service

routine to the corresponding branching locations. The program counter is loaded automatically

with the respective vector addresses which indicate the starting address of the respective vector

interrupt service routines.

The EMB and ERB flags should be modified using VENT before the vector interrupts are

acknowledged. Then, when an interrupt is generated, the EMB and ERB values of the previous

routine are automatically pushed onto the stack and then popped back when the routine is

completed.

After the return from interrupt (IRET) you do not need to set the EMB and ERB values again.

Instead, use BITR and BITS to clear these values in your program routine.

The starting addresses for vector interrupts and reset operations are pointed to by the VENTn

instruction. These starting addresses must be located in ROM ranges 0000H-3FFFH. Generally,

the VENTn instructions are coded starting at location 0000H.

The format for VENT instructions is as follows:

VENTn

d1,d2,ADDR

EMB ← d1 ("0" or "1")

ERB ← d2 ("0" or "1")

PC ← ADDR (address to branch

n = device-specific module address code (n = 0-n)

Operand

Binary Code

Operation Notation

EMB (0,1)

ERB (0,1)

ADR

E

M

B

E

R

B

a13 a12 a11 a10 a9

a8 ROM (2 x n) 7-6 → EMB, ERB

ROM (2 x n) 5-4 → PC13-12

ROM (2 x n) 3-0 → PC11-8

ROM (2 x n + 1) 7-0 → PC7-0

(n = 0, 1, 2, 3, 4, 5, 6, 7)

a7

a6 a5

a4

a3 a2

a1

a0

ꢉ

ꢔꢕꢆꢖꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢘꢍꢇꢈꢆꢛꢆꢕ%ꢖꢘꢆꢂꢓꢔ6ꢆꢂꢃꢔ6ꢆꢖꢗꢘꢆꢁ'+ꢞ%!ꢆꢍꢘꢘ!',,ꢀ

VENTn

(Continued)

Example:

The instruction sequence

ORG

0000H

VENT0

VENT1

VENT2

VENT3

VENT4

VENT6

VENT7

1,0,RESET

0,1,INTA

0,1,INTB

0,1,INTC

0,1,INTD

0,1,INTE

0,1,INTF

causes the program sequence to branch to the RESET routine labeled 'RESET', setting EMB to

"1" and ERB to "0" when ꢃꢄꢅꢄꢆ is activated. When a basic timer interrupt is generated, VENT1

causes the program to branch to the basic timer's interrupt service routine, INTA, and to set the

EMB value to "0" and the ERB value to "1". VENT2 then branches to INTB, VENT3 to INTC, and

so on, setting the appropriate EMB and ERB values.

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ꢞꢓꢕꢎꢔꢍꢒꢅꢘꢌꢖꢊ ꢐꢁꢅ

ꢅ

ꢔꢕꢆꢄꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢒꢋꢗꢆꢛꢆꢂ/+ ꢖꢗ*'ꢆꢍꢆ%!ꢆꢂꢍꢆꢜꢝꢞ ꢆꢇꢝ44)'ꢆ%!ꢆꢔ"ꢞ'ꢀ

XCH

dst,src

Operand

Operation:

Operation Summary

Bytes

Cycles

A,DA

A,Ra

A,@RRa

EA,DA

EA,RRb

EA,@HL

Exchange A and data memory contents

Exchange A and register (Ra) contents

Exchange A and indirect data memory

Exchange EA and direct data memory contents

Exchange EA and register pair (RRb) contents

Exchange EA and indirect data memory contents

2

1

2

1

2

Description: The instruction XCH loads the accumulator with the contents of the indicated destination variable

and writes the original contents of the accumulator to the source.

Operand

A,DA

Binary Code

Operation Notation

A ↔ DA

0

1

0

1

a7 a6 a5 a4 a3 a2 a1 a0

A,Ra

A,@RRa

EA,DA

0

1

0

1

0

1

r2

i2

1

r1

i1

1

r0 A ↔ Ra

i0 A ↔ (RRa)

A ↔ DA,E ↔ DA + 1

1

a7 a6 a5 a4 a3 a2 a1 a0

EA,RRb

EA,@HL

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

r2

1

0

r1

0

1

EA ↔ RRb

A ↔ (HL), E ↔ (HL + 1)

0

Example:

Double register HL contains the address 20H. The accumulator contains the value 3FH

(00111111B) and internal RAM location 20H the value 75H (01110101B). The instruction

XCH

EA,@HL

leaves RAM location 20H with the value 3FH (00111111B) and the extended accumulator with the

value 75H (01110101B).

ꢉ

ꢔꢕꢆꢁꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢒꢋꢗꢎꢆꢛꢆꢂ/+ ꢖꢗ*'ꢆꢖꢗꢘꢆꢑ'+!'2'ꢗꢞꢀ

XCHD

dst,src

Operand

A,@HL

Operation:

Operation Summary

Bytes

Cycles

Exchange A and data memory contents; decrement

contents of register L and skip on borrow

1

2 + S

Description: The instruction XCHD exchanges the contents of the accumulator with the RAM location

addressed by register pair HL and then decrements the contents of register L. If the content of

register L is 0FH, the next instruction is skipped. The value of the carry flag is unaffected.

Operand

A,@HL

Binary Code

Operation Notation

0

1

0

1

A ↔ (HL), then L ← L-1;

skip if L = 0FH

Example:

Register pair HL contains the address 20H and internal RAM location 20H contains the value 0FH:

LD

HL,#20H

A,#0H

A,@HL

XXX

LD

XCHD

; A ← 0FH and L ← L - 1, (HL) ← "0"

; Skipped since a borrow occurred

; H ← 2H, L ← 0FH

JPS

YYY

XCHD

A,@HL

; (2FH) ← 0FH, A ← (2FH), L ← L - 1 = 0EH

ꢆ

The 'JPS YYY' instruction is executed since a skip occurs after the XCHD instruction.

ꢔꢕꢆꢌꢉ

ꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢒꢋꢗꢆꢆꢛꢆꢂ/+ ꢖꢗ*'ꢆꢖꢗꢘꢆꢄꢗ+!'2'ꢗꢞꢁ

XCHI

dst,src

Operand

A,@HL

Operation:

Operation Summary

Bytes

Cycles

Exchange A and data memory contents; increment

contents of register L and skip on overflow

1

2 + S

Description: The instruction XCHI exchanges the contents of the accumulator with the RAM location addressed

by register pair HL and then increments the contents of register L. If the content of register L is 0H,

a skip is executed. The value of the carry flag is unaffected.

Operand

A,@HL

Binary Code

Operation Notation

0

1

0

1

0

A ↔ (HL), then L ← L+1;

skip if L = 0H

Example:

Register pair HL contains the address 2FH and internal RAM location 2FH contains 0FH:

LD

XCHI

JPS

XCHI

ꢆ

HL,#2FH

A,#0H

A,@HL

XXX

; A ← 0FH and L ← L + 1 = 0, (HL) ← "0"

; Skipped since an overflow occurred

; H ← 2H, L ← 0H

YYY

A,@HL

; (20H) ← 0FH, A ← (20H), L ← L + 1 = 1H

ꢆ

The 'JPS YYY' instruction is executed since a skip occurs after the XCHI instruction.

ꢉ

ꢔꢕꢆꢔꢉ

ꢀꢊꢋꢌꢃꢉꢍꢎꢀꢏꢐꢑꢂꢏꢍꢒꢎꢉꢀꢓꢏꢉ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ

ꢀꢁꢂ^{ꢆꢛꢆꢕ%*ꢝ+ꢖ)ꢆꢂ/+)-,ꢝ&'ꢆꢀꢃ}ꢀ

XOR

dst,src

Operand

Operation:

Operation Summary

Exclusive-OR immediate data to A

Exclusive-OR indirect data memory to A

Exclusive-OR register pair (RR) to EA

Exclusive-OR register pair (RRb) to EA

Bytes

Cycles

A,#im

2

1

2

1

2

A,@HL

EA,RR

RRb,EA

Description: XOR performs a bitwise logical XOR operation between the source and destination variables and

stores the result in the destination. The source contents are unaffected.

Operand

A,#im

Binary Code

Operation Notation

A ← A XOR im

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

d3 d2 d1 d0

A,@HL

EA,RR

1

0

1

0

1

r2

1

0

r1

0

1

0

A ← A XOR (HL)

EA ← EA XOR (RR)

RRb,EA

RRb ← RRb XOR EA

r2

r1

Example:

If the extended accumulator contains 0C3H (11000011B) and register pair HL contains 55H

(01010101B), the instruction

XOR

EA,HL

leaves the value 96H (10010110B) in the extended accumulator.

ꢔꢕꢆꢘꢉ

ꢉ


型号：	S3C72G9
厂家：	SAMSUNG
描述：	SAM47 INSTRUCTION SET SAM47指令集
文件：	总96页 (文件大小：1006K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S3C72G9 [SAMSUNG]

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